JP2903162B2 - Distributed amplifier - Google Patents
Distributed amplifierInfo
- Publication number
- JP2903162B2 JP2903162B2 JP30508789A JP30508789A JP2903162B2 JP 2903162 B2 JP2903162 B2 JP 2903162B2 JP 30508789 A JP30508789 A JP 30508789A JP 30508789 A JP30508789 A JP 30508789A JP 2903162 B2 JP2903162 B2 JP 2903162B2
- Authority
- JP
- Japan
- Prior art keywords
- transmission line
- capacitor
- bias
- resistor
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はモノリシックIC化に適した分布増幅器に関す
るものである。Description: TECHNICAL FIELD The present invention relates to a distributed amplifier suitable for making a monolithic IC.
（従来の技術） 第３図にモノリシックが可能な分布増幅器の基本回路
を示す。図において、1,2はそれぞれ入力，出力端子、3
1〜3nはFETトランジスタ、40〜4nはFETのドレイン側の
伝送線路、50〜5nはFETのゲート側の伝送線路、6,7はそ
れぞれドレイン側，ゲート側の終端抵抗を示す。ここ
で、40,4nの伝送線路は41〜４（ｎ−１）の伝送線路の1
/2長、50,5nの伝送線路は51〜５（ｎ−１）の伝送線路
の1/2長を与えている。分布増幅器は第３図に示すよう
にソース接地FETの入力端子または出力端子とグランド
間の寄生容量を伝送線路の一部とすることにより、広帯
域な特性を示す。ところが分布増幅器の１段当たりの利
得は10dB以下の比較的小さい値で、実際に適用する場
合、多段化して用いる。ここで分布増幅器ICの多段化実
装に通した回路構成として第４図に示すような分布増幅
器が提案されている。(Prior Art) FIG. 3 shows a basic circuit of a distributed amplifier capable of being monolithic. In the figure, 1 and 2 are input and output terminals, 3
1 to 3n are FET transistors, 40 to 4n are transmission lines on the drain side of the FET, 50 to 5n are transmission lines on the gate side of the FET, and 6, 7 are terminal resistances on the drain side and the gate side, respectively. Here, 40,4n transmission lines are one of 41 to 4 (n-1) transmission lines.
The / 2 length, 50,5n transmission line provides 1/2 the length of the 51 to 5 (n-1) transmission line. As shown in FIG. 3, the distributed amplifier exhibits a wide band characteristic by using the parasitic capacitance between the input terminal or output terminal of the common source FET and the ground as a part of the transmission line. However, the gain per stage of the distributed amplifier is a relatively small value of 10 dB or less. Here, a distributed amplifier as shown in FIG. 4 has been proposed as a circuit configuration for multistage mounting of a distributed amplifier IC.
図において１は入力端子、２は出力端子、31〜3nはFE
Tトランジスタ、40〜4nはFETのドレイン側の伝送線路、
50〜5nはFETのゲート側の伝送線路、6,7はそれぞれドレ
イン側，ゲート側の終端抵抗、8,9はそれぞれドレイン
及びゲート用のバイアス端子、10〜13は容量を示す。10
〜13の容量値は使用帯域内で特性を満たす値が与えられ
る。このような構成となっているので、第４図の分布増
幅器をIC化し、多段実装した構成は第５図に示すように
なる。In the figure, 1 is an input terminal, 2 is an output terminal, 31 to 3n are FE
T transistor, 40 ~ 4n is transmission line on the drain side of FET,
Reference numerals 50 to 5n denote transmission lines on the gate side of the FET, reference numerals 6 and 7 denote termination resistors on the drain side and gate side, reference numerals 8 and 9 denote bias terminals for the drain and gate, and reference numerals 10 to 13 denote capacitance. Ten
Capacitance values of 1313 are given values that satisfy the characteristics within the used band. With such a configuration, the distributed amplifier shown in FIG. 4 is integrated into an IC and mounted in multiple stages as shown in FIG.
図において、14はIC実装治具あるいはパッケージ、1
5,16は入力及び出力端子、17,18はそれぞれドレイン及
びゲートバイアス用端子、19は第４図の分布増幅器をIC
化したチップ、20,21はバイアス用チップコンデンサ、2
2,23は入出力接続用伝送線路、24は入出力間接続用のボ
ンディングワイヤLIO,25,27はそれぞれドレイン及びゲ
ートバイアス用のボンディングワイヤLD,LG、26,28はチ
ップコンデンサからドレイン，ゲートバイアス端子への
接続用のボンディングワイヤLDGを示す。バイアス用チ
ップコンデンサの裏面は治具の接地面と接着して接続さ
れている。In the figure, 14 is an IC mounting jig or package, 1
5 and 16 are input and output terminals, 17 and 18 are drain and gate bias terminals respectively, and 19 is the distributed amplifier shown in Fig. 4.
Chips, 20 and 21 are bias chip capacitors, 2
2,23 transmission lines for input and output connections, 24 bonding wire L IO for input and output connections, the bonding wires L D for each drain and gate bias 25, 27, L G, 26, 28 from the chip capacitor The bonding wire LDG for connection to the drain and gate bias terminals is shown. The back surface of the bias chip capacitor is bonded and connected to the ground surface of the jig.
この構造によれば、チップ間接続が直近で出来、入出
力間でのバイアス回路が不用なため、実装が容易とな
る。ここで、これらの部品をマイクロ波用パッケージ，
治具等に実装することを考えると、現状で実装可能な市
販のチップコンデンサは最大130pF程度である。いま１
つのチップの実装を含めた等価回路を第６図に示す。ゲ
ート及びドレインバイアス側のボンディングワイヤのイ
ンダクタンスLG及びLDを0.5nH程度とし、バイパスコン
デンサCBPを130pFとすると、LG,CBPおよびLD,CBPより直
列共振が生じ、その共振点は 1/2π（LGCBP）1/2＝1/2π（LDCBP）1/2 …… （この場合、約624MHZ） で与えられる。従って、共振点付近で急激に入力のイン
ピーダンスが変化するため、それに伴って利得の周波数
特性も変化を受け、帯域の平坦性が劣化する。According to this structure, connection between chips can be made immediately, and a bias circuit between input and output is unnecessary, so that mounting becomes easy. Here, these parts are used for microwave package,
Considering mounting on a jig or the like, currently available commercially available chip capacitors have a maximum of about 130 pF. Now 1
FIG. 6 shows an equivalent circuit including the mounting of one chip. When the inductances L G and L D of the bonding wires on the gate and drain bias sides are set to about 0.5 nH and the bypass capacitor C BP is set to 130 pF, series resonance occurs from L G , C BP and L D , C BP. It is given by 1 / 2π (L G C BP ) 1/2 = 1 / 2π (L D C BP) 1/2 ...... ( in this case, approximately 624MH Z). Therefore, since the input impedance changes rapidly near the resonance point, the frequency characteristics of the gain are also changed, and the flatness of the band is deteriorated.
第７図は、第６図に示す実装条件で１段の分布増幅器
ICを評価した特性を示す。IC内には出力側の容量11は含
まれていない。また使用したチップコンデンサは45pFで
あり、ゲート及びドレインバイアス端子には更に大きい
バイバスコンデンサ（0.01μＦ程度）を付加している。
入力側，出力側ともそれぞれマルで囲んだ2GHZ,2.9GHZ
付近でインピーダンスが大きく変化しており（50Ωに近
い値となり）、この点でいずれも共振が生じており、利
得S21の平坦性も劣化している。この共振点からボンデ
ィングワイヤのインダクタンスを概算すると、LG＝0.15
nH,LD＝0.07nHとなり、実装状態の見積りの値にほぼ等
しく、解析式からの予測とよく一致する。FIG. 7 shows a single-stage distributed amplifier under the mounting conditions shown in FIG.
This shows the characteristics evaluated for IC. The output capacitor 11 is not included in the IC. The chip capacitor used was 45 pF, and a larger bypass capacitor (about 0.01 μF) was added to the gate and drain bias terminals.
The input side and the output side and also circled each 2GH Z, 2.9GH Z
Nearby is changing impedance greatly (becomes a value close to 50 [Omega), and both the resonance occurs at this point, has deteriorated flatness of gain S 21. When the inductance of the bonding wire is roughly estimated from this resonance point, L G = 0.15
nH, L D = 0.07 nH, which is almost equal to the value of the estimation of the mounting state, and is in good agreement with the prediction from the analytical formula.
このように、実装された分布増幅器の帯域特性は共振
点付近で劣化を受けるため、ボンディングワイヤ，バイ
パスチップコンデンサの実装条件により、分布増幅器IC
の帯域特性より狭い範囲に制限される。As described above, since the band characteristics of the mounted distributed amplifier are deteriorated near the resonance point, the distributed amplifier IC may be changed depending on the mounting conditions of the bonding wire and the bypass chip capacitor.
Is limited to a narrower range than the band characteristic of.
第８図は前記共振点付近での帯域特性の劣化を改善し
た分布増幅器の参考例を示す。図において、31〜3nはFE
Tトランジスタを示す。夫々のFETのソース側は接地され
ており、FET31のゲートは第３の伝送線路50と第１の伝
送線路51の接続点に接続されている。ここに第３の伝送
線路50は第１の伝送線路51の1/2長である。以下、同様
にFET32〜３（ｎ−１）のゲートは第１の伝送線路に接
続され、FET3nのゲートは第１の伝送機構５（ｎ−１）
と第４の伝送線路5nの接続点に接続される。ここに第４
の伝送線路は第１の伝送線路の1/2長である。FIG. 8 shows a reference example of a distributed amplifier in which the deterioration of the band characteristic near the resonance point is improved. In the figure, 31 to 3n are FE
2 shows a T transistor. The source side of each FET is grounded, and the gate of the FET 31 is connected to the connection point between the third transmission line 50 and the first transmission line 51. Here, the third transmission line 50 is half the length of the first transmission line 51. Hereinafter, similarly, the gates of the FETs 32 to 3 (n-1) are connected to the first transmission line, and the gate of the FET 3n is connected to the first transmission mechanism 5 (n-1).
And the fourth transmission line 5n. Here the fourth
Is 1/2 the length of the first transmission line.
また、FET31のドレイン側は第５の伝送線路40と第２
の伝送線路41との接続点に接続される。ここに第５の伝
送線路は第２の伝送線路の1/2長である。以下、同様に
してFET32〜３（ｎ−１）は第２の伝送線路に接続さ
れ、FET3nのドレイン側は第２の伝送線路４（ｎ−１）
と第６の伝送線路4nとの接続点に接続される。ここに第
６の伝送線路は第２の伝送線路の1/2長である。The drain side of the FET 31 is connected to the fifth transmission line 40 and the second
Is connected to a connection point with the transmission line 41. Here, the fifth transmission line is half the length of the second transmission line. Hereinafter, similarly, the FETs 32 to 3 (n-1) are connected to the second transmission line, and the drain side of the FET 3n is connected to the second transmission line 4 (n-1).
And the sixth transmission line 4n. Here, the sixth transmission line is half the length of the second transmission line.
次に入力端子１はインダクタンス24,容量10を介して
第３の伝送線路50の一端に接続され、出力端子２はイン
ダクタンス24,容量11を介して第６の伝送線路4nの一端
に接続される。Next, the input terminal 1 is connected to one end of the third transmission line 50 via the inductance 24 and the capacitance 10, and the output terminal 2 is connected to one end of the sixth transmission line 4n via the inductance 24 and the capacitance 11. .
次に第１のバイアス電源端子18はインダクタンス28,
第１の抵抗29,インダクタンス27を介して、第１の終端
抵抗７と第１の容量13との接続点（ゲートバイアス端）
に接続され、抵抗７の他端は第４の伝送線路5nの一端に
接続される。また容量13の他端は接地される。さらに容
量21の一端は、抵抗29とインダクタンス28の接続点に接
続され、この容量21の他端は接地される。Next, the first bias power supply terminal 18 has an inductance 28,
Connection point (gate bias end) between the first terminating resistor 7 and the first capacitor 13 via the first resistor 29 and the inductance 27
, And the other end of the resistor 7 is connected to one end of the fourth transmission line 5n. The other end of the capacitor 13 is grounded. Further, one end of the capacitor 21 is connected to a connection point between the resistor 29 and the inductance 28, and the other end of the capacitor 21 is grounded.
次に第２のバイアス電源端子17はインダクタンス26,
第２の抵抗30,インダクタンス25を介して、第２の終端
抵抗６と第２の容量12の一端との接続点（ドレインバイ
アス端）に接続され、容量12の他端は接地される。さら
に抵抗６の他端は第５の伝送線路に接続され、また容量
20の一端は接地され、他端はインダクタンス26と第２の
抵抗30との接続点に接続される。Next, the second bias power supply terminal 17 has an inductance 26,
The second terminal 30 is connected to the connection point (drain bias end) between the second terminating resistor 6 and one end of the second capacitor 12 via the inductance 25, and the other end of the capacitor 12 is grounded. Further, the other end of the resistor 6 is connected to a fifth transmission line,
One end of 20 is grounded, and the other end is connected to a connection point between the inductance 26 and the second resistor 30.
ここにインダクタンス24,25,26,27,28はボンディング
ワイヤのもつインダクタンスを示す。Here, the inductances 24, 25, 26, 27, and 28 indicate the inductances of the bonding wires.
この回路の特徴は直列共振回路内に抵抗29,30を挿入
した点にある。これによって共振回路のＱを下げ、入出
力インピーダンスの急激な変化を緩和し、帯域特性を改
善することができる。The feature of this circuit is that resistors 29 and 30 are inserted in the series resonance circuit. As a result, the Q of the resonance circuit can be reduced, a sudden change in input / output impedance can be reduced, and the band characteristics can be improved.
第９図はゲート側に比較的高抵抗RG＝5.6KΩを与え、
ドレイン側の抵抗RDは付加していない場合の１段の分布
増幅器ICの特性の実測結果を示す。これによると共振点
付近での入力整合S11は改善され、これに伴いS21の帯域
特性が改善されていることが認められる。FIG. 9 shows that a relatively high resistance R G = 5.6 KΩ is applied to the gate side.
The measured results of the characteristics of the single-stage distributed amplifier IC when the drain-side resistor RD is not added are shown. Input matching S 11 in the vicinity of the resonance point due to this will be improved, it is recognized that the band characteristic of the S 21 Along with this has been improved.
第10図は更にドレイン側に抵抗RD＝100Ωを与えた場
合の１段の分布増幅器ICの特性の実測結果を示す。第９
図の場合と同様にS22,S21の帯域特性が改善されてい
る。ここでドレイン側では電流IDが流れるため、抵抗RD
でiDRDの電位降下が生ずるため、ドレインバイアス端子
からは更にiDRD分だけ大きなバイアスを必要とする。抵
抗RG,RDはあらかじめ分布増幅器IC内に含めることも可
能で、この結果第11図に示すような実装となり、第８図
の場合と同様な効果が得られる。FIG. 10 shows the measured results of the characteristics of the single-stage distributed amplifier IC when the resistance R D = 100Ω is further applied to the drain side. Ninth
Band characteristics of S 22, S 21 as in the case of FIG is improved. Here, since the current ID flows on the drain side, the resistance R D
In i D for potential drop R D occurs, it requires a large bias only further i D R D min from the drain bias terminal. The resistors R G and R D can be included in the distributed amplifier IC in advance, and as a result, the mounting is as shown in FIG. 11, and the same effect as in FIG. 8 is obtained.
（発明が解決しようとする課題） 以上説明したように、ドレイン側では電流IDが流れる
ため、抵抗RDでiDRDの電位降下が生ずるため、ドレイン
バイアス端子からは更にiDRD分だけ大きなバイアスを必
要とするという課題があった。As explained (0008) or more, the flow current I D at the drain side, the resistor R and the potential drop of the i D R D occurs at D, the drain bias further i D R D from the terminal There was a problem that a large bias was required.
本発明は上記の欠点を改善するために提案されたもの
で、その目的は、前記ドレインバイアスの増加を防ぎ、
バイパスコンデンサとボンディングワイヤのインダクタ
ンスにより生ずる共振を低減できる分布増幅器を提供す
ることにある。The present invention has been proposed in order to improve the above disadvantages, and its purpose is to prevent the increase in the drain bias,
An object of the present invention is to provide a distributed amplifier capable of reducing resonance caused by inductance of a bypass capacitor and a bonding wire.
（課題を解決するための手段） 上記の目的を達成するため、本発明はFETのソース端
を接地したFETを複数（ｎ個）配列し、各FETのゲート，
ドレイン間をそれぞれ第１及び第２の伝送線路で順次接
続し、第１のFETのゲートを第１の伝送線路の1/2の長さ
の第３の伝送線路の一端に接続し、前記第３の伝送線路
の他端を信号入力端とし、第ｎのFETのゲートを第１の
伝送線路の1/2の長さの第４の伝送線路に接続し、前記
第４の伝送線路の他端を第１の終端抵抗の一端に接続
し、前記第１の終端抵抗の他端をゲートバイアス端と
し、前記ゲートバイアス端と接地間に第１の容量を挿入
し、前記第１のFETのドレインを前記第２の伝送線路の1
/2の長さの第５の伝送線路の一端に接続し、前記第５の
伝送線路の他端を第２の終端抵抗の一端に接続し、前記
第２の終端抵抗の他端をドレインバイアス端とし、前記
ドレインバイアス端と接地間に第２の容量を挿入し、前
記第ｎのFETのドレインを前記第２の伝送線路の1/2の長
さの第６の伝送線路の一端に接続し、前記第６の伝送線
路の他端を出力端とする分布増幅器ICにおいて、前記ゲ
ートバイアス端は第１の抵抗の一端と第１のバイアス電
源端子に接続し、前記第１の抵抗の他端は第３の容量の
一端に接続し、前記第３の容量の他端は接地し、ドレイ
ンバイアス端は第２の抵抗の一端と第２のバイアス電源
端子に接続し、前記第２の抵抗の他端は第４の容量の一
端に接続し、前記第４の容量の他端は接地したことを特
徴とする分布増幅器を発明の要旨とするものである。(Means for Solving the Problems) In order to achieve the above object, the present invention arranges a plurality (n) of FETs each having a grounded source end, and a gate,
The drains are sequentially connected by first and second transmission lines, respectively, and the gate of the first FET is connected to one end of a third transmission line having a half length of the first transmission line. The other end of the third transmission line is used as a signal input terminal, and the gate of the n-th FET is connected to a fourth transmission line having half the length of the first transmission line. The other end of the first terminal resistor is connected to one end of the first terminal resistor, the other end of the first terminal resistor is used as a gate bias terminal, a first capacitor is inserted between the gate bias terminal and ground, and The drain is connected to one of the second transmission lines.
/ 2 length is connected to one end of a fifth transmission line, the other end of the fifth transmission line is connected to one end of a second termination resistor, and the other end of the second termination resistor is connected to a drain bias. End, a second capacitor is inserted between the drain bias end and ground, and the drain of the n-th FET is connected to one end of a sixth transmission line having a length half of the second transmission line. In the distributed amplifier IC having the other end of the sixth transmission line as an output end, the gate bias end is connected to one end of a first resistor and a first bias power supply terminal, and the other end of the first resistor is connected to the other end of the first resistor. One end of the third capacitor is connected to one end of the third capacitor; the other end of the third capacitor is grounded; the drain bias end is connected to one end of the second resistor and a second bias power supply terminal; Is connected to one end of a fourth capacitor, and the other end of the fourth capacitor is grounded. This is the gist of the invention.
（作用） 本発明においては、DC電流が流れないバイパスコンデ
ンサ側に抵抗29,30を付加している。このため第10図の
場合で問題となったドレインバイアスの増加を防ぐこと
ができる。(Operation) In the present invention, the resistors 29 and 30 are added to the bypass capacitor side where no DC current flows. For this reason, it is possible to prevent an increase in drain bias, which is a problem in the case of FIG.
（実施例） 次に本発明の実施例について説明する。なお、実施例
は一つの例示であって、本発明の精神を逸脱しない範囲
で、種々の変更あるいは改良を行い得ることは言うまで
もない。(Example) Next, an example of the present invention will be described. The embodiment is merely an example, and it goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.
第１図は本発明の一実施例を示すもので、参考例の第
８図と異なる点は、インダクタンス25,26の接続点と、
容量20との間に抵抗30を挿入した点と、インダクタンス
27と28の接続点と容量21との間に抵抗29を挿入した点に
ある。すなわち、DC電流が流れないバイパスコンデンサ
側に抵抗29,30を付加している。このため第10図の場合
で問題となったドレインバイアスの増加を防ぐことがで
きる。第１図の場合に対しても同様に抵抗RG,RDをIC内
に含めることは可能で、その場合第２図に示すような実
装図となる。FIG. 1 shows an embodiment of the present invention, which differs from FIG. 8 of the reference example in that the connection points of the inductances 25 and 26 are
Inserting a resistor 30 between the capacitor 20 and the inductance
The point is that a resistor 29 is inserted between the connection point of 27 and 28 and the capacitor 21. That is, the resistors 29 and 30 are added to the bypass capacitor side where no DC current flows. For this reason, it is possible to prevent an increase in drain bias, which is a problem in the case of FIG. The resistors R G and R D can be similarly included in the IC in the case of FIG. 1, and in this case, the mounting diagram is as shown in FIG.
（発明の効果） 上記構成により、本発明はドレインバイアスの増加な
しにバイパスコンデンサとボンディングワイヤのインダ
クタンスにより生ずる共振を低減できるという効果を奏
する。(Effect of the Invention) With the above configuration, the present invention has an effect that resonance caused by inductance of the bypass capacitor and the bonding wire can be reduced without increasing the drain bias.
第１図は本発明の分布増幅器実装回路の実施例、第２図
は本発明の分布増幅器実装回路の他の実施例を示す。 第３図及び第４図は従来の分布増幅器、第５図は分布増
幅器ICを多段化した場合の実装図、第６図は１つの分布
増幅器ICの実装を含めた等価回路、第７図は第６図の分
布増幅器の特性を示す。 第８図は分布増幅器の参考例、第９図及び第10図は参考
例の分布増幅器の特性の実測例、第11図は参考例の分布
増幅器の実装回路を示す。 １……入力端子 ２……出力端子 31〜３……FETトランジスタ 40〜4n,50〜5n……伝送線路 6,7……終端抵抗 8,9,17,18……バイアス端子 10〜13,20,21……容量 14……IC実装治具あるいはパッケージ 15,16……入出力端子 19……分布増幅器ICチップ 22,23……伝送線路 24〜28……ボンディングワイヤに含まれるインダクタン
ス 29,30……抵抗FIG. 1 shows an embodiment of the distributed amplifier mounting circuit of the present invention, and FIG. 2 shows another embodiment of the distributed amplifier mounting circuit of the present invention. 3 and 4 are conventional distributed amplifiers, FIG. 5 is an implementation diagram of a multistage distributed amplifier IC, FIG. 6 is an equivalent circuit including the implementation of one distributed amplifier IC, and FIG. 6 shows the characteristics of the distributed amplifier of FIG. FIG. 8 shows a reference example of the distributed amplifier, FIGS. 9 and 10 show actual measurement examples of the characteristics of the distributed amplifier of the reference example, and FIG. 11 shows an implementation circuit of the distributed amplifier of the reference example. 1 Input terminal 2 Output terminal 31-3 FET transistor 40-4n, 50-5n Transmission line 6,7 Terminating resistor 8,9,17,18 Bias terminal 10-13 20,21 Capacitance 14 IC mounting jig or package 15,16 Input / output terminal 19 Distributed amplifier IC chip 22,23 Transmission line 24 to 28 Inductance included in bonding wire 29, 30 …… resistance
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−218111（ＪＰ，Ａ) 特開 平１−166608（ＪＰ，Ａ) 特開 昭63−76605（ＪＰ，Ａ) 特開 昭62−206912（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H03F 3/00 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-218111 (JP, A) JP-A-1-166608 (JP, A) JP-A-63-76605 (JP, A) JP-A-62-1987 206912 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H03F 3/00
Claims (1)
個）配列し、各FETのゲート，ドレイン間をそれぞれ第
１及び第２の伝送線路で順次接続し、第１のFETのゲー
トを第１の伝送線路の1/2の長さの第３の伝送線路の一
端に接続し、前記第３の伝送線路の他端を信号入力端と
し、第ｎのFETのゲートを第１の伝送線路の1/2の長さの
第４の伝送線路に接続し、前記第４の伝送線路の他端を
第１の終端抵抗の一端に接続し、前記第１の終端抵抗の
他端をゲートバイアス端とし、前記ゲートバイアス端と
接地間に第１の容量を挿入し、前記第１のFETのドレイ
ンを前記第２の伝送線路の1/2の長さの第５の伝送線路
の一端に接続し、前記第５の伝送線路の他端を第２の終
端抵抗の一端に接続し、前記第２の終端抵抗の他端をド
レインバイアス端とし、前記ドレインバイアス端と接地
間に第２の容量を挿入し、前記第ｎのFETのドレインを
前記第２の伝送線路の1/2の長さの第６の伝送線路の一
端に接続し、前記第６の伝送線路の他端を出力端とする
分布増幅器ICにおいて、 前記ゲートバイアス端は第１の抵抗の一端と第１のバイ
アス電源端子に接続し、前記第１の抵抗の他端は第３の
容量の一端に接続し、前記第３の容量の他端は接地し、
ドレインバイアス端は第２の抵抗の一端と第２のバイア
ス電源端子に接続し、前記第２の抵抗の他端は第４の容
量の一端に接続し、前記第４の容量の他端は接地したこ
とを特徴とする分布増幅器。A plurality of (n) FETs each having a grounded source end.
And a gate and a drain of each FET are sequentially connected by first and second transmission lines, respectively, and a gate of the first FET is connected to a third transmission line having a half length of the first transmission line. Connected to one end of a transmission line, the other end of the third transmission line is used as a signal input terminal, and the gate of the n-th FET is connected to a fourth transmission line having half the length of the first transmission line. The other end of the fourth transmission line is connected to one end of a first terminating resistor, the other end of the first terminating resistor is used as a gate bias end, and a first capacitor is connected between the gate bias end and ground. And the drain of the first FET is connected to one end of a fifth transmission line having a length half of that of the second transmission line, and the other end of the fifth transmission line is connected to a second transmission line. Connected to one end of a terminating resistor, the other end of the second terminating resistor as a drain bias end, and inserting a second capacitor between the drain bias end and ground; In a distributed amplifier IC in which the drains of n FETs are connected to one end of a sixth transmission line having a length equal to 1/2 of the second transmission line, and the other end of the sixth transmission line is used as an output terminal. The gate bias end is connected to one end of a first resistor and a first bias power supply terminal, the other end of the first resistor is connected to one end of a third capacitor, and the other end of the third capacitor is Ground,
The drain bias end is connected to one end of a second resistor and a second bias power supply terminal, the other end of the second resistor is connected to one end of a fourth capacitor, and the other end of the fourth capacitor is grounded. A distributed amplifier characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30508789A JP2903162B2 (en) | 1989-11-24 | 1989-11-24 | Distributed amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30508789A JP2903162B2 (en) | 1989-11-24 | 1989-11-24 | Distributed amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03165108A JPH03165108A (en) | 1991-07-17 |
| JP2903162B2 true JP2903162B2 (en) | 1999-06-07 |
Family
ID=17940953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30508789A Expired - Fee Related JP2903162B2 (en) | 1989-11-24 | 1989-11-24 | Distributed amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903162B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2752883B2 (en) * | 1993-06-11 | 1998-05-18 | 日本電気株式会社 | High frequency amplifier |
| US7733185B2 (en) | 2005-10-24 | 2010-06-08 | Nec Corporation | Distributed amplifier and integrated circuit |
-
1989
- 1989-11-24 JP JP30508789A patent/JP2903162B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03165108A (en) | 1991-07-17 |
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