JP2901428B2 - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JP2901428B2
JP2901428B2 JP4221123A JP22112392A JP2901428B2 JP 2901428 B2 JP2901428 B2 JP 2901428B2 JP 4221123 A JP4221123 A JP 4221123A JP 22112392 A JP22112392 A JP 22112392A JP 2901428 B2 JP2901428 B2 JP 2901428B2
Authority
JP
Japan
Prior art keywords
circuit
output
time constant
signal
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4221123A
Other languages
Japanese (ja)
Other versions
JPH0666891A (en
Inventor
敏雄 工藤
正彦 平山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP4221123A priority Critical patent/JP2901428B2/en
Publication of JPH0666891A publication Critical patent/JPH0666891A/en
Application granted granted Critical
Publication of JP2901428B2 publication Critical patent/JP2901428B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は入力信号を処理すること
により伝達する情報を含む論理信号を出力する機能を備
えた集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a function of outputting a logical signal containing information to be transmitted by processing an input signal.

【0002】[0002]

【従来の技術】上記のような集積回路の一例を図4のブ
ロック回路図を示す。この集積回路は、一定周波数の信
号が伝えようとする情報にしたがって断続する図5の波
形図(a)に示すような入力信号が加えられる入力端子
1と、この入力信号を検波する検波回路3と、検波回路
3の出力波形を整形し、図5の波形図(b)に示すよう
な、前記情報を含む論理信号として出力端子2に出力す
る波形整形回路4とから形成されているところの、一般
的AV機器用リモコン受信部のプリアンプである。
2. Description of the Related Art FIG. 4 is a block circuit diagram showing an example of such an integrated circuit. This integrated circuit has an input terminal 1 to which an input signal is applied as shown in a waveform diagram (a) of FIG. 5 which is intermittent according to information to be transmitted by a signal of a constant frequency, and a detection circuit 3 for detecting the input signal. And a waveform shaping circuit 4 which shapes the output waveform of the detection circuit 3 and outputs it to the output terminal 2 as a logic signal containing the information as shown in the waveform diagram (b) of FIG. , A preamplifier of a remote control receiving unit for general AV equipment.

【0003】このような集積回路において、特性、機能
が類似したもの同士の間でお互いの異同を識別するた
め、または、お互いが混入することを防止するための方
法として、つぎに示すような方法が用いられる。
[0003] In such an integrated circuit, the following methods are used as a method for discriminating the difference between those having similar characteristics and functions, or for preventing them from being mixed with each other. Is used.

【0004】すなわち一つの方法として、端子配置やパ
ッケージを変えることである。他の方法としては図6の
パッゲージの平面図に示すように、一対のチェック端子
t1、t2と、この端子間に或る値の抵抗Rを作り込
み、この抵抗値によりお互いの異同を識別する方法であ
る。
That is, one method is to change the terminal arrangement and the package. As another method, as shown in the plan view of the package shown in FIG. 6, a pair of check terminals t1 and t2 and a certain value of a resistor R are formed between the terminals, and the difference between the terminals is identified by the resistance value. Is the way.

【0005】[0005]

【発明が解決しようとする課題】上記のような類似した
集積回路同士の間の混入防止や異同識別方法のうち、前
者の端子配置やパッケージの変更は、使用者にとっては
使い難いという欠点がある。また、後者のチェック端子
を設けることは余り端子があればよいが、そうでなけれ
ば新しく端子を設けなければならず、非常に不経済であ
る。
Among the above-described methods for preventing the mixing of similar integrated circuits and identifying the difference between the integrated circuits, the former method has a disadvantage that the terminal arrangement and the package are difficult to use for the user. . Also, the latter check terminal may be provided only with extra terminals, but otherwise, a new terminal must be provided, which is very uneconomical.

【0006】[0006]

【課題を解決するための手段】上記の課題に対して本発
明では、論理信号を出す出力回路と出力端子との間に時
定数回路を挿入して、その時定数をを変えることにより
類似している集積回路同士の間の異同を識別するように
している。
According to the present invention, a time constant circuit is inserted between an output circuit for outputting a logic signal and an output terminal, and the time constant is changed. The differences between the integrated circuits are identified.

【0007】[0007]

【実施例】つぎに図面を参照して本発明を説明する。図
1は本発明の一実施例のブロック回路図である。図1に
おいて、入力端子1には、図3の波形図の(a)のよう
な一定周波数の連続信号が所定の情報にしたがって断続
されている入力信号が加えられる。この入力信号は検波
回路3により検波されて検波出力を出し、つぎの波形整
形回路4に加えられ、波形整形回路4の出力は、波形整
形回路4と出力端子2の間に設けている時定数回路5を
介して出力端子2に出力される。しかして、この時定数
回路5の時定数は類似する集積回路同士の間の差異にし
たがって変えられる。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block circuit diagram of one embodiment of the present invention. In FIG. 1, an input signal in which a continuous signal of a constant frequency is intermittently transmitted according to predetermined information as shown in FIG. This input signal is detected by the detection circuit 3 to generate a detection output, and is applied to the next waveform shaping circuit 4. The output of the waveform shaping circuit 4 is a time constant provided between the waveform shaping circuit 4 and the output terminal 2. The signal is output to the output terminal 2 via the circuit 5. Thus, the time constant of the time constant circuit 5 is changed according to the difference between similar integrated circuits.

【0008】例えば、時定数回路5の時定数が最小値の
ときは、図3の(b)のように波形は元の歪みのない矩
形波であり、中間値の時定数では図3(c)のように波
形は鈍り、さらに大きな時定数では図3(d)のように
大きく鈍った波形となる。よってこの波形の違いを判別
することより類似する集積回路同士の間の異同を識別で
きる。
For example, when the time constant of the time constant circuit 5 is the minimum value, the waveform is a rectangular wave having no original distortion as shown in FIG. 3B, and as shown in FIG. The waveform becomes dull as shown in FIG. 3), and becomes a dull waveform as shown in FIG. Therefore, the difference between similar integrated circuits can be identified by determining the difference between the waveforms.

【0009】判別手段としては、例えば図2のブロック
回路図のようなサンプルホールド回路6を用い、図3に
示すタイミングT1、T2、T3、T4でホールドした
電圧を比較することにより波形の違い、ひいては集積回
路の異同を識別できる。
As a discriminating means, for example, a sample and hold circuit 6 as shown in the block circuit diagram of FIG. 2 is used, and by comparing the voltages held at timings T1, T2, T3 and T4 shown in FIG. As a result, differences between integrated circuits can be identified.

【0010】なお上例はリモコン回路受信部のプリアン
プ集積回路について述べているが、本発明はこれに限ら
ず、或る信号処理により論理信号を出力する、例えばA
−D変換器などなどにも適用できるのはいうまでもな
い。
Although the above example describes a preamplifier integrated circuit of a remote control circuit receiving section, the present invention is not limited to this, and outputs a logic signal by a certain signal processing.
It goes without saying that the present invention can be applied to a -D converter and the like.

【0011】[0011]

【発明の効果】上述のとおり本発明では、論理信号出力
部に時定数回路を設け、この時定数回路の時定数を異な
る集積回路では違った時定数にしておくことにより、出
力波形の違いを判別することにより集積回路の異同を容
易に識別できるという効果がある。
As described above, in the present invention, the time constant circuit is provided in the logic signal output section, and the time constant of this time constant circuit is set to a different time constant in a different integrated circuit. The discrimination has the effect that the difference between the integrated circuits can be easily identified.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例のブロック回路図である。FIG. 1 is a block circuit diagram of one embodiment of the present invention.

【図2】図1の実施例に係るサンプルホールド回路のブ
ロック回路図である。
FIG. 2 is a block circuit diagram of a sample and hold circuit according to the embodiment of FIG.

【図3】図1の実施例の動作を説明するための波形図で
ある。
FIG. 3 is a waveform chart for explaining the operation of the embodiment of FIG. 1;

【図4】一般的AV機器のリモコン受信部のプリアンプ
を示すブロック回路図である。
FIG. 4 is a block circuit diagram showing a preamplifier of a remote control receiving unit of a general AV device.

【図5】図4の回路の入力信号と出力信号を示す波形図
である。
FIG. 5 is a waveform diagram showing an input signal and an output signal of the circuit of FIG.

【図6】類似集積回路間異同識別用抵抗付き集積回路パ
ッケージの平面図である。
FIG. 6 is a plan view of an integrated circuit package with a resistor for distinguishing between similar integrated circuits.

【符号の説明】[Explanation of symbols]

1 入力端子 2 出力端子 3 検波回路 4 波形整形回路 5 時定数回路 6 サンプルホールド回路 1 input terminal 2 output terminal 3 detection circuit 4 waveform shaping circuit 5 time constant circuit 6 sample hold circuit

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) G01R 31/28 - 31/3193 H01L 21/822 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 入力端子に入力された信号を処理するこ
とにより出力端子に論理信号を出力する集積回路におい
て、前記論理信号を出力する最終の出力回路と出力端子
の間に、類似集積回路間異同を識別するための時定数回
路が設けられていることを特徴とする集積回路。
An integrated circuit that outputs a logic signal to an output terminal by processing a signal input to an input terminal, wherein a similar output signal is output between a final output circuit that outputs the logic signal and the output terminal. An integrated circuit, comprising a time constant circuit for identifying a difference.
JP4221123A 1992-08-20 1992-08-20 Integrated circuit Expired - Fee Related JP2901428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4221123A JP2901428B2 (en) 1992-08-20 1992-08-20 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4221123A JP2901428B2 (en) 1992-08-20 1992-08-20 Integrated circuit

Publications (2)

Publication Number Publication Date
JPH0666891A JPH0666891A (en) 1994-03-11
JP2901428B2 true JP2901428B2 (en) 1999-06-07

Family

ID=16761834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4221123A Expired - Fee Related JP2901428B2 (en) 1992-08-20 1992-08-20 Integrated circuit

Country Status (1)

Country Link
JP (1) JP2901428B2 (en)

Also Published As

Publication number Publication date
JPH0666891A (en) 1994-03-11

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