JP2900678B2 - Frequency mixer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency mixer circuit, and more particularly to a frequency mixer circuit composed of a dual gate FET.

[0002]

2. Description of the Related Art As a frequency mixer circuit constituted by using a dual gate FET, for example, the one shown in FIG. 2 is conventionally known. In FIG. 2, the frequency mixer circuit uses a dual-gate FET Q2, and applies an output signal of a preceding-stage high-frequency (RF) amplifier to one gate of the Q2 and a local signal to the other gate. Frequency conversion is performed.

[0003]

However, in the above-described conventional frequency mixer circuit, one dual-gate FET is used.
Since the square characteristic of (Q2) is used, a local signal level is required so that the square characteristic appears in the drain current, and the required signal level is about several volts. Therefore, a high-output amplifier is required to supply such a signal level local signal, and there is a problem that the circuit current cannot be reduced.

An object of the present invention is to provide a frequency mixer circuit having a dual gate FET structure which operates without any problem even when the local signal level is low.

[0005]

In order to achieve the above object, a frequency mixer circuit according to the present invention has the following configuration. That is, the frequency mixer circuit of the present invention comprises two dual-gate Fs whose sources are connected in common and driven by current.
ET; two pairs of differential pairs each comprising ET; first and second dual-gate FETs forming one differential pair, and third and fourth dual-gate FEs forming the other differential pair
T, one of the gates of the first and third dual-gate FETs is connected in common and a first DC voltage is applied; and one of the gates of the second and fourth dual-gate FETs is connected to each other. Directly connected to the first DC voltage
A second DC voltage of a different voltage value is applied; by connecting the other gates of the first and fourth dual-gate FET directly applying a first AC signal; second and third du
Arugeto before connecting the other of the gates of the FET directly
A second AC signal to be mixed with the first AC signal is applied; drains of the first and third dual-gate FETs are commonly connected; drains of the second and fourth dual-gate FETs are commonly used; Connection; a load resistor for taking out a mixing output is interposed between any one of the drains and the power supply;

[0006]

Next, the operation of the frequency mixer circuit of the present invention configured as described above will be described. According to the present invention, two dual gates F are driven in common with their sources connected in common.
In two sets of differential pairs constituted by ET, the conductance is different between the two dual-gate FETs constituting each differential pair by changing the value of the DC (bias) voltage applied to one of the gates. By doing so, a square characteristic is realized. Therefore, it is possible to provide a frequency mixer circuit that can perform the frequency conversion operation without any problem even if the level of the local signal (for example, the second AC signal) is small.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a frequency mixer circuit according to one embodiment of the present invention. This frequency mixer circuit is configured around four dual-gate FETs (M1, M2, M3, M4).

(M1, M2) and (M3, M4) have constant sources (1a, 1a,
constitute a differential pair driven by the drive current I ₀ of b).

Same as differential pair (M1, M2) (M3, M4)
, One of the gates of M1 and M3 is commonly connected and connected to the positive side of the DC voltage source (voltage V _B ) 2 and one of the gates of M2 and M4 is commonly connected. DC voltage source connected to the negative polarity side (voltage V _B) 2, M2
If one of the gates of M4 commonly connected to a DC voltage source is connected to the positive polarity side (voltage V _G) 3. in short,
The negative polarity side of the DC voltage source (voltage V _G) 3 is are grounded, both DC voltage source (2, 3) are connected in series. Therefore, the DC bias voltage applied as a first DC voltage to one of the gates of M1 and M3 is the sum voltage (V _B + V _G ) of both DC voltage sources, and the first bias voltage is applied to one of the gates of M2 and M4. DC bias voltage to be applied as a second DC voltage becomes the voltage V _G.

Further, the other gates of M1 and M4 are directly connected to each other, and a high frequency (RF) is connected between the gates and ground.
A signal source 4 is provided, and an RF signal (voltage V
_RF ), the other gates of M2 and M3 are directly connected to each other, a local signal source 5 is provided between the gates and the ground, and a local signal (voltage V _LO ) as a second AC signal is applied. .

The drains of M2 and M4 are commonly connected to a DC power supply (voltage V _DD ) 6, and M1 and M4 are connected to each other.
The drains 4 are commonly connected to a DC power supply 6 via a load resistor _RL . Therefore, in this embodiment, M1 and M
3 is converted into a voltage by the load resistance _RL , and the output voltage V _OUT is taken out.

In the above configuration, the drain currents (I _{D1 to} I _D4 ) of M1 to M4 monotonically increase and decrease according to the DC bias voltage of each gate. First, the M1 and differential pair M2, the drain current I _D1 of M1, is expressed as Equation 1 by using the conductance beta ₁ and the gate-source voltage V _GS1 and the threshold voltage V _TH, M2 of the drain current I _D2 is expressed as equation 2 using the conductance beta ₂ and gate-source voltage V _GS2 and the threshold voltage V _TH.

[0013]

(Equation 1)

[0014]

(Equation 2)

Further, conductance beta ₁ is a function of DC bias voltage (V _B + V _G) (Equation 3), conductance beta ₂ is a function of the DC bias voltage V _G (Equation 4).

[0016]

(Equation 3)

[0017]

(Equation 4)

Therefore, the sum of the two drain currents is defined as I ₀ (Equation 5), the ratio between β ₁ and β ₂ is defined as K (Equation 6), and the difference between the gate-source voltage is determined by the RF signal voltage V _RF and the local Since it is the difference from the signal voltage V _LO (Equation 7), I _D1 is obtained by Expression 8, and I _D2 is obtained by Expression 9.

[0019]

(Equation 5)

[0020]

(Equation 6)

[0021]

(Equation 7)

[0022]

(Equation 8)

[0023]

(Equation 9)

In Equations 8 and 9, the first item is a DC component term, while the second item can be regarded as a term proportional to (V _RF -V _LO ) ² , and the third item is (V _RF −V _LO ).

Similarly, in the differential pair of M3 and M4, the drain current I _{D3 of} M3 is expressed by Expression 10 using the conductance β ₃ , the gate-source voltage V _GS3, and the threshold voltage V _TH. drain current I _D4 of is expressed as equation 11 by using the conductance beta ₄ and the gate-source voltage V _GS4 and the threshold voltage V _TH.

[0026]

(Equation 10)

[0027]

[Equation 11]

Therefore, the sum of the two drain currents is defined as I ₀ (Equation 12), the ratio between β ₃ and β ₄ is defined as K (Equation 13),
Since the difference between the gate and source voltages is the difference between the RF signal voltage V _RF and the local signal voltage V _LO (Equation 14), I _D3
Is obtained as Expression 15, and I _D4 is obtained as Expression 16.

[0029]

(Equation 12)

[0030]

(Equation 13)

[0031]

[Equation 14]

[0032]

(Equation 15)

[0033]

(Equation 16)

Accordingly, the sum current (I _D1 + I _D3 ) of the drain currents of M1 and M3 is obtained by Expression 17, and the sum current (I _D2 + I _D4 ) of the drain currents of M2 and M4 is obtained by Expression 18.

[0035]

[Equation 17]

[0036]

(Equation 18)

From Equations 6 and 13, the characteristics of the two FETs are different in each differential pair, but between the two differential pairs, M2 and M4 have the same characteristics, and M1 and M3 have the same characteristics. I understand that there is.

Then, equations 8 and 9 and equation 17 and 1
In (8), the term (V _RF -V _LO ) ² can be expanded as in Expression 19.

[0039]

[Equation 19]

Here, the RF signal voltage V _RF is expressed by Expression 20, the local signal voltage V _LO is _expressed by Expression 21, and the product V
_{When RF} · V _LO is obtained, it becomes Expression 22. Therefore, (I _D1 +
I _D3 ) and (I _D2 + I _D4 ) include the sum and difference components of the frequencies f _RF and f _LO .

[0041]

(Equation 20)

[0042]

(Equation 21)

[0043]

(Equation 22)

Therefore, (I _D1 + I _D3 ) or (I _D1 + I _D3 )
If filtering _D2 + _{I D4)} after voltage _conversion, the sum and difference frequencies of the frequency of _{f RF} and _{f LO} is obtained. FIG. 1 shows a frequency mixer circuit for converting ( _ID1 + _ID3 ) into a voltage. Thus, two differentials
One of two dual-gate FETs forming a pair
Apply different biases to the other gate to
Operates with ductance to ensure square characteristics
Frequency mixer circuit is realized.

[0045]

As described above, according to the frequency mixer circuit of the present invention, in each of two sets of differential pairs composed of two dual-gate FETs whose sources are connected in common and driven by current, Since the value of the DC (bias) voltage applied to one of the gates of the two dual-gate FETs constituting the differential pair is made different to make the conductance different, the square characteristic is realized.
There is an effect that a frequency mixer circuit capable of performing a frequency conversion operation without any problem even if the level of a local signal (for example, the second AC signal) is small is provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a frequency mixer circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional frequency mixer circuit.

[Explanation of symbols]

1a Constant current source 1b Constant current source 2 DC voltage source 3 DC voltage source 4 High frequency (RF) signal source 5 Local signal source 6 DC power source M1 to M4 Dual gate FET R _L Load resistance

Claims (1)

(57) [Claims] 1. A differential pair comprising two sets of two dual-gate FETs whose sources are commonly connected and driven by current; first and second dual gates forming one differential pair Between the FET and the third and fourth dual-gate FETs constituting the other differential pair, one of the gates of the first and third dual-gate FETs is commonly connected to generate a first DC voltage. Applying one of the gates of the second and fourth dual-gate FETs directly to a second direct-current FET having a voltage value different from the first DC voltage.
Current voltage ; first and fourth dual-gate FEs
The first AC signal is applied by connecting the other gates of the T directly; the second and third dual-gate the other said connected directly to gates of the first AC signal of the FET and Miki
The second AC signal to be sequenced is applied; the first and third
Connect the drains of the dual-gate FETs in common;
The drains of the second and fourth dual-gate FETs are commonly connected; between one of the drains and the power supply
A load resistor for taking out the mixing output is interposed;
A frequency mixer circuit characterized by the above.