JP2896172B2 - Display control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a display control method suitable for use in, for example, a laptop personal computer in which a plurality of types of display drive circuits are mounted.

(Prior Art) In recent years, various types of laptop personal computers that are easy to carry and that can operate with an internal battery have been developed. This type of personal computer is required to have a display drive function capable of driving a plurality of types of display devices in order to expand the use of the personal computer as the functions and performance are improved. To meet this demand, it is necessary to provide a display control circuit unique to each display device to be driven. For example, when a so-called flat panel display such as a plasma display (hereinafter referred to as a PDP) or a liquid crystal display (hereinafter referred to as an LCD) and a CRT display are respectively driven, the PDP and C
RT can display control with common timing control,
Since the PDP and the LCD, both of which have a flat panel display configuration, have completely different display timings, it is necessary to provide an independent display control circuit including a display memory unique to each display device.

However, when each display control circuit of each of these display devices is mounted, for example, when driving a CRT display as a display target, the LCD,
Since the display drive circuit such as the PDP is in the operation mode, wasteful power consumption occurs, and in particular, there is an inconvenience that the use time is reduced when the battery is driven. In particular,
Flat panel displays such as PDPs and LCDs with backlight require high voltage for panel emission (PDP = discharge voltage, LCD with backlight = voltage for EL drive) to emit light from the panel. The drive power supply including the circuit consumes relatively large power.

(Problems to be Solved by the Invention) As described above, in the related art, even when a CRT display is driven as a display target, for example, a display drive circuit such as an LCD or a PDP in an unused state is in an operation mode. As a result, wasteful power consumption occurs, and the use time is shortened, particularly when the battery is driven.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in a personal computer having a configuration capable of driving a plurality of types of display devices, it is possible to eliminate unnecessary power in a display system which consumes a large amount of power, and to reduce a power supply load of the apparatus. It is an object of the present invention to provide a display control method capable of reducing battery power and enabling long-time use by battery driving.

[Constitution of the Invention] (Means and Actions for Solving the Problems) According to the present invention, the use state of a first display device (for example, a flat panel display such as an LCD or a PDP) using a specific display body is input by a plurality of inputs. A discriminating circuit for discriminating based on the conditions, and a display driving power supply (for example, a 5 V DC logic operating power supply and a 12 V DC power supply) supplied to the flat panel display when the non-use state of the flat panel display is determined by the discriminating circuit. And a switch circuit for shutting off a power supply for obtaining a panel light-emission voltage, thereby enabling the display drive of the flat panel display when the flat panel display such as an LCD or PDP is not in the display drive state. Eliminate wasteful and relatively large power consumption associated with system power supply, greatly reduce the power consumption of the entire system, and reduce the power load of the system. The battery operation can be reduced for a long time.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a system configuration in one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a display controller in FIG. 1, and FIG. 3 is a block diagram in the above embodiment. FIG. 3 is a block diagram illustrating a circuit configuration of a main part.

In FIG. 1, reference numeral 11 denotes a main CPU for controlling the entire system, which is realized here by a 32-bit CPU chip. Reference numerals 12 and 13 denote internal buses connected to the CPU 11, of which 12 is a 16-bit width internal data bus and 13 is a 24-bit width internal address bus. Numeral 14 denotes an optional numerical processor (Numerical Data Processor) that is selectively connected to the internal data bus 12 via a connector. Reference numeral 15 denotes a system bus including a 16-bit data bus 15D, a 20-bit lower address bus 15L, and a 7-bit upper address bus 15U. A bus driver (BUS-DRV) 16 serves as a connection interface between the internal buses 12, 13 and the system bus 15, and a bus controller (BUS-CN) 17 controls the system bus 15.
T) and 18 are memory controllers (MEM-CNT) for controlling the transfer of addresses between the address buses 13-15 (U, L) and for controlling the read / write of the main memory 19. Reference numeral 19 denotes a main memory (I-RAM) accessed under the address control of the memory controller 18. Reference numeral 20 denotes a BIOS-ROM storing a BIOS (basic input / output program), which has a processing routine as shown in FIG. 4 in an initialization routine (IRT). Reference numeral 21 denotes an I / O decoder (I / O-DEC) which decodes an I / O address on the system bus 15 and transfers it to a corresponding I / O element (chip), and 22 controls input / output of I / O data. I / O controller (I / O-CNT), 23 is a super integration IC (SI) containing various I / O controllers such as a floppy disk interface, hard disk interface, DMA controller, interrupt controller, etc., 24 is a floppy disk drive ( FD
D) A frequency oscillator (VFO) that generates a clock, 25 is a floppy disk drive interface (FDD-I
/ F), 26 is a hard disk drive interface (HDD-I / F), 27 is a keyboard controller (KBC), 2
8 is a keyboard scan controller (SCC), 29 is a backup RAM used for the resume function, etc.
(B-RAM), 30 is the extended memory card connector C1, C2, C3
An optional extended memory card (EXTM), 31 is a clock module (RTC; Real-Tim) that has its own operating battery and memory (CMOS-RAM) backed up by the battery.
e Clock), 32 is an external floppy disk drive (FD
D), an input / output port (PRT / FDD-IF) for connecting an input / output device such as a printer (PRT), and a serial input / output interface (SIO) 33 to which an RS-232C interface device or the like is connected. 34 is an intelligent power supply (PS) equipped with a power control CPU (PC-CPU), which controls the supply of power for operation of the device. Here, two main batteries (BT-L, BT-R) are connected. It is possible to control various power supplies under the control of the power control CPU (PC-CPU).
This is notified to the CPU 11 via the I / O controller 22. Reference numeral 35 denotes a display controller (DISP-CNT) serving as a display subsystem in the apparatus. Here, a so-called plasma display (hereinafter referred to as PDP), a liquid crystal display (hereinafter referred to as LCD), a color panel (color LCD) and the like are used. The flat panel display and the CRT display (hereinafter, referred to as CRT) are to be driven, and details thereof are shown in FIG. Reference numeral 36 denotes an extension connector to which various extension modules such as an extension display controller (display subsystem) can be connected. Reference numeral 14 denotes a floppy disk drive (FDD) connected to a floppy disk drive interface 25 and mounted in the device;
2, a hard disk drive (HDD) connected to the hard disk drive interface 26; 43, a keyboard unit (KB) connected to the keyboard scan controller 28; 44, a numeric keypad (tenkey);
47 is a display device connected to the display controller 35, of which 45 is an LCD with a backlight (for example, EL), 46 is a PDP having a discharge voltage generation DC-DC converter on the panel unit side, and 47 is a display device. CRT. C1
0 is a flat panel display connection connector, C11 is an LCD45 connector coupled to the flat panel display connection connector C10, and C12 is a PDP46 connector. Two specific pins for obtaining a signal for determining a connected flat panel display are assigned to the connector C10, and a determination signal indicating a display connected to the specific pin is transmitted to an I / O register provided in the display controller 35. Is read into the CPU 11 via the CPU (see FIG. 3).

FIG. 2 shows the display controller shown in FIG.
35 is a block diagram showing the configuration of 35. FIG.

In FIG. 2, 131 to 136 are components of a high-resolution display system, respectively, and 131 is a display main controller (CRT-CNT; PVGA) having a display drive control function of driving a CRT 47 at a high resolution. And 132, a bus interface function circuit for exchanging various display control data with the CPU 11 via the system bus 15, and an LCD 45.
And a display control unit (DC; HRGS-GA) having a gate array structure in which various functional circuit units for controlling display of the PDP 46 are mounted.
Here, the display drive function of various display devices (PDP, LCD, flat panel display such as color panel, CRT, etc.) subject to display control is selectively disabled according to the use state of each display. A display function killer circuit as shown in FIG. 3 which locks (locks to the non-drive level) and eliminates useless power consumed by the display drive control circuit of the display in the non-drive state is included.

133 is a display data memory (VRA) for storing display data
M), and is read-accessed by the display main controller 131 during display drive control of a CRT, a PDP, or the like. Reference numeral 134 denotes a CRT display data generation unit (DAC) for generating analog display data (R, G, B) under the control of the display main controller 131. As shown in FIG. Up-table) and three digital-analog converters (D / A) provided for the three primary colors (R, G, B). 135a and 135b are a pair of frame memories (FRAM-
A, FRAM-B) and the FRAM provided in the display control unit 132.
Memory access signals (FRA (RAS), FCA (CAS), WEU (write ena) output from the control circuit (209 in FIG. 3)
ble upper), WEL (write enable lower), DT (data tra
nsfer), SC (serial clock), FMA0-8 (memory addres
s, 0-8) etc.), and the frame memory 135a stores the display data of the upper half of the LCD display screen,
The frame memory 135b stores the display data of the lower half. 13
Reference numeral 6 denotes an LCD 45 and a PDP 46 according to a flat panel display enable signal (FPEN; see FIG. 3) from the display control unit 132.
This is a display power supply control circuit (PSC) that uses a switching gate circuit to selectively control the supply of display drive power (DC12V, DC5V) to flat panel displays such as LCD45, PDP46, etc. When the panel display is not in use (FPEN = "0"), the supply of display drive power (DC12V, DC5V) to the display device is prohibited.

FIG. 3 is a circuit block diagram showing a configuration of a display function killer circuit provided in the display control unit 132 shown in FIG. 2, and various display devices (CRTs) to be display-controlled.
The display drive function of the display and flat panel display such as PDP, LCD, and color panel) is selectively disabled (locked to the non-drive level) according to the use state of each display, and the display drive function of the non-drive state is disabled. Eliminate unnecessary power consumed by the display drive control circuit.

In FIG. 3, reference numerals 201 to 215 designate constituent elements of a display function killer circuit in the display main controller 131, and reference numerals 201 to 205 designate respective initialization routines (BIOS-IRT) shown in FIG. This register indicates a display condition and a display mode that are set. Of these, 201 is the use mode of LCD45 (“1”; LCD
A register (REG1) indicating the use mode) (202) is a register (REG1) indicating the use mode (“1”; CRT use mode) of the CRT47.
2), 203 is a register (REG3) indicating the enable / disable state (“1”; enable) of the internal display controller set at the time of setup, and 204 is the enable / disable (“1”; enable) of the flat panel display Register (REG4), 205 is CR
This is a register (REG5) indicating enable / disable of the T display data generation unit (DAC) 134 (“1”; enable). The registers 204 and 205 are set to the enabled ("1") state at the time of initial setting (see FIG. 4). Thereafter, when the display auto-off mode is set to be enabled in the setup, the registers 204 and 205 are also set in the setup. If there is no key input within the specified time, it will be switched to the disabled ("0") state under BIOS control.

Reference numeral 206 denotes the register 203 indicating that the internal display controller is enabled ("1") and the register 205
Is a NAND gate for generating a reference current cutoff enable signal (DDAC = “1”), except when it indicates the enable state (“1”) of the CRT display data generator (DAC) 134. Reference numeral 207 denotes a constant circuit provided with a circuit for cutting a reference current (IREF) flowing through a CRT display data generation unit (DAC) 134 when a reference current cutoff enable signal (DDAC = "1") is output from the NAND gate 206. It is a current circuit (CC). Reference numeral 208 denotes a reference current cutoff enable signal (DDAC =
When “1”) is output, the CRT display data generator (D
An AC gate 134 prohibits the display clock (DCLK) supplied to the AC 134. A FRAM control circuit 209 controls access to the frame memories 135a and 135b.
AS), FCA (CAS), WEU (write enable upper), WEL (wri
te enable lower), DT (data transfer), SC (serial c
lock), and various memory access signals such as FMA0-8 (memory address, 0-8). 210 is register 201 LCD4
5 indicates the use mode (“1”), and a flat panel display enable signal (FPEN =
This is an AND gate that outputs a frame memory enable signal (FMEN = "1") when "1") is being output.
211 is a NAND gate that obtains a state determination signal indicating whether or not the flat panel display is connected from a specific pin signal of the flat panel display connection connector C10,
Reference numeral 212 denotes a state in which the open / close switch SM of the flat panel display has the panel cover open (switch off = “1”).
Output), and indicates that the NAND gate 211 is connected to a flat panel display (“1”).
In this case, the AND gate outputs a "1" level signal indicating that the flat panel display is in use. 213 indicates that the register 202 is not in the CRT mode,
When the register 203 indicates the enable state of the internal display controller, the register 204 indicates the flat panel display enable state, and the AND gate 212 indicates the flat panel display use state, the flat panel display enable signal (FPEN =
This is an AND gate that outputs “1”). 214 is a memory access signal (F
RA, FCA, WEU, WEL, DT, SC, FMA0-8) is a NAND gate that controls the output according to the frame memory enable signal (FMEN), and the frame memory enable signal (FMEN) is "1".
Only when is the above memory access signal
Output to 135a and 135b. Reference numeral 215 denotes a specific pin signal of the flat panel display connector C10 in the sixth and seventh bits (b
It is an I / O register (I / O-REG) that can be read by the CPU 11 and latched in the it6, bit7). When the LCD 45 is connected to the flat panel display connector C10, the sixth and seventh bits (bit6 , bit7) are set to “0” and the PDP
When 46 is connected, the sixth bit (bit 6) is set to “1”,
The seventh bit (bit 7) is set to “0”, and the color panel sets “6” (bit 6) to “0” and the seventh bit (bit 7).
7) is set to “1”, and when the flat panel display is not connected, the sixth and seventh bits (bit
6) Set “1” to bit7).

Fig. 4 shows the initialization routine of the BIOS-ROM 20 (BIOS-IRT).
Is a flowchart showing a part of I / O register 2
A step of determining whether or not the PDP 46 is in a connected state from the signal of the seventh bit (bit 7) of No. 15, S2 and S3 are steps S1 and S3.
Setting the register 201 according to the judgment of S4
Is a step of determining whether or not the CRT is enabled from the CRT / panel bit signal of the setup data stored in the battery-backed memory (CMOS-RAM) in the clock module (RTC) 31; S5, S6 Is a step of setting the register 202 according to the determination of step S4, S7 is a step of determining whether the signal of the internal display controller enable bit of the setup data is in an enable setting state, and S8 and S9 are registers according to the determination of step S7. Steps of setting 203, S10 and S11 are steps of initially setting the registers 204 and 205 to "1".

Here, the operation in one embodiment of the present invention will be described with reference to FIG. 1 to FIG.

When the power is turned on, the BIOS-R
The initialization routine (BIOS-IRT) stored in the OM 20 is executed, and the setting processing of the registers 201, 202,... 205 in the display control unit 132 as shown in FIG. That is, first, the seventh bit (bi
It is determined from the signal at t7) whether or not the PDP 46 is connected (step S1 in FIG. 4). If a platform panel display (LCD 45 or color panel) other than the PDP 46 is connected, “0” is stored in the register 201. Is set, and when the PDP 46 is connected, "1" is set in the register 201 (steps S2 and S3 in FIG. 4). Next, the watch module (RTC) 31
Battery-backed memory inside (CMOS-RA
Read the CRT / panel bit of the setup data stored in M), and if the bit indicates the CRT use mode (“1”), set “1” in the register 202 and set the CRT use mode (“1”). Is not set, "0" is set in the register 202 (steps S4 to S6 in FIG. 4). Next, the internal display controller enable bit of the setup data is read, and if the bit is in the enable setting state, "1" is set in the register 203. If the bit is in the disable setting state, "0" is set in the register 203. (Steps S7 to S9 in FIG. 4). Next, "1" is initially set in the registers 204 and 205 (steps S10 and S11 in FIG. 4).

As described above, the setting process of the registers 201, 202,... 205 provided in the display control unit 132 is executed by the initialization routine (BIOS-IRT). The setting information of the registers 201, 202,... 205 selectively disables (locks to the non-drive level) the display drive control system circuit of the display in the non-drive state, and sets the display drive control system of the display in the non-drive state. It is used for display function killer control that eliminates wasted power consumed by the circuit. That is, the signal of the register 201 is input to the AND gate 210, and the registers 202, 203, 204
Are input to the AND gate 213 after the signal of the register 202 is inverted by the inverter, and the signals of the registers 203 and 205 are input to the NAND gate 206.

The NAND gate 206 except when the register 203 indicates the enable state ("1") of the internal display controller and the register 205 indicates the enable state ("1") of the CRT display data generation unit (DAC) 134. And outputs a reference current cutoff enable signal (DDAC = "1") to the constant current circuit 207.

When receiving the reference current cutoff enable signal (DDAC = "1") from the NAND gate 206, the constant current circuit 207 cuts the reference current (IREF) flowing to the CRT display data generation unit (DAC) 134.

In this case, the AND gate 208 operates according to the reference current cutoff enable signal (DDAC = "1").
Display clock (DCL) to CRT display data generator (DAC) 134
K) supply is banned.

As a result, the display clock (DC) is stored in the CRT palette (look-up table) of the CRT display data generator (DAC) 134.
LK) is not supplied, and furthermore, since the generation current of each display signal (R, G, B) does not flow through each of the R, G, B digital-analog converters (D / A), the CRT palette and The operation drive current of each digital-to-analog converter (D / A) is extremely reduced, and the power consumption of the CRT display data generator (DAC) 134 is significantly reduced.

Also, CR by using internal display controller 35
Even when the display is driven in T47, when the display auto-off is enabled in the setup, if the key input of the keyboard unit 43 is not performed within the set time, the register 205 is set to “0”. A reference current cut-off enable signal (DDAC = "1") is output from the AND gate 206, and supply of the display clock (DCLK) to the CRT display data generation unit (DAC) 134 is prohibited, and the reference current (IREF) is reduced. Be cut.

As described above, when the display drive of the CRT 47 is performed by using the internal display controller 35, except when the display auto-off function is activated,
The display clock (DCL) is output to the CRT display data generator (DAC) 134.
K) is supplied, and R, having a potential according to the display data content,
The display signals of the analog amounts of G and B are generated, but in other states, the supply of the display clock (DCLK) to the CRT display data generation unit (DAC) 134 is cut off, and the R, G, B
The current path for signal generation is cut off, and the CRT display data generation unit (DAC) 134 enters a power consumption state close to when power supply is cut off.

An AND gate 213 indicates that the register 202 is not in the CRT mode, a register 203 indicates an enable state of the internal display controller, a register 204 indicates a flat panel display enable, and an AND gate 212 indicates a use state of the flat panel display. Is output, the flat panel display enable signal (FPEN = "1") is output. This And Gate 21
The output of 3 is supplied to the AND gate 210 and also to the display power supply control circuit (PSC) 136.

The display power supply control circuit (PSC) 136 controls the supply of drive power (DC12V, DC5V) for flat panel displays such as the LCD 45 and PDP 46 according to the output signal of the AND gate 213. That is, the display power supply control circuit (PSC) 136 uses the AND gate 213 to output a "1" level flat panel display enable signal (FPEN =) indicating that the flat panel display such as the LCD 45 or PDP 46 is in use.
LCD45, PDP46 in use only when receiving “1”)
Drive power (DC12
V, DC5V). At this time, the DC-DC provided on the display unit side is
The converter generates a high voltage power supply for the backlight of the LCD 45 (for example, a high voltage power supply for the EL drive) or a high voltage power supply for the LCD 45. Also, the display power supply control circuit (PS
C) 136 is a flat panel display enable signal (FPEN = “1” level) from the AND gate 213 when the flat panel display such as the LCD 45 and PDP 46 is not in use.
When "1") is not output, supply of drive power (DC12V, DC5V) to LCD45, PDP46, etc. is cut off. Further, even if the use conditions of the flat panel display are prepared, when the display auto-off function is performed in the same manner as described above without the key input, the register 204 becomes “0”, whereby the output of the AND gate 213 becomes “0”. LCD45, P as above
Supply of drive power (DC12V, DC5V) to DP46 etc. is cut off.

As described above, when the use conditions of the flat panel display are not satisfied, the supply of the drive power (DC12V, DC5V) to the display drive circuits such as the LCD45 and PDP46 is cut off,
High-voltage drive power generation circuit with large power consumption (DC-DC
The power supply of the circuit including the converter is cut off.
Wasteful power consumption when a flat panel display such as P46 is not used is avoided.

The register 210 is a frame memory enable signal only when the register 201 indicates the use mode (“1”) of the LCD 45 and the flat panel display enable signal (FPEN = “1”) is output from the AND gate 213. (FMEN = "1") to open control the AND gates 214,. As a result, FRA (RAS), FCA (CAS), WEU (write enable up
per), WEL (write enable lower), DT (data transfe
r), SC (serial clock), FMA0-8 (memory address, 0
-8) are output to the frame memories 135a and 135b via the AND gates 214 and. When the LCD 45 is not in use and the output of the AND gate 213 is "0", the AND gates 214,... Are closed, and all the memory access signals generated by the FRAM control circuit 209 are at the non-drive level. (“1” = Vcc level), the frame memories 135a, 135
The unnecessary power consumption accompanying the access drive of b is avoided.

As described above, the non-use state of the LCD 45 is determined by a plurality of condition signals, and at the same time, the display drive system signal of the LCD 45 is locked to the non-drive level. Unnecessary power consumption can be suppressed, and the amount of power consumption during battery operation can be greatly reduced, thereby enabling battery operation for a long time.

By providing the display function killer circuit as shown in the above embodiment, the display drive system circuit of various display devices (CRT and flat panel display such as PDP, LCD, color panel, etc.) to be displayed is controlled. The non-drive level can be selectively locked in accordance with the use state of the display, and unnecessary power consumed by the non-display drive circuit can be eliminated, so that long-time use by battery driving is possible.

The configuration of the display controller 35 including the display function killer circuit according to the present invention is not limited to the configurations shown in FIGS. 2 and 3, but may be appropriately changed depending on the system configuration and the like.
The control target circuit and the like can be changed.

[Effects of the Invention] As described above in detail, according to the display control method of the present invention,
First display device using a specific display (eg, LCD, PDP
And the like, for determining the use state of a flat panel display based on a plurality of input conditions, and a display drive supplied to the flat panel display when the non-use state of the flat panel display is determined by the determination circuit. A switch circuit that shuts off the power supply makes it possible to use a relatively large and wasteful power supply for the display drive system of the flat panel display when the flat panel display such as an LCD or PDP is not in the display drive state. Power consumption can be eliminated, thereby greatly reducing the power consumption of the entire device, reducing the power load on the device, and enabling long-time battery-driven operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration in one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a display controller in FIG. 1, and FIG. 3 is a block diagram in the above embodiment. FIG. 4 is a block diagram showing a circuit configuration of a main part, and FIG. 4 is a flowchart showing a part of an initialization routine in the above embodiment. 11 CPU (main CPU), 12, 13 Internal bus (12
Internal data bus, 13: Internal address bus), 14: Numerical data processor (NDP),
15 System bus (15D… Data bus, 15L, 15U…)
Address bus), 16 Bus driver (BUS-DRV), 17
…… Bus controller (BUS-CNT), 18… Memory controller (MEM-CNT), 19 …… Main memory (I-RA)
M), 20 BIOS-ROM, 21 I / O decoder (I / O-DE
C), 22: I / O controller (I / O-CNT), 23: Super integration IC (SI), 24: Frequency oscillator (VFO), 25: Floppy disk drive interface (FDD-I / F), 26: Hard disk drive interface (HDD-I / F), 27: Keyboard controller (KBC), 28: Keyboard scan controller (SCC), 29: Backup RAM (B-RAM), 30
... Extended memory card (EXTM), 31 Clock module (RTC), 32 Input / output port (PRT / FDD-IF), 33
Serial I / O interface (SIO), 34 Intelligent power supply (PS), 35 Display controller (DISP-CNT), 36 Connector for expansion, 41 Floppy disk drive (FDD), 42
... Hard disk drive (HDD), 43 ... Keyboard unit (KB), 44 ... Tenkeypad (tenkey), 45
…… LCD, 46 …… PDP, 47 …… CRT display (CRT),
131 Display main controller (CRT-CNT; PVGA), 13
2 ... Display control unit (DC; HRGS-GA), 133: display data memory (VRAM) for storing display data, 134: CRT display data generation unit (DAC), 135a, 135b ... Frame memory (FRAM)
-A, FRAM-B), 136 ... Display power supply control circuit (PS
C), 201, 202, ... 205 ... register, 206, 211, 214 ..., ...
… Nand gate, 207 …… Constant current circuit (CC), 208,210,2
12,213, AND gate, 209 FRAM control circuit, 215 I / O register (I / O REG), C1, C2, C3 Memory card connector, BT-L, BT-R Main Battery, SM ... Flat panel display open / close switch,
C10 ... Flat panel display connector, IRE
F: Reference current, DDAC: Reference current cutoff enable signal, DCLK: Display clock, FPEN
...... Flat panel display enable signal, FMEN
…… Frame memory enable signal.

Claims (2)

(57) [Claims] 1. A first display control circuit for driving and controlling a first display device, and a second display control for driving and controlling a second display device using a display body different from the first display device. Circuit, a register indicating the use mode setting contents of the first display control circuit, a register indicating the use mode setting contents of the second display device, and a condition signal having the value of each register as one input condition. Determining means for determining whether or not use conditions of the first display circuit are satisfied; and a control circuit for controlling supply / stop of an operation power supply of the first display device according to the determination conditions. It is determined whether or not the use condition of the first display circuit is satisfied according to the condition signal including the register setting contents of the above, and only when the use condition is satisfied, the supply of the operating power to the first display device is controlled. Specially Display control system to be. 2. The display control method according to claim 1, wherein the operation signal of the display memory of the first display circuit is output controlled using the condition signal.