JP2892546B2 - Wireless control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery-powered wireless control device used for, for example, a game machine, and more particularly to a wireless control device for reducing the power required for transmission and reception. is there.

[0002]

2. Description of the Related Art Wireless control devices are now widely used in televisions, VTRs, game machines and the like. The schematic configuration of this device is as shown in FIG. This device is a wireless control device for a game device, and a wireless controller 1 for transmitting a signal.
0 and a receiving unit 11 that receives this signal. The key input unit 1 outputs an electric signal corresponding to a pressed key as parallel data. The electric signal of the parallel data output from this is converted into serial data by the parallel-serial conversion circuit 2. The code adding circuit 3 adds a header to the head of the serial data output from the parallel-serial conversion circuit 2 and adds a parity to the end thereof. Here, the header is
This signal is used to stably amplify the signal at the time of reception and to clarify the delimiter at the head of the data. Parity indicates whether the sum of all data is even or odd in order to confirm that there is no error during transfer.

The modulation circuit 4 performs pulse position modulation on these (0, 1) serial data to provide an interval between pulses. FIG. 6 shows an example of this pulse position modulation. In the portion corresponding to data 0, the pulse period is represented by T, and in the portion corresponding to data 1, the pulse width is represented by T and the pulse interval is represented by 2T. Signal. The modulation circuit 4 performs the above-described conversion processing on the input (0, 1) signal.
The transmitting circuit 5 transmits the modulated signal to a receiving circuit described later.

[0004] The receiving circuit 6 receives the signal output from the transmitting circuit 5 and outputs this signal to the demodulating circuit 7. In the demodulation circuit 7, processing opposite to that of the modulation circuit 4 is performed. That is, a process of converting the input signal into a serial signal output from the code adding circuit 3 based on the pulse period is performed. In the code analysis circuit 8, a process of removing a header and a parity included in the serial data restored by the demodulation circuit 7 is performed. As a result, the key data is restored.

At this time, a parity check is performed to check whether the parity of the restored data matches the parity removed earlier. If the parities do not match, it means that erroneous data has been received, and a process of discarding this data and not outputting it to the subsequent stage is performed.
If the parities match, the data is output to the data transfer circuit 9. This data transfer circuit 9 is a game device 1
This data is output in accordance with the data request from the device 2.

[0006]

However, in such a conventional wireless control device, it is necessary to continuously transmit the same data while the key is pressed, even if the key input does not change. As a result, there has been a problem that the power consumption is very large. Also,
Since it is determined which key is pressed in the order of data, for example, when eight keys are provided, even if only one of them is input, the other seven keys are pressed. Key data must also be transmitted, which also contributes to an increase in power consumption.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems and a demand for a longer battery replacement cycle on the customer side, and has a function of transmitting necessary data only when necessary. An object of the present invention is to provide a wireless control device which solves the above-mentioned problems by providing the wireless control device.

[0008]

According to the present invention, there is provided a key data output means for outputting key data corresponding to a key operation, and an input of current key data output from the key data output means. Transmission side storage means for updating and storing each time, and output from the key data output means.
By comparing the old <br/> key data stored in the transmission-side storage unit and the current key data, wireless and a transmitting means for outputting the current key data only when the mismatch control
A transmitting device, wherein the transmitting means transmits the current key data.
From the beginning or end data to the mismatched data
The smaller partial key data of the number of data
Wireless control device characterized by outputting
It is .

[0009]

[0010]

In the wireless control device configured as described [action] above, when transmitting the key data, the old key data stored in the current key data and the storage means is output from the key data output means compared bets is to output the current key data these data are outputted from the key data output means only when the discrepancy
Is the first data of the current key data or
Is the number of data from the last data to the mismatched data.
Chi, in <br/> to output either lesser part key data, gets rid transmitting the current key data unnecessarily,
The power required for transmission will be the minimum power.

[0011]

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration block diagram of a wireless control device according to the present invention. The appearance of the transmitter side of this device, that is, the wireless controller is as shown in FIG. The key input unit 1 outputs an electric signal corresponding to a pressed key as parallel data. The electric signal of the parallel data output from this is converted into serial data by the parallel-serial conversion circuit 2. This converted data (current key
Are stored in the memory 13 and the comparison circuit 1
4 is output. The comparison circuit 14 compares the data (current key data) output from the parallel-serial conversion circuit 2 with the data (old key data) stored in the memory 13.

If the result of the comparison by the comparison circuit 14 does not match the data, the data currently output from the parallel-serial conversion circuit 2 is output. If the result of the comparison is a data match, no data is output. The code addition circuit 3 adds a header to the head of the serial data output from the comparison circuit 14 and a parity to the end of the header. In the modulation circuit 4, these (0,
A pulse train is generated for the serial data of 1), and the transmitting circuit 5 transmits the generated pulse train to a receiving circuit described later.

The receiving circuit 6 receives the signal output from the transmitting circuit 5 and outputs this signal to the demodulating circuit 7. In the demodulation circuit 7, processing opposite to that of the modulation circuit 4 is performed. That is, the input signal is converted to the code addition circuit 3
Is performed to convert the serial signal into a serial signal output from. In the code analysis circuit 8, a process of removing a header and a parity included in the serial data restored by the demodulation circuit 7 is performed. As a result, the key data is restored. At this time, a parity check is performed to check whether the parity of the restored data matches the parity removed earlier. If the parities do not match, it means that erroneous data has been received, and a process of discarding this data and not outputting it to the subsequent stage is performed.

If the parities match, the data is output to the comparison circuit 16. This comparison circuit 16 is a memory 1
5 is compared with the data output from the code analysis circuit 8 to determine the parts that do not match.
Then, the data stored in the memory 15 is rewritten to the data output from the code analysis circuit 8. The data changed by this
Only the data portion is rewritten in the memory 15. The data transfer circuit 9 outputs data stored in the memory 15 according to a data request from the game device 12.

The wireless control apparatus according to the present invention having the above-described structure operates as follows. First, it is assumed that data is not yet stored in the memories 13 and 15 as an initial condition. Here, when any key is pressed by operating the controller as shown in FIG. 3A, the bit assignment as shown in FIG. 3B is followed in accordance with the pressed key. The parallel data is converted by the parallel-serial conversion circuit 2 into serial data. This data is stored in the comparator 1
In step 4, the data is compared with the data stored in the memory 13. On the other hand, the parallel-serial conversion circuit 2
Is output to the memory 13. At this time, the data stored in the memory 13 is erased and replaced with the data output from the parallel-serial conversion circuit 2.

The comparison circuit 14 outputs difference data between the data stored in the memory 13 and the data output from the parallel-serial conversion circuit 2 to the code addition circuit 3. The code adding circuit 3 adds a header to the head of the difference data output from the comparing circuit 14 and adds a parity to the end thereof, and sends a signal indicating the header part and a signal indicating the data part to the modulation circuit 4. At this time, a process of changing the value of the header portion depending on the position where the key input is made to reverse the order in which the data values are code-encoded is performed. For example, as shown in FIG. 3B, when 1 is assigned to the head of the data and 8 is assigned to the rear, if the key 2 is input, the data is encoded as shown in FIG. , 8 key input, the header value is set to 1 and the code is coded from the rear side to obtain a code as shown in FIG. In this way, data (partial data) is always encoded with the smallest bit.

The modulation circuit 4 modulates the header, data and parity of the encoded data separately. The modulation circuit 4 modulates the data 0 and the data 1 into signals like the A section and the B section shown in FIG. 2, respectively. At the end of the header part, a signal as shown in the part C of the figure is allocated, and at the end of the data, a signal as shown in the part D of the figure is allocated, so that each block is separated by the receiver. The code can be identified by the user. Transmission circuit 5
Then, the code thus modulated is transmitted by turning on and off the carrier wave of light or radio waves.

The receiving circuit 6 receives the transmitted code, and the demodulating circuit 7 restores the code to a pulse train before modulation. The restored pulse train is sent to the code analysis circuit 8, where the header part, the data part and the parity constituting the pulse train are separated, and the direction of encoding is determined based on the value of the header part. For example, when encoding is performed from the rear (the header portion is 1), this is converted into data from the head and only the data portion is output to the comparison circuit 16.
At this time, a parity check is performed. If the parity value does not match the sum of the data, it is determined that the contents of the data cannot be trusted, and the data is not used.

The comparison circuit 16 compares the data stored in the memory 15 with the data sent from the code analysis circuit 8. In the present example, no data is stored in the memory 15 yet, so the transmitted data is written. When the game device 12 requests data transfer, the data transfer circuit 9
5 is retrieved and output as key data.

When the next key operation is performed, the comparison circuit 14 on the transmitter side compares the previously stored data stored in the memory 13 with the data output from the serial-parallel conversion circuit 2. And the value of the difference data is 0
, No data is output from the code adding circuit 3, and therefore no signal is output from the transmitter. Even in such a case, since the previous data is stored in the memory 15 on the receiver side, even if there is a data transfer request, the data can be output to the game device 12.

On the other hand, when a key operation different from the previous operation is performed, the difference data of the comparison circuit 14 is not 0, and therefore, the code addition circuit 3 determines only the minimum number of data including the data having the difference signal. It is encoded and transmitted together with a header value indicating the order of code encoding. Also,
The data in the memory 13 is replaced with the current data instead of the previous data. The receiver compares and corrects the previous data stored in the memory 15 with the data sent from the code analysis circuit 8 and the header value.
Is updated and stored. Then, in response to a data transfer request from the game machine 12, the newly updated and stored data is output.

[0023]

As is apparent from the above description, according to the present invention, key data is transmitted from the transmitter to the receiver only when a different key operation is performed. Since only the minimum number of partial key data including mismatched data is transmitted upon transmission, the amount of data to be transmitted can be greatly reduced. Therefore, since most of the power consumption of a wireless controller that operates on a battery is used for data transmission, the usage time of the battery is increased by the amount of transmission data reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of a wireless control device according to the present invention.

FIG. 2 is a diagram showing an example of a modulated signal generated by the device of FIG.

FIG. 3 is a diagram illustrating an external view of a wireless controller and an example of bit allocation assigned to a key of the wireless controller.

FIG. 4 is a diagram illustrating an example of variable-length coding generated by the device of FIG. 1;

FIG. 5 is a schematic block diagram of a conventional wireless control device.

FIG. 6 is a diagram illustrating an example of a modulated signal generated by the device of FIG. 5;

[Explanation of symbols]

 1: key input section (key data output means) 2: parallel-serial conversion circuit (key data output means) 5: transmission circuit (output means) 6: reception circuit (reception means) 9: data transfer circuit (output means) 13, 15: Memory (storage means) 14: Comparison circuit (output means) 16: Comparison circuit (storage means)

Claims (1)

(57) [Claims] 1. Key data output means for outputting current key data corresponding to a key operation; transmission side storage means for updating and storing current key data output from the key data output means each time an input is made; A wireless control device having a transmission unit that compares the current key data output from the data output unit with the old key data stored in the transmission side storage unit and outputs the current key data only when there is a mismatch. Wherein the transmitting means outputs partial key data, which is the smaller of the number of data from the first data or the last data of the current key data to the mismatched data.