JP2891729B2 - Measuring method of dielectric isolation substrate and its measuring device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for measuring a dielectrically isolated substrate having isolated islands formed thereon.

(Prior art) Conventionally, techniques in such a field include Japanese Patent Application No. 59-19 / 1979.
9491.

 Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a cross-sectional view showing a conventional method for measuring the polished state of a dielectric isolation substrate, and FIG. 3 is a plan view of FIG.

The dielectric isolation substrate 1 has an isolation island 3 made of silicon single crystal dielectrically isolated via an isolation insulating film 2. For example, three moats 4a, 4b, 4c projecting in an inverted V-shape are formed in the separation island 3, and have different heights. The surface of the dielectric substrate 1 on the side of the separation island 3 is polished, and the depth of the separation island 3 is set to a predetermined value.

Resistor diffusion layers 5a, 5b, 5c are formed on the surface layer of the separation island 3 near the tops of the motors 4a, 4b, 4c, respectively, and an insulating film 6 is formed thereon. Electrode extraction holes 7 are formed in the insulating film 6, and each of the resistor diffusion layers 5a, 5b, 5c is formed by an electrode wiring 8 provided through these electrode extraction holes 7.
Are connected in series. Also, each of the resistor diffusion layers 5a, 5b,
The width of 5c is the width W of each mote 4a, 4b, 4c as shown in FIG.
It is set to be narrower. Where each mote
Since the heights of 4a, 4b, and 4c are different, for example, a gap D is formed between the moat 4a and the resistor diffusion layer 5a, the moat 4b and the resistor diffusion layer 5b are in contact, and the moat 4c is This cuts into the diffusion layer 5c to separate it.

In the resistor diffusion layers 5a, 5b, 5c configured as described above, if a voltage is applied between the resistor diffusion layers 5a, 5b, 5c via the electrode wiring 8, the resistor diffusion layers 5a, 5b A current flows through. However, since the resistor diffusion layer 5c is separated by the moat 4c, no current flows and its resistance value is infinite. That is, when the moat 4c is exposed on the surface of the isolation island 3, no current flows, and when the moat 4c is in the isolation island 3 as in the motes 4a and 4b and does not divide the resistor diffusion layers 5a and 5b. The current flows.

In this way, the resistance diffused layers 5a, 5b, 5c are provided on the moats 4a, 4b, 4c having different heights, and the resistance values thereof are electrically measured, whereby the polished state of the separation island 3 is obtained. A measurement was taking place.

In addition, the measurement of the mask alignment deviation with respect to the conventional dielectric isolation substrate has been performed as shown in FIG.

In this figure, reference numeral 21 denotes an isolation island serving as a semiconductor element formation region, 22 denotes an isolation insulating film for insulating and separating the isolation islands 21, 23 denotes a support layer of a dielectric isolation substrate, and 24 denotes a main portion of the isolation island 21. An actual pattern 25 formed on the front surface side is a design pattern.

Here, lx, ly is the isolation insulating film 2 from the actual pattern 24.
The distance up to 2, mx, my is the actual distance between adjacent isolated islands 21 and nx, ny is the distance m between the designed pattern 25 and the isolated islands 21
Indicates the distance to the center of x, my.

Next, an example of a conventional method for measuring a mask misalignment will be described.

The distance of lx, ly and mx, my is measured by an optical method such as microscopy. Since nx, ny is known as a design value, the actual misalignment of the pattern 24 with respect to the separation island 21 is Δx = nx−lx−1 / 2mx Δy = ny− in the x-axis and y-axis directions, respectively. It is given by the formula ly−1 / 2my.

(Problems to be Solved by the Invention) However, in the above-described conventional method for measuring the polishing state of the dielectric isolation substrate, the measurement accuracy is poor due to the variation in the resistance value and the existence of the transition region as shown in FIG. It was difficult to improve it. That is, FIG. 4 shows a conventional measurement example of a polished state, and shows the resistance value of the resistor diffusion layer corresponding to each moat. In this figure, the resistor diffusion layers 10a to 1a formed on the moats 9a to 9f are shown.
0f is a diffusion resistance, and the resistance value varies depending on the depth and distribution density of the diffusion layer. For example, in the resistor diffused layers 10a and 10b, the resistance values are not constant and vary with respect to the set value R even though they are not divided by the moats 9a and 9b. on the other hand,
When a part of the resistor diffusion layers 10c and 10d are separated by the moats 9c and 9d, respectively, since the resistance value is located in a transition region where the resistance value is difficult to predict and is indistinct, an accurate measurement of the polishing state is performed. Becomes difficult.

The above-described variation in the resistance value and the existence of the transition region are mainly caused by the depth of the diffusion layer forming the resistor diffusion layers 10a to 10f. A shallow junction can be considered. However, in general, the depth of the diffusion layer is relatively deep, about 0.3 μm or more. Therefore, a complicated process must be performed to achieve the shallow junction. In particular, in the case of a dielectric isolation substrate that does not normally require a shallow junction, problems such as the necessity of adding a new process are caused.

Also, in the above-described method of measuring the mask alignment deviation, it is difficult to automate the length measurement process,
There is a problem that a large number of man-hours are required because evaluation is performed by microscopic inspection.

Furthermore, since an artificial operation is added in the step of calculating the mask misalignment from the acquired length measurement data, there is also a problem in data reliability.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problem that the measurement accuracy is poor due to the above-described variation in resistance value and the presence of a transition region, and it is difficult to improve the measurement accuracy. An object of the present invention is to provide a method for measuring a body separation substrate and a measuring device therefor.

Another object of the present invention is to eliminate the problems of increased measurement time due to difficulty in automation and the unreliability of data due to manual work in measuring the above-described mask misalignment, thereby enabling automation. To provide a method for measuring a dielectric isolation substrate and a measuring apparatus therefor.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for measuring the polished state of a dielectric separation substrate (11), the method comprising the steps of: A plurality of single crystal silicon islands (14, 14) are formed via an isolation insulating film (13), and the single crystal silicon islands (14, 14) on the main surface side of the adjacent single crystal silicon islands (14, 14) are formed. ), A plurality of single-crystal silicon islands (14, 14) and a plurality of resistor diffusion layers (15) of the opposite conductivity type are formed over the exposed portion of the support layer (12), and the resistor diffusion layers (15) are formed. A plurality of sets of electrodes having different distances symmetrically from the center between the single-crystal silicon islands (14, 14) are formed thereon, and a voltage is applied between the electrodes of each set to form a dielectric isolation substrate (11). ) Is electrically measured.

Also, a plurality of single crystal silicon islands (34, 34) are formed on a dielectric isolation substrate (31) having a moat having a constant height via an isolation insulating film (33), and the adjacent single crystal silicon islands (34) are formed. This single crystal silicon island (34,34) on the main surface side of 34,34)
The single-crystal silicon islands (34, 34) that straddle the exposed portion of the support layer (32) between them and the resistive diffusion layer (35) of the opposite conductivity type are independent in the single-crystal silicon islands (34, 34). In the exposed portion of the support layer (32), the independent resistor diffusion layer (35) is formed to be short-circuited, and the unit is formed on the resistor diffusion layer (35). Crystalline silicon island (34,34)
A plurality of pairs of electrodes having different distances are formed symmetrically from the center between them, and a voltage is applied between the electrodes of each pair to electrically measure the mask alignment deviation.

(Operation) As described above, according to the present invention, when measuring the polishing state of the dielectric isolation substrate (11), the adjacent single crystal silicon islands (14, 1
A resistor diffusion layer (15) is formed on the main surface of (4) via a V-groove, and a plurality of pairs of electrodes having different distances symmetrically from the center between the isolation islands are formed on the resistor diffusion layer (15). By examining the conduction state, the polishing state of the single crystal silicon island (14, 14) can be accurately measured.

Also, when measuring the mask alignment deviation of the dielectric isolation substrate (31), the resistor diffusion layer (35) is placed on the main surface side of the adjacent single crystal silicon island (34, 34) via a V-groove to form an electrode in the isolation island. A plurality of resistive diffusion layers (35) are connected independently on the support layer (32) between the isolated islands according to the number, and the right and left sides of the resistor diffused layer are shifted from the center between the isolated islands. Plural sets of electrodes having different distances are formed symmetrically, and those having the same structure as those described above are arranged so as to be orthogonal to each other with respect to the X-axis and the Y-axis. By examining the state, it is possible to evaluate the mask alignment deviation with respect to the separation island.

(Embodiment) FIG. 1 is a structural view of a measuring element in a polished state of a dielectric isolation substrate showing an embodiment of the present invention. FIG. 1 (a) is a plan view thereof, and FIG. 1 is a cross-sectional view taken along line AA of FIG.
FIG. 1 (c) is a sectional view taken along the line BB of FIG. 1 (a).

Hereinafter, a method for measuring the polished state of the dielectric isolation substrate of the present invention will be described with reference to FIG.

First, the configuration of the measuring element in a polished state of the dielectric isolation substrate will be described.

The dielectric isolation substrate 11 has an isolation island 14 made of single crystal silicon that has been dielectrically isolated via a support layer 12 made of polysilicon or the like and an isolation insulating film 13. On the main surface side of the isolation island 14 between the adjacent isolation islands 14, a resistor diffusion layer 15 having a surface concentration that allows easy formation of ohmic contact with the isolation island 14 via the isolation insulating film 13 is formed. The insulating film 16 is formed thereon. Insulating film
In 16, electrode extraction holes 17 of different distances which face adjacent separation islands 14 and are arranged symmetrically from the center between the separation islands 14, 14.
Are a plurality of sets (in the embodiment, two sets are shown in a simplified manner,
Actually, the number is determined in accordance with the desired measurement accuracy and range), and the electrode wiring is formed through these electrode extraction holes 17.
18a and 18b are formed.

Next, a measuring method of the polishing state measuring device formed as described above will be described.

In FIG. 1B, if a voltage is applied between the resistor diffusion layers 15 via the electrode wirings 18a, a current flows through the resistor diffusion layers 15. On the other hand, in FIG. 1C, since the resistor diffusion layer 15 is divided by the isolation insulating film 13, no current flows even when a voltage is applied between the resistor diffusion layers 15 via the electrode wiring 18b. , Its resistance value shows infinity.

In other words, when the electrode extraction hole 17 is disposed outside the isolation island 14, that is, on the support layer 12, the resistor diffusion layer 15 is not divided by the isolation insulating film 13, so that a current flows. Conversely, when the electrode extraction hole 17 is arranged in the isolation island 14, the resistor diffusion layer 15 is separated by the isolation insulating film 13, so that no current flows.

In this way, by providing electrode extraction holes 17 with different distances between the electrodes on the resistor diffusion layer 15 and electrically measuring the conduction state of the resistor diffusion layer 15, the polishing state of the single crystal silicon island, that is, , Separation island spacing and separation island depth can be determined.

Next, another embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a configuration diagram of an element for measuring a mask alignment shift of a dielectric isolation substrate according to another embodiment of the present invention. FIG. 6 (a) is a plan view thereof, and FIG. FIG. 6 (a) is a sectional view taken along the line CC, and FIG. 6 (c) is FIG. 6 (a).
FIG. 4 is a sectional view taken along line DD of FIG.

First, the dielectric isolation substrate 31 has isolation islands 34 made of dielectrically isolated single crystal silicon via a support layer 32 made of polysilicon or the like and an isolation insulating film 33. Between the adjacent isolated islands 34, on the main surface side of the isolated islands 34, there is a resistor diffusion layer 35 having a surface concentration capable of easily forming ohmic contact with the isolated islands 34 through the isolation insulating film 33 with a reverse conductivity type. It is formed independently. The respective resistor diffusion layers 35 are connected (short-circuited) on the support layer 32, and the insulating film 36 is formed thereon. In the insulating film 36, a plurality of sets of electrode extraction holes 37 having different distances which face the adjacent separation islands 34 and are arranged symmetrically with respect to the center between the separation islands 34, 34 (in the embodiment, 6 pairs in a simplified manner). Although they are assembled, the number is actually determined according to the desired measurement accuracy and range), and the electrode wirings X ₁₁ , X ₁₁ are formed through these electrode extraction holes 37.
_{12, X 13, X 21,} X 22, X 23, Y 11, Y 12, Y 13, Y 21, Y 22, Y 23 is formed.

Next, a description will be given of the measurement principle of the mask alignment deviation measuring device formed as described above.

In FIG. 6B, when a voltage is applied between the resistor diffusion layers 35 via the electrode wirings X ₁₁ and X ₂₁ , a current flows through the resistor diffusion layers 35. On the other hand, in FIG. 6 (c), since the resistance diffusion layer 35 is separated by a separation insulating film 33, even if a voltage is applied via the electrode wirings X _12, X ₂₂ across resistor diffusion layer 35 No current flows and its resistance shows infinity. In other words, the electrode extraction hole 37 is located outside the separation island 34, that is, the support layer.
In the case where the resistor diffusion layer 35 is disposed on the resistor 32, the resistor diffusion layer 35 is not divided by the isolation insulating film 33, so that a current flows. Conversely, when the electrode extraction hole 37 is disposed in the isolation island 34, no current flows because the resistor diffusion layer 35 is divided by the isolation insulating film 33.

The structure and measurement principle of the mask alignment deviation measuring device according to one embodiment of the present invention have been described above.

Next, a method of measuring a mask alignment shift will be described with reference to FIGS. 7 and 8. FIG. Where E-
The E line indicates the center line between the separation islands 34. ΔX indicates the amount of mask alignment deviation with respect to the separation island 34, and the arrow indicates the direction.

FIG. 7 shows a mask alignment displacement measuring element in the X-ray axis direction.
An electrode extraction hole 37 is formed. That is, at least the interval (first interval) between the electrode extraction holes 37 arranged at the uppermost stage (first stage) is smaller than the interval W between the separation islands, and is arranged at the lower middle stage (second stage). The space between the electrode extraction holes 37 (second space) is wider than the first space, but is smaller than the space W between the separation islands. The spread amount is the same amount on both the left and right sides, and is a minute amount (Δl). Next, the interval (third stage interval) between the electrode extraction holes 37 arranged in the lowermost stage (third stage) is wider than the interval W between separation islands and wider than the second stage interval. The spread amount is the second on both sides.
The same amount as in the case of the step interval.

Further, to be generally applicable, the electrode extraction hole 37 on the left side is provided between separated islands having a constant width (W).
Is electrically conducted from the lower stage to the upper stage, and the distance l from the right end of the first electrode extraction hole 37 to the center between the separation islands and the separation island having the width (W) are set to the right electrode. The electrode extraction holes 37 are formed such that the electrical conduction is sequentially performed from the lower stage of the extraction holes 37 to the upper stage, and the distance m from the left end of the first electrode extraction hole 37 that is first conducted to the center between the separation islands is equal. Such a mask for measurement is used. Therefore, we describe a procedure to examine the conduction state between the electrode lines X _11, X _12, X ₁₃ and electrode wires _{X 21, X 22, X 23} .

First, the electrode wires X ₂₁ , X ₂₂ and X ₂₃ are short-circuited, and the electrode wires X _21
13, X _12, a voltage between the electrodes in the order of X ₁₁ is applied examine its conducting state.

For this case, the electrode wiring X _21, X _22, X ₂₃ short-circuit terminal,
When a voltage is applied to the electrode lines X _11, a current flows.

Next, the short circuit of the electrode wirings X ₂₁ , X ₂₂ and X ₂₃ is released, and a voltage is applied between the two electrodes in the order of the electrode wirings X ₂₃ , X ₂₂ and X ₂₁ with respect to the electrode wiring X ₁₁ , Examine the combination of electrode wirings through which the first current flows. Thereby, the relationship of X ₁₁ −X ₂₂ can be obtained.

Next, the mask alignment deviation amount Δ with respect to the separation island 34
A method for deriving X will be described. Here, it is assumed that the mask alignment shift amount ΔX exists in the direction shown in FIG.

Then, the wiring electrodes X _1n , X _2n (n = 1, 2, 3) and the separation island 34
The design distance to the EE line between them is set to L _1n , L _2n (n = 1, 2, 3), respectively, corresponding to the subscript of the electrode wiring.

Distance l and m to the electrode wiring X ₁₁ and X ₂₂ and the line E-E is given by the following equation, respectively.

l = L ₁₁ + ΔX (1) m = L ₂₂ −ΔX (2) Further, from the above, l−m = 0 (3) Therefore, from the above (1), (2) and (3), l, m
Is erased, ΔX = (L ₂₂ −L ₁₁ ) / 2... (4) Since L ₁₁ and L ₂₂ are known by design values,
A mask alignment shift amount ΔX is derived.

The mask alignment shift in the X-axis direction has been described above, but the shift amount can be derived in exactly the same manner in the Y-axis direction.

Further, this determines the interval between the separation islands 34, 34.

In this way, by providing electrode extraction holes having different distances between the electrodes on the resistor diffusion layer and electrically measuring the conduction state of the resistor diffusion layer, the amount of mask alignment deviation with respect to the separation island and the separation island spacing can be obtained. Can be determined appropriately.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the gist of the present invention.
They are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, the following effects can be obtained.

(1) A plurality of electrodes having different distances are formed symmetrically from the center of the V groove on a resistor diffusion layer formed so as to straddle the V groove on the main surface side of the adjacent single crystal silicon island. Since the conduction state is measured, there is no transition region where measurement values are unclear as in the prior art, and the measurement accuracy can be determined by the distance between the electrodes, that is, the photolithographic accuracy. Therefore, the measurement accuracy is improved, and the polishing state of the single crystal silicon island can be clearly determined.

(2) Further, since the area of the polishing state measuring element of the present invention is determined by the electrode opening size, the area is significantly reduced as compared with the conventional structure in which V grooves having different depths are provided. can do.

(3) In addition, a plurality of resistor diffusion layers are formed on the main surface side of the adjacent single crystal silicon island so as to straddle the V groove, and a plurality of resistor diffusion layers are independently formed in the single crystal silicon island according to the number of electrodes. Then, on the support layer between the single crystal silicon islands, each resistor diffusion layer is formed so as to connect with each other, and a plurality of electrodes having different distances symmetrically from the center between the single crystal silicon islands on the resistor diffusion layer. Since the mask alignment deviation can be evaluated by forming a set and measuring the conduction state thereof, automation becomes possible, so that measurement time can be reduced and highly reliable data can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a measuring element in a polished state of a dielectric isolation substrate showing an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional method of measuring a polished state, and FIG. 3 is a plan view of FIG. FIG. 4, FIG. 4 is a view showing a conventional example of measurement of a polished state, FIG. 5 is a view for explaining a conventional method for evaluating a mask alignment deviation with respect to a separation island, and FIG. 6 is another embodiment of the present invention. FIG. 7 is a configuration diagram of a measurement element of a mask alignment shift of a dielectric isolation substrate, FIG.
The figure is an enlarged plan view of the mask alignment displacement measuring element in the X-ray axis direction, and FIG. 8 is a schematic diagram of the equivalent circuit of FIG. 11,31 ... Dielectric separation substrate, 12,32 ... Support layer, 13,33
…… Isolation insulation film, 14,34 …… Isolation island, 15,35 …… Resistance diffusion layer, 16,36 …… Insulation film, 17,37 …… Electrode extraction hole, 18a, 18
b ... Electrode wiring.

Claims (5)

(57) [Claims] 1. A method for measuring a polished state of a dielectric isolation substrate, comprising: (a) forming a plurality of single crystal silicon islands on a dielectric isolation substrate having a moat having a constant height via an isolation insulating film; b) forming a plurality of single-crystal silicon islands and a plurality of opposite-conductivity-type resistor diffusion layers extending over exposed portions of the support layer between the single-crystal silicon islands on the main surface side of the adjacent single-crystal silicon islands; Forming a plurality of sets of electrodes having different distances symmetrically from the center between the single-crystal silicon islands on the resistor diffusion layer; and (d) applying a voltage between each set of electrodes to form a dielectric isolation substrate. A method for measuring a dielectric isolation substrate, wherein a polishing state is electrically measured. 2. An apparatus for measuring a polished state of a dielectric isolation substrate, comprising: (a) a plurality of single-crystal silicon islands formed on a dielectric isolation substrate having a moat having a constant height via an isolation insulating film; (B) a plurality of single-crystal silicon islands formed across the exposed portion of the support layer between the single-crystal silicon islands on the main surface side of the adjacent single-crystal silicon islands and a resistor diffusion layer of a reverse conductivity type; (C) a plurality of sets of electrodes formed on the resistor diffusion layer at different distances symmetrically from the center between the single-crystal silicon islands at different distances; and (d) applying a voltage between each set of electrodes. Means for electrically measuring the polished state of the dielectric isolation substrate by applying the voltage to the dielectric isolation substrate. 3. A method of measuring a mask alignment shift of a dielectric isolation substrate, comprising: (a) forming a plurality of single-crystal silicon islands on a dielectric isolation substrate having a moat having a constant height via an isolation insulating film; (B) A single-crystal silicon island and a resistor diffusion layer of the opposite conductivity type extending over the exposed portion of the support layer between the single-crystal silicon islands on the main surface side of the adjacent single-crystal silicon island are formed in the single-crystal silicon island. A plurality of independent sets are formed, and in the exposed portion of the support layer, the independent resistor diffusion layers are formed to be short-circuited; (c) a center between the single crystal silicon islands on the resistor diffusion layer; (D) applying a voltage between each pair of electrodes to electrically measure a mask alignment shift; Measuring method. 4. An apparatus for measuring a mask alignment shift of a dielectric isolation substrate, comprising: (a) a plurality of single-crystal silicon islands formed on a dielectric isolation substrate having a constant height moat via an isolation insulating film; (B) a plurality of independent sets of single-crystal silicon islands are formed in the single-crystal silicon islands over the exposed portions of the support layer between the single-crystal silicon islands on the main surface side of the adjacent single-crystal silicon islands to expose the support layer; A single-crystal silicon island for short-circuiting the independent resistor diffusion layer and a resistor diffusion layer of the opposite conductivity type; and (c) a distance symmetrically on the resistor diffusion layer from the center between the single-crystal silicon islands. A plurality of sets of electrodes formed with different intervals from each other; and (d) means for applying a voltage between each set of electrodes to electrically measure mask alignment deviation. Measurement device for body separation substrate. 5. An apparatus for measuring misalignment of a mask of a dielectric isolation substrate, comprising: (a) a plurality of single-crystal silicon islands formed on a dielectric isolation substrate having a constant height moat via an isolation insulating film; (B) a plurality of sets independently in the single-crystal silicon island extending over the exposed portion of the support layer along the X-axis direction and the Y-axis direction between the single-crystal silicon islands on the main surface side of the adjacent single-crystal silicon island; A single-crystal silicon island for short-circuiting the independent resistor diffusion layer at an exposed portion of the support layer and a resistor diffusion layer of a reverse conductivity type; and (c) the single crystal on the resistor diffusion layer. A plurality of pairs of electrodes formed at different distances symmetrically from the center between the silicon islands, and (d) means for applying a voltage between each pair of electrodes to electrically measure mask alignment deviation. Dielectric characterized by comprising Measurement device for body separation substrate.