JP2891194B2 - Bus driver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] 1. Field of the Invention [0002] The present invention relates to a bus driver, and more particularly to a bus driver in which ringing occurring in an output waveform is reduced.

[0001]

2. Description of the Related Art Conventionally, this kind of bus driver is provided in each of a plurality of electronic circuit packages, and each of the plurality of packages is electrically connected to a bus via a bus driver.

FIG. 17 is a diagram showing a connection relationship between a plurality of electronic circuit packages and a bus. In the figure, bus B is
, And C7, and bus terminating resistors R1 and R2. Connector C1,
.. And C7 have an electronic circuit package, for example, L
SI (Large Scale Integrated Circuit) package PKG-1, ...
And PKG-7 are respectively connected. Connector C
, And C7 and each of PKG-1,..., And PKG-7 are connected via stubs. The bus terminating resistors R1 and R2 terminate both ends of the bus B. Each of the plurality of PKG-1,..., And PKG-7 is provided with a bus driver.

As shown in FIG. 18, a conventional bus driver is a MOS (Metal Oxide Semiconductor).
ndulator) is an open drain type structure using the transistor 109. That is, the source terminal S of the MOS transistor 109 is connected to the ground level,
The drain terminal D is connected to the output terminal T. When a signal to be output from the LSI package is applied to the gate terminal G of the MOS transistor 109 via the input terminal of the bus driver, the MOS transistor 109 turns on and off according to the state of the signal. When the MOS transistor 109 is turned on, the output terminal T goes to the ground level. On the other hand, when the MOS transistor 109 is turned off, the output terminal T enters a floating state.

Referring to FIGS. 17 and 18, an output terminal T of a bus driver 19 is connected to connectors C1,..., C7.

[0005] An example of such a bus driver is disclosed in Japanese Patent Application Laid-Open No. 2-242313.

[0006]

In the bus B of FIG. 17, the space between the connectors C1 and C2 is 1.4 inches, the space between the connectors C2 and C3 is 2.0 inches, and the space between the connectors C3 and C4 is 1.8 inches, 1.8 inches between connectors C4 and C5, 2.0 inches between connectors C5 and C6, and 1.0 inches between connectors C6 and C7. Suppose there is. Further, in a state where each LSI package is connected to the connector, it is assumed that the length of the stub from the circuit element on the LSI package to the connector is 1.0 inch. Further, it is assumed that the resistances of the terminating resistors R1 and R2 are both 56 [Ω], and the resistors R1 and R2 are connected to a 1.5 volt DC power supply VT. in this case,
LSI package PKG-3 connected to connector C3
LSI packages PKG-1, PKG-3,... Obtained by output waveforms from the output terminals of the bus driver
Simulation waveforms at the output terminals of the PKG-7 and PKG-7 bus drivers are as shown in FIG.

A curve 73 is a waveform in the LSI package PKG-3, a curve 74 is a waveform in the LSI package PKG-4, a curve 71 is a waveform in the LSI package PKG-1, a curve 75 is a waveform in the LSI package PKG-5, and a curve 76 is A waveform in the LSI package PKG-6 and a curve 77 are waveforms in the LSI package PKG-7. In the figure, the vertical axis is the voltage value volt, and the horizontal axis is the time nanosecond.

As shown in FIG. 1, when the output waveform of the bus driver of the LSI package PKG-3 rises, that is, when the MOS transistor in the bus driver transitions from the on state to the off state, ringing occurs in each output waveform. Has occurred. In particular, the curve 75, which is a waveform in the LSI package PKG-5, has large ringing and is hard to fit.

As described above, the conventional bus driver has a problem that ringing occurs in the output waveform.

[0010] This is considered to be caused by reflection from each line constituting the bus. The ringing waveform in the curve 75 oscillates up and down around the terminal potential of 1.5 volts, and in particular, may drop below V1 of about 1.0 volt.

As described above, since a large ringing occurs in the conventional bus driver, it is difficult to transmit a waveform having a small pulse width, that is, a signal having a high repetition frequency. Therefore, there is a problem that it is difficult to use a conventional bus driver for data transfer on a high-speed bus.

An object of the present invention is to provide a bus driver in which ringing generated in an output waveform is reduced.

[0013]

According to the present invention, there is provided a bus driver comprising: an input terminal; an output terminal connected to a bus; and a signal applied to the input terminal. A transistor for outputting to a terminal; and a diode connected between the transistor and a power supply.

Further, another bus driver according to the present invention includes an input terminal, an output terminal connected to a bus, a control terminal connected to the input terminal, and a first node connected to a first power supply. And a second node connected to the output terminal, the transistor forming a current path from the second node to the first node by an input provided from the input terminal to the control end point. And a diode connected between a second node of the transistor and a second power supply to form a current path from the second node of the transistor to the second power supply.

Further, another bus driver of the present invention is characterized in that a plurality of diodes are connected in series to the diode.

Further, another bus driver according to the present invention is characterized in that a plurality of diodes are connected in parallel to the diode.

Further, another bus driver according to the present invention is characterized in that the second power supply is maintained at a terminal potential of the bus.

Further, another bus driver of the present invention includes an input terminal, an output terminal connected to a bus, a transistor for driving a signal applied to the input terminal and outputting the signal to the output terminal, And a power supply connected between the power supply and the power supply.

According to another bus driver of the present invention, an input terminal, an output terminal connected to a bus, a control end point connected to the input terminal, and a first node connected to a first power supply are provided. And a second node connected to the output terminal, the transistor forming a current path from the second node to the first node by an input provided from the input terminal to the control end point. And a circuit provided between the second end point of the transistor and a second power supply, the circuit including at least one diode and at least one capacitive element.

In another bus driver according to the present invention, the second power supply is maintained at a ground potential.

In another bus driver of the present invention, the circuit includes one diode and one capacitive element,
The invention is characterized in that the diode and the capacitive element are connected in series.

In another bus driver according to the present invention, the circuit is configured such that the circuit includes a capacitive element connected to a second node of the transistor, an anode connected to the capacitive element, and the first power supply. A diode having a connected cathode.

In another bus driver according to the present invention, the circuit comprises: a first capacitive element connected to a second node of the transistor; and a second capacitor connected to the second power supply. And a diode having an anode connected to the first capacitive element and a cathode connected to the second capacitive element.

In another bus driver according to the present invention, the circuit comprises: a first capacitive element connected to a second node of the transistor; and a second capacitor connected to the second power supply. A plurality of diodes connected in series, each including a capacitive element, one diode having an anode connected to the first capacitive element, and another diode having a cathode connected to the second capacitive element. And

In another bus driver according to the present invention, the transistor is a MOS transistor.

In another bus driver of the present invention, the transistor is an NPN transistor.

In another bus driver according to the present invention, the transistor is a PNP transistor.

Another bus driver according to the present invention is characterized in that the second power supply is maintained at a potential lower than the terminal potential of the bus.

[0029]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a bus driver 10 according to the present invention includes an input terminal I to which an output signal to be output from an LSI package is applied, an output terminal T connected to a bus B, a MOS transistor 101, , A diode 201.

The gate G of the MOS transistor 101 is connected to the input terminal I of the bus driver 10, the source S is connected to a low potential power supply, and the drain D is connected to the bus driver 10.
Are connected to the output terminal T. The low potential power supply is the ground GND in this embodiment. The diode 201 has an anode connected to the drain D of the MOS transistor 101 and a cathode connected to a high-potential power supply. In this embodiment, the high-potential power supply has a terminal potential of the bus of 1.5 volts. The diode 201 uses a Schottky diode. At this time, the forward voltage is 0.4 volt. In this embodiment, this is represented as Vf. Diode 201 is MO
The drain D of the S transistor 101 and the terminal potential V of the bus
And T.

Next, the operation of this embodiment will be described.

In FIG. 1 and FIG. 2, when the MOS transistor 101 transitions from the on state to the off state, the output waveform sent from the output terminal of the bus driver 10 to the bus after the transition state has been reached. Converges to 5 volts.

The output waveform sent to the bus includes a plurality of LSs.
Vibration around the terminal potential of the bus, that is, ringing occurs due to reflection from the I package. The diode 201 clamps a waveform component having a higher potential than (VT + Vf) on the bus to remove ringing of the output waveform of the bus driver. More specifically, (VT + Vf) on the bus
The higher-potential waveform component is discharged to the higher-potential power supply terminal via the diode 201.

Referring to FIG. 2, the bus driver 10 corresponds to FIG.
3 shows simulation results of output waveforms of the respective LSI packages in a state where the LSI packages are connected to the bus. As is apparent from the figure, in the present embodiment, the convergence is faster than the ringing of the output waveform of the conventional bus driver shown in FIG.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. The features of the second embodiment are:
The point is that an NPN transistor is used in place of the MOS transistor of the first embodiment. Other configurations are the same as those of the first embodiment.

Referring to FIG. 3, NPN transistor 4
The base b of 01 is connected to the input terminal I of the bus driver 11a, the emitter e is connected to a low potential power supply, and the collector c is connected to the output terminal T of the bus driver 11a. The low potential power supply is the ground GND in this embodiment. The diode 202 has an anode connected to the collector c of the NPN transistor 401 and a cathode connected to a high-potential power supply.

FIG. 4 shows the NP in the embodiment shown in FIG.
This is an example in which a PNP transistor is used instead of the N transistor. Base b of NPN transistor 402
Is connected to the input terminal I of the bus driver 11b, the collector c is connected to a low-potential power supply, and the emitter e is connected to the output terminal T of the bus driver 11b. The diode 203 has an anode connected to the emitter e of the PNP transistor 402 and a cathode connected to a high-potential power supply.

Next, a third embodiment of the present invention will be described in detail with reference to the drawings. The features of the third embodiment are as follows.
It includes a plurality of diodes connected in series. Other configurations are the same as those of the first embodiment.

Referring to FIG. 5, the bus driver 12 in the third embodiment includes a diode group 21 composed of a plurality of diodes 211,... 212 connected in series. The diode group 21 is provided between the drain D of the MOS transistor 102 of the bus driver and the terminal potential of the bus. The anode of the diode 211 is connected to the drain D of the MOS transistor 102, and the diode 212
Are connected to a high-potential power supply. In the present embodiment, it is assumed that the number of the plurality of diodes 211,..., 212 is N (N is an integer of 2 or more), and that all of the forward potentials are Vf.

Next, the operation of this embodiment will be described.

In FIG. 5, the diode group 21 clamps a waveform component having a higher potential than (VT + N × Vf) on the bus, and removes ringing of the output waveform of the bus driver 12. More specifically, a waveform component having a higher potential than (VT + N × Vf) on the bus is discharged to a high-potential power supply terminal via the diode group 21.

In this embodiment, the potential level (VT + N × Vf) for removing ringing can be more easily adjusted by adjusting the number of diodes constituting the diode group 21.

In this embodiment, an NPN transistor may be used instead of the MOS transistor. In this case, the base of the NPN transistor is connected to the input terminal I, the emitter is connected to a low-potential power supply, and the collector is connected to the anode of the diode. Further, a PNP transistor may be used instead of the MOS transistor. In this case, the base of the PNP transistor is connected to the input terminal I, the collector is connected to a low-potential power supply, and the emitter is connected to the anode of the diode.

Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. The features of the fourth embodiment are as follows.
It includes a plurality of diodes connected in parallel. Other configurations are the same as those of the first embodiment.

Referring to FIG. 6, a bus driver 13 according to the fourth embodiment includes a plurality of diodes 22 connected in parallel.
1, ... 222 are included. The diode group 22 is the MOS transistor 1 of the bus driver.
03 and the terminal potential of the bus. , 222 are connected to the drain D of the MOS transistor 103, and the cathodes of the diodes 221,..., 222 are connected to a high-potential power supply. The forward voltage of the diode group 22, that is, the clamp voltage is V
fp.

Next, the operation of this embodiment will be described.

Referring to FIG. 6, diode group 22 clamps a waveform component having a higher potential than (VT + Vfp) on the bus to eliminate ringing of the output waveform of bus driver 13. More specifically, a waveform component having a higher potential than (VT + Vfp) on the bus is discharged to a high-potential power supply terminal via the diode group 22.

In this embodiment, a diode group 22 is provided between the drain D of the MOS transistor 103 of the bus driver and the terminal potential of the bus. Therefore, the following two effects can be obtained.

First, when adjusting the potential level for removing ringing, when the number of diodes constituting the diode group 22 is sufficiently large, only the value VT of the terminal potential of the bus need be considered. That is, it is not necessary to consider the clamp potential of each of the plurality of diodes constituting the diode group 22.

Second, since the area of the current path in the diode group 22 increases in proportion to the number of diodes constituting the diode group, the removal of noise due to ringing is prompt, and the output waveform from the bus driver to the bus is reduced. Convergence is faster.

In this embodiment, an NPN transistor may be used instead of the MOS transistor. In this case, the base of the NPN transistor is connected to the input terminal I, the emitter is connected to a low-potential power supply, and the collector is connected to the anodes of the plurality of diodes. Further, a PNP transistor may be used instead of the MOS transistor. In this case, the base of the PNP transistor is connected to the input terminal I,
The collector is connected to the low potential power supply, and the emitter is connected to the anode of the diode.

Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. The features of the fifth embodiment are as follows.
The point is that the diode is provided between the transistor and a potential lower than the terminal potential of the bus. Other configurations are the same as those of the first embodiment.

Referring to FIG. 7, in the bus driver 14 according to the fifth embodiment, a diode 231 is
It is provided between the drain D of the transistor 104 and the potential LVT lower than the terminal potential of the bus. The value of LVT is
It is obtained by dividing the value of the terminal potential of the bus by a general technique of resistance division of voltage.

Next, the operation of this embodiment will be described.

In FIG. 7, a diode group 21 clamps a waveform component having a higher potential than (LVT + Vf) on the bus to remove ringing of the output waveform of the bus driver 14. More specifically, a waveform component having a higher potential than (LVT + Vf) on the bus is discharged via the diode 231 to a potential LVT lower than the terminal potential of the bus.

FIG. 8 shows a bus driver 1 in this embodiment.
4 shows a simulation result of a waveform of each LSI package in a state where it is connected to the bus of FIG. According to the bus driver 14 of the present embodiment, convergence is faster than the ringing of the output waveform of the conventional bus driver shown in FIG.

In this embodiment, the potential level (LVT + Vf) for removing ringing can be freely set by changing the LVT.

In this embodiment, an NPN transistor may be used instead of the MOS transistor. In this case, the base of the NPN transistor is connected to the input terminal I, the emitter is connected to a low-potential power supply, and the collector is connected to the anode of the diode. Further, a PNP transistor may be used instead of the MOS transistor. In this case, the base of the PNP transistor is connected to the input terminal I, the collector is connected to a low-potential power supply, and the emitter is connected to the anode of the diode.

In the above-described second, third or fourth embodiment, the value of the high potential power supply terminal may be set to a potential lower than the terminal potential of the bus.

Next, a sixth embodiment of the present invention will be described in detail with reference to the drawings. The features of the sixth embodiment are:
In other words, the circuit includes a circuit including one diode and one capacitor. Other configurations are the same as those of the first embodiment.

Referring to FIG. 9, in the bus driver 15 of the sixth embodiment, a diode 241 and a capacitor 3
01 is connected between the drain D of the MOS transistor 105 and the DC power source maintained at the potential LVT lower than the terminal potential VT of the bus. One end of the capacitor 301 is connected to the drain D of the MOS transistor 105, and the other end of the capacitor 301 is connected to the anode of the diode 241. Diode 2
12 has a potential L lower than the terminal potential VT of the bus.
Connected to VT.

A potential LVT lower than the terminal potential VT of the bus
Is set to a lower voltage value because the terminal potential of the bus is 1.5 volts. Here, assuming that the diode is a PN diode, the forward voltage Vf is generally about 0.8 volt. Therefore, in this example, the value of the potential LVT is set to 1.0 volt in view of a margin of 0.2 volt.

Next, the operation of this embodiment will be described.

In FIG. 9, the capacitor 301 is
When the S-transistor 105 transitions from the on-state to the off-state, it is charged via the output terminal by the potential LVT lower than the terminal potential of the bus. In this embodiment, the capacitor 301 is provided, but a component having a capacitance can be used.

When the charged value of the capacitor 301 exceeds a predetermined threshold value determined by the forward voltage Vf of the diode 241 and the value of the power supply LVT, the diode 241 discharges the charge stored in the capacitor 301 to the power supply LVT. As described above, since the capacitor 301 is charged at the time of the level transition and discharged when the charge value exceeds the predetermined threshold value, the disturbance of the rising waveform is absorbed and the convergence of the ringing is accelerated.

FIG. 10 shows a simulation result of the waveform of each LSI package when the bus driver 15 of this embodiment is connected to the bus of FIG. According to the bus driver 15 of the present embodiment, the convergence is faster than the ringing of the output waveform of the conventional bus driver shown in FIG. Therefore, by using the bus driver 15 of this embodiment, it is possible to transmit a waveform having a small pulse width, that is, a signal having a high repetition frequency.

In this embodiment, a capacitor is provided which is charged by the terminal potential when the level of the binary signal changes.
By discharging the capacitor when the charge value of the capacitor exceeds a predetermined threshold value, the convergence of ringing is accelerated. Therefore, by using the bus driver 15 in the present embodiment, a high-speed bus can be easily realized. You can.

In this embodiment, the same effect can be obtained even if the order of connection between the capacitor 301 and the diode 241 is changed.

Further, in this embodiment, the value of the power supply LVT is set to a potential lower than the terminal potential of the bus, but this may be the terminal potential of the bus.

Further, in this embodiment, an NPN transistor may be used instead of the MOS transistor.
In this case, the base of the NPN transistor is connected to the input terminal I.
The emitter is connected to a low-potential power supply, and the collector is connected to the capacitor 301. Further, a PNP transistor may be used instead of the MOS transistor. In this case, the base of the PNP transistor is the input terminal I, the collector is the low potential power supply, and the emitter is the capacitor 301.
Connected to each other.

Next, a seventh embodiment of the present invention will be described in detail with reference to the drawings. The features of the seventh embodiment are:
In the bus driver of the sixth embodiment, a capacitor is provided between the diode and the power supply LVT. Other configurations are the same as those of the fifth embodiment.

Referring to FIG. 11, in the bus driver 16 of the sixth embodiment, a circuit in which a capacitor 311, a diode 251, and a capacitor 312 are connected in series forms a drain D of the MOS transistor 106 and a terminal potential VT of the bus. It is provided between the lower potential LVT.
One end of the capacitor 311 is connected to the drain D of the MOS transistor 106, and the other end of the capacitor 311 is connected to the anode of the diode 251. The cathode of the diode 251 is connected to one end of the capacitor 312, and the other end of the capacitor 312 is connected to a potential LVT lower than the terminal potential VT of the bus.

Next, the operation of this embodiment will be described.

In FIG. 11, the capacitor 311 is charged when the output level of the transistor 106 changes. When the charged value of the capacitor 311 exceeds a predetermined threshold value and the diode 251 discharges the capacitor 311, the capacitor 312 is further charged. The charge stored in the capacitor 312 is discharged to the power supply LVT.

FIG. 12 shows a simulation result of a waveform of each LSI package when the bus driver 16 of this embodiment is connected to the bus of FIG. According to the bus driver 16 of the present embodiment, the rise time of each waveform is shorter than in the case of FIG. This is because two capacitors are connected in series.

In this embodiment, a capacitor 311 is provided which is charged by the terminal potential when the level of the binary signal changes. Further, another capacitor 312 is provided for discharging the charge stored in the capacitor 311 to the power supply LVT when the charge value of the capacitor 311 exceeds a predetermined threshold. Therefore, the convergence of the ringing is fast and the rise time of the waveform is short, so that a faster bus can be realized.

In this embodiment, the capacitors 311 and 312 are used. However, the present invention is not limited to this, and capacitive components can be used.

Since the capacitor 312 is inserted, the voltage value of the power supply LVT can have a certain degree of freedom. For example, the power supply terminal V may be connected to the ground potential.

Further, in this embodiment, an NPN transistor may be used instead of the MOS transistor.
In this case, the base of the NPN transistor is connected to the input terminal I.
The emitter is connected to a low-potential power supply, and the collector is connected to the capacitor 311. Further, a PNP transistor may be used instead of the MOS transistor. In this case, the base of the PNP transistor is the input terminal I, the collector is the low potential power supply, and the emitter is the capacitor 311.
Connected to each other.

Next, an eighth embodiment of the present invention will be described in detail with reference to the drawings. The features of the eighth embodiment are:
Compared with the bus driver of the seventh embodiment, a diode group including a plurality of diodes is provided. Other configurations are the same as those of the seventh embodiment.

Referring to FIG. 13, in the bus driver 17 of the eighth embodiment, a circuit in which a capacitor 321, a diode group 26, and a capacitor 322 are connected in series is connected to the drain D of the MOS transistor 107 and the terminal potential of the bus. It is provided between a potential LVT lower than VT.
The diode group 26 includes a plurality of diodes 261,.
62. One end of the capacitor 321 is connected to the drain D of the MOS transistor 107.
The other end of 1 is connected to the anode of a diode 261 constituting a diode group. The cathode of the diode 262 constituting the diode group is connected to one end of the capacitor 322, and the other end of the capacitor 322 is connected to the potential LVT lower than the terminal potential VT of the bus.

FIG. 14 shows a simulation result of the waveform of each LSI package when the bus driver 17 of this embodiment is connected to the bus of FIG. According to the bus driver 17 of this embodiment, the convergence of ringing in each waveform is faster than in the case of FIG.

In this embodiment, a plurality of diodes 261,
.., 262 are provided. Therefore, the threshold value for discharging the charge stored in the capacitor 321 to the power supply terminal V can be easily adjusted by adjusting the number of the plurality of diodes.

In this embodiment, an NPN transistor may be used instead of the MOS transistor. In this case, the base of the NPN transistor is connected to the input terminal I, the emitter is connected to a low potential power supply, and the collector is connected to the capacitor 321. Further, a PNP transistor may be used instead of the MOS transistor. In this case, P
The base of the NP transistor is connected to the input terminal I, the collector is connected to a low-potential power supply, and the emitter is connected to the capacitor 321.

Next, a ninth embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 15, the power supply terminal V is connected to the ground potential. In the present embodiment, the power supply terminal V is connected to a potential lower than the terminal potential of the bus. However, since the capacitor 322 is inserted, the voltage value of the power supply V can have some degree of freedom.

FIG. 16 shows a simulation result of the waveform of each LSI package when the bus driver 18 of this embodiment is connected to the bus of FIG. According to the bus driver 18 of the present embodiment, the convergence of ringing in each waveform is faster than in the case of FIG.

In this embodiment, the power supply terminal V is connected to the ground potential. Therefore, there is no need to generate a potential for the power supply terminal V by dividing the terminal potential of the bus.

In this embodiment, an NPN transistor may be used instead of the MOS transistor. In this case, the base of the NPN transistor is connected to the input terminal I, the emitter is connected to a low potential power supply, and the collector is connected to the capacitor 331. Further, a PNP transistor may be used instead of the MOS transistor. In this case, P
The base of the NP transistor is connected to the input terminal I, the collector is connected to the low potential power supply, and the emitter is connected to the capacitor 331.

In the above embodiment, it is apparent that the convergence of not only the ringing at the rising edge of the waveform but also the ringing at the falling edge can be accelerated.

Further, the diode in the above embodiment may be either a Schottky diode or a PN diode.

[0093]

As is apparent from the above description, according to the present invention, a diode is provided between the drain D of the transistor of the bus driver and the terminal potential of the bus. Therefore, a waveform component having a higher potential than a predetermined potential on the bus is clamped, and ringing of the output waveform of the bus driver is removed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform chart of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is another circuit diagram of the second embodiment of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a fifth embodiment of the present invention.

FIG. 8 is a waveform chart of a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram of a sixth embodiment of the present invention.

FIG. 10 is a waveform chart of a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram of a seventh embodiment of the present invention.

FIG. 12 is a waveform chart of a seventh embodiment of the present invention.

FIG. 13 is a circuit diagram of an eighth embodiment of the present invention.

FIG. 14 is a waveform chart of an eighth embodiment of the present invention.

FIG. 15 is a circuit diagram of a ninth embodiment of the present invention.

FIG. 16 is a waveform chart of a ninth embodiment of the present invention.

FIG. 17 is a diagram illustrating a connection relationship between a plurality of circuit packages and a bus.

FIG. 18 is a conventional circuit diagram.

FIG. 19 is a conventional waveform diagram.

[Explanation of symbols]

, 19 Bus driver 11a, 11b Bus driver 101, ..., 109 MOS transistor 401 NPN transistor 402 PNP transistor 201, 202, 203 Diode 21 Diode group 211, 212 Diode 22 Diode group 221, 222 Diode 231 Diode 241 Diode 251 Diode 26 Diode group 261, 262 Diode 27 Diode group 271, 272 Diode 301, 311, 321, 322, 331, 332 Capacitor

Claims (11)

(57) [Claims] An input terminal; an output terminal connected to a bus; a transistor for driving a signal applied to the input terminal to output to the output terminal; and a diode connected between the transistor and a power supply. And a circuit comprising a capacitive element. 2. An input terminal, an output terminal connected to a bus, a control terminal connected to the input terminal, a first node connected to a first power supply, and a terminal connected to the output terminal. A transistor having a second node, forming a current path from the second node to the first node by an input given from the input terminal to the control terminal; a second terminal of the transistor At least one diode and at least one
And a circuit comprising two capacitive elements. 3. The bus driver according to claim 2, wherein said transistor is a MOS transistor. 4. The bus driver according to claim 2, wherein said transistor is an NPN transistor. 5. The bus driver according to claim 2, wherein said transistor is a PNP transistor. 6. The bus driver according to claim 2, wherein said second power supply is maintained at a potential lower than a terminal potential of a bus. 7. The bus driver according to claim 2, wherein said second power supply is kept at a ground potential. 8. The bus driver according to claim 2, wherein the circuit includes one diode and one capacitive element, and the diode and the capacitive element are connected in series. 9. The circuit, comprising: a capacitive element connected to a second node of the transistor; a diode having an anode connected to the capacitive element and a cathode connected to the first power supply; 3. The bus driver according to claim 2, comprising: 10. The circuit, comprising: a first capacitive element connected to a second node of the transistor; a second capacitive element connected to the second power supply; and the first capacitor An anode connected to the conductive element and the second
3. A bus driver according to claim 2, further comprising: a diode having a cathode connected to said capacitive element. 11. The circuit comprises: a first capacitive element connected to a second node of the transistor; a second capacitive element connected to the second power supply; and the first capacitor A plurality of diodes connected in series, each including one diode having an anode connected to the capacitive element and another diode having a cathode connected to the second capacitive element. Item 2. The bus driver according to item 2.