JP2885021B2 - Frequency multiplier / mixer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier / mixer circuit, and more particularly to a frequency multiplier / mixer circuit formed on a semiconductor integrated circuit and capable of operating at a low voltage.

[0002]

2. Description of the Related Art A conventional frequency multiplication / mixer circuit is disclosed in Japanese Unexamined Patent Publication No.
No. 3409 and JP-A-4-240904 shown in FIG.
Is disclosed.

Referring to FIG. 29, a frequency multiplier / mixer circuit according to a first conventional example includes a squaring circuit 41g including two pairs of differential pair transistors Q1d and Q2d and emitters Q3d and Q4d whose emitters are commonly connected. Have. The two transistors Q0a and Q0b are constant current sources for the respective differential pair transistors. The base of the transistor Q0a and Q0b high-frequency signal V _RE is applied is Tatamikasane the base voltage V _F.

In the frequency multiplication / mixer circuit shown in FIG. 29, the differential output current ΔI _OUT is approximated by the following equation 1 with a, b, and c as constants. However, the input voltage of the local frequency signal is V _LO .

[0005]

(Equation 1)

Here, V _T is a thermal voltage, and V _T = kT
/ Q. Here, k is Boltzmann's constant, T is absolute temperature, and q is unit electron charge. Α _Fn is npn
This is the current amplification factor of the transistor. FIG. 30 shows the input / output characteristics of the squaring circuit 41g thus obtained.

The collector current I _O of the transistor Q0a is expressed by the following equation (2).

[0008]

(Equation 2)

When the series is expanded, the collector current I _O is expressed by the following equation (3).

[0010]

(Equation 3)

Here, if | V _RF | << V _T and the second-order and higher-order terms are ignored, the collector current I _O can be approximated by the following equation (4).

[0012]

(Equation 4)

At this time, by substituting Equation 4 into Equation 1, the product V _LO ² V _RF is obtained. V _LO and V _RF are represented by the following Expressions 5 and 6.

[0014]

(Equation 5)

[0015]

(Equation 6)

Then, the product V _LO ² V _RF is expressed by the following equation (7).

[0017]

(Equation 7)

From the above equation (7), the local frequency f _LO of 2
The product of the harmonic (2f _LO ) and the high frequency f _RF cos ｛2π
A term including (2f _LO ) t)｝ cos (2πf _RF t) is obtained. Here, the product is represented by the following Expression 8.

[0019]

(Equation 8)

From equation 8, the local frequency f _LO of 2
Harmonic (2f _LO) and high-frequency frequency f _RF of the sum and difference frequency components (2f _LO + f _RF) and (2f _LO -f _RF) is obtained, the frequency multiplier mixer circuit can be realized. In this case, in order to improve the third-order distortion as a mixer circuit, a method of inserting an emitter resistor into a common-emitter current mirror circuit on which a high-frequency signal voltage is superposed is often used. In order to increase the high-frequency gain by lowering the ground resistance with respect to the high-frequency signal, it is necessary to ground the emitter with a capacitor (capacitor), but the operation principle is as described above.

Referring to FIG. 31, the frequency multiplier / mixer circuit of the second conventional example has a differential output of a square circuit 41 composed of two unbalanced differential pairs having an emitter area ratio of K: 1. The current is turned back by the two current mirror circuits 43b and 44a on the power supply side and the ground side, and the mixer circuit 42A is configured as a drive current for a differential pair to which the high-frequency signal _VRF is input.

The differential output current ΔI of the squaring circuit 41 composed of two unbalanced differential pairs having an emitter area ratio of K: 1 is obtained by the following equations (9) and (10).

[0023]

(Equation 9)

[0024]

(Equation 10)

FIG. 32 shows the squaring circuit 41 thus obtained.
Are shown using the emitter area ratio K as a parameter. The input voltage range of the squaring circuit 41 is the largest when K ≒ 10.5. At this time, if the input voltage range is limited to 2 V _{T or} less, a substantially good square characteristic can be obtained. That is, the input voltage is changed to the local frequency signal V _LO
Then, the local frequency signal V _LO can be doubled. If the input voltage range of the local frequency signal V _LO is limited to 2 V _{T or} less, a filter is not required for the doubled output, and the circuit can be directly connected in circuit and is suitable for LSI. That is, 2
The differential output current ΔI of the multiplying circuit 41 is approximated by the following equation (11).

[0026]

[Equation 11]

Therefore, the differential output current ΔI _OUT of the mixer circuit 42A composed of a differential pair is expressed by the following equation (12).

[0028]

(Equation 12)

In the case of a small signal, the differential output current ΔI _OUT of the mixer circuit 42A is approximated by the following equations (13) and (14).

[0030]

(Equation 13)

[0031]

[Equation 14]

In the above equation (14), the product of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency frequency f _RF cosｃｏ2π
A term including (2f _LO ) t)｝ cos (2πf _RF t) is obtained. Therefore, the second harmonic (2f) of the local frequency f _LO
LO) and the high-frequency frequency f _RF of the sum and difference frequency components (2f _LO
+ F _RF ) and (2f _LO -f _RF ) are obtained.
A mixer circuit can be realized.

[0033]

As described above, the conventional frequency multiplication / mixer circuit can operate at a low voltage of 3 V or less. In addition, there is an advantage that the circuit scale is relatively small, and its utility is great. However, in addition to the above-described conventional circuit example, several types of frequency multiplication / mixer circuits capable of low-voltage operation can be realized as described in detail below.
Further, low-voltage operation and circuit scale reduction can be achieved.

An object of the present invention is to provide a frequency multiplier / mixer circuit which can operate at a low voltage.

[0035]

A frequency multiplier / mixer circuit according to the present invention is a square circuit having a local frequency signal as an input.
A high-frequency signal is input superimposed on the constant current driving the
High frequency signal mixed with twice frequency of local frequency signal
In the constant frequency / mixer circuit,
Two differential pairs or four trucks with offset applied
Transistors are driven by a common current
Consists of

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a frequency multiplier / mixer circuit according to a first embodiment of the present invention. The illustrated frequency multiplier / mixer circuit has a local frequency signal V having a local frequency f _LO.
It has a squaring circuit 41 to which _LO is supplied. The constant current source circuit of the squaring circuit 41 has a transistor Q0. The base of the transistor Q0, the base voltage V _F to a high-frequency frequency f
The high-frequency signal voltage _{VRF of RE} is superposed and applied.

Assuming that the differential output current of the squaring circuit 41 is ΔI _OUT , it is represented by the following equation (15).

[0039]

(Equation 15)

Here, since ΔI _OUT is the differential output current of the squaring circuit 41, f (V _LO ) in the above equation (15) can be expressed by the following equation (16).

[0041]

(Equation 16)

F (V _LO ) is generally the local frequency signal V
_Although the higher order term of the local frequency signal V _LO is included in addition to the second order term of the _LO , the squaring circuit 41 determines that at an appropriate input signal level, the second order term of the local frequency signal V _LO is dominant. It must be a possible circuit. Otherwise, it cannot be called a squaring circuit.

[0043] Since the high-frequency signal voltage V _RF is the square circuit constant current source base over scan voltage V _F applied to the base of the transistor Q0 constituting the circuit 41 is Tatamikasane, the collector current I of the transistor Q0 _O is represented by the following equation (17).

[0044]

[Equation 17]

[0045] Here, I _s is the saturation current. When the above equation (17) is expanded in series, the collector current I _O is expressed by the following equation (18).

[0046]

(Equation 18)

Here, if | V _RF | << V _T and higher-order terms of second order or higher are ignored, the collector current I _O can be approximated by the following equation (19).

[0048]

[Equation 19]

At this time, by substituting equation (19) into equation (15), the product V _LO ² _VRF is obtained. Therefore, as described above, the second harmonic of the local frequency f _LO (2f _LO )
A frequency component of the sum and difference of the high-frequency frequency f _RE (2f _LO + f
_RE ) and (2f _LO −f _RE ) are obtained, and a frequency multiplication / mixer circuit can be realized.

Referring to FIG. 2, a conventional squaring circuit 41
Means that the emitter area ratio shown in the second example of the conventional circuit is K:
One unbalanced differential pair Q1 and Q3, and Q2 and Q4. In this case, f (V _LO ) is given by the following equation (20).
It is represented by

[0051]

(Equation 20)

Similarly, the product V _LO ² V _RF is obtained, and the frequency components (2f _LO + f _RE ) and (2f _LO + f _RE ) of the sum and difference of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency f _RE are obtained. −
f _RE ) is obtained, and a frequency multiplication / mixer circuit can be realized.

Referring to FIG. 3, another squaring circuit 41a
Are two differential pairs Q1a and Q3a and Q2a and Q4a
The same offset voltage V _K is applied to each input, the inputs are cross-connected, and the outputs are connected in parallel.
In this case, f (V _LO ) is represented by the following Expression 21.

[0054]

(Equation 21)

Equations (20) and (21) show that V _K = V _T
It is equivalent to lnK. Therefore, similarly to the circuit shown in FIG. 2, the product V _LO ² _VRF is obtained, and the local frequency f
Second harmonic (2f _LO) frequency components of the sum and difference of the high-frequency frequency f _RE of _LO (2f _LO + f _RE) and (2f _LO -f _RE) is obtained, the frequency multiplier mixer circuit can be realized.

Referring to FIG. 4, a further squaring circuit 4 is shown.
Reference numeral 1b denotes a quadritail cell in which two transistor pairs Q1b and Q2b, Q4b and Q3b having common collectors are driven by a current source I _O , and a differential input voltage V is applied to the first transistor pair Q1b and Q2b. _LO ² is applied, and a midpoint voltage is applied to the second transistor pair Q4b and Q3b. In this case, f (V _LO ) is represented by Expression 22 below.

[0057]

(Equation 22)

FIG. 5 shows the square characteristic shown by the above equation (22). If the input voltage range is limited to | V _LO | <2V _T ,
Almost good square characteristics can be obtained. So, similarly,
The product V _LO ² V _RF is obtained, and the frequency components (2f _LO + f _RF ) and (2f _LO −f _RF ) of the sum and difference of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency f _RF are obtained. Thus, a frequency multiplication / mixer circuit can be realized.

As can be easily analogized, a frequency multiplier / mixer circuit can be realized with a square circuit driven by a constant current.

FIG. 6 shows a frequency multiplier / mixer circuit according to a second embodiment of the present invention. The illustrated frequency multiplier / mixer circuit has a local frequency signal V having a local frequency f _LO.
A square circuit 41 _{which LO} is supplied, and a cross connection emitter-coupled pair 42 a high-frequency signal V _RF is supplied with a high-frequency frequency f _RE, cross connected emitter-coupled pair 42 is square circuit 41 differential Driven by the output current ΔI. The cross-coupled emitter-coupled pair 42, as shown in FIG.
To Q8. Cross-Connected Emitter Couple Pair 42
The differential output current ΔI _OUT is represented by the following equation (23).

[0061]

(Equation 23)

FIG. 7 shows a frequency multiplier / mixer circuit in the case where the squaring circuit 41 comprises two unbalanced differential pairs Q1 and Q3 and Q2 and Q4 having an emitter area ratio of K: 1.

A squaring circuit 4 composed of two unbalanced differential pairs Q1 and Q3 and Q2 and Q4 having an emitter area ratio of K: 1.
The differential output current ΔI of Equation (1) is expressed by the following Expressions 24 and 25
Can be represented by

[0064]

(Equation 24)

[0065]

(Equation 25)

Therefore, the cross-coupled emitter coupling pair 42
Are two pairs of unbalanced differential pairs Q1 having an emitter area ratio of K: 1.
The differential output current ΔI _OUT of the frequency-multiplier / mixer circuit driven by the differential output current ΔI of the squaring circuit 41 composed of Q2 and Q2 and Q4 is obtained by the following equation (26).

[0067]

(Equation 26)

Equation 26 can be developed in exactly the same manner as Equations 24 to 14, and the product of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency f _RF cos ｛2π (2f
A term including _LO ) t {cos (2πf _RF t} is obtained, and therefore, the frequency component of the sum and difference of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency f _RF (2f _LO + f _RF )
And (2f _LO −f _RF ) are obtained, and a frequency multiplication / mixer circuit can be realized.

FIG. 8 shows that the squaring circuit 41c has a gate W / L
Two pairs of MOS transistors M1, M3, M having a ratio of K: 1
2 shows a frequency multiplying / mixing circuit in the case of an unbalanced differential pair consisting of 2 and M4.

The differential output current .DELTA.I of the squaring circuit 41c comprising an unbalanced differential pair consisting of two pairs of MOS transistors M1 and M3 and M2 and M4 having a gate W / L ratio of K: 1.
Is limited by the input voltage, and is represented by the following Expression 27.

[0071]

[Equation 27]

Here, β = μ (Cox / 2) (W / L) is a transconductance parameter, μ is the effective mobility of the carrier, Cox is the gate oxide film capacity per unit area, and W and L are the gates, respectively. Width, gate length.

FIG. 9 shows a squaring circuit 41 realized in this way.
The input / output characteristic of c is shown using K as a parameter. MOS
When a squaring circuit is realized with transistors as described above, the transconductance parameter β, specifically, the value of the gate W / L and the value of the driving current _IO are ideal 2
The input / output voltage range having the square characteristic is determined, and can be set wider than the input voltage range with a small approximation error of the square characteristic of the square circuit 41 shown in FIG.

Therefore, the cross-coupled emitter coupling pair 42
However, the differential output current ΔI of the frequency multiplication / mixer circuit driven by the differential output current ΔI of the squaring circuit 41c composed of two unbalanced differential pairs having a gate W / L ratio of K: 1.
_OUT is obtained by the following Expression 28.

[0075]

[Equation 28]

Therefore, by using the squaring circuit 41c configured as described above, a frequency multiplication / mixer circuit can be similarly realized.

FIG. 10 shows that the squaring circuit 41a includes two unbalanced differential pairs Q1a to which the same offset voltage V _K is applied.
And a frequency multiplying / mixing circuit in the case of comprising Q3a and Q2a and Q4a. That is, the squaring circuit 41
a is the same as that shown in FIG.

Therefore, the differential output current ΔI of the squaring circuit 41a is represented by the following equation (29).

[0079]

(Equation 29)

Therefore, the cross-coupled emitter coupling pair 42
Is the frequency multiplier / mixer circuit driven by the differential output current ΔI of the squaring circuit 41a composed of two unbalanced differential pairs Q1a and Q3a and Q2a and Q4a to which the same offset voltage V _K is applied. The differential output current ΔI _OUT is obtained by the following Expression 30.

[0081]

[Equation 30]

Therefore, by using the squaring circuit 41a configured as described above, a frequency multiplication / mixer circuit can be similarly realized.

FIG. 11 shows a frequency multiplication / mixer circuit when the squaring circuit 41d is composed of two pairs of MOS unbalanced differential pairs M1a and M3a and M2a and M4a to which the same offset voltage V _K is applied. Show. That is, the differential output current ΔI of the squaring circuit 41d is expressed by the following equation 31 when the input voltage is limited.

[0084]

(Equation 31)

The above equation 31 is approximated by the following equation 32.

[0086]

(Equation 32)

According to the approximation formula shown in Expression 32, the differential output current ΔI of the squaring circuit 41d is 2 with respect to the input voltage V _LO .
It can be seen that it has a power characteristic. This approximation formula has a small approximation error and is a very good approximation formula representing the differential output current ΔI of the squaring circuit 41d.

FIG. 12 shows a squaring circuit 41 realized in this way.
The input / output characteristics of d are shown using the offset voltage V _K as a parameter.

Therefore, the cross-coupled emitter coupling pair 42
Are the two pairs of MOs with equal offset voltage V _K applied.
The differential output current ΔI _OUT of the frequency multiplying / mixer circuit driven by the differential output current ΔI of the squaring circuit 41d composed of the S unbalanced differential pairs M1a and M3a, M2a and M4a is
Equation 33 below is obtained.

[0090]

[Equation 33]

Therefore, by using the squaring circuit 41d configured as described above, a frequency multiplication / mixer circuit can be similarly realized.

In FIG. 13, a squaring circuit 41e comprises two transistor pairs Q1c, Q2c, Q
3 shows a frequency multiplying / mixing circuit in the case where 3c and Q4c are quadrutail cells driven by one current source I _O. The differential output current ΔI of the squaring circuit (quadritail cell) 41e is represented by the following Expression 34.

[0093]

(Equation 34)

Therefore, the cross-coupled emitter coupling pair 42
However, the differential output current ΔI _OUT of the frequency-multiplier / mixer circuit driven by the differential output current ΔI of the squaring circuit 41 e composed of quadritail cells is obtained by the following Expression 35.

[0095]

(Equation 35)

Therefore, by using the squaring circuit 41e constituted by quadritail cells in this manner,
A frequency multiplication / mixer circuit can be realized.

FIG. 14 shows that the squaring circuit 41f has two pairs of transistors M1b, M2b, M
3 shows a frequency multiplication / mixer circuit in the case where MOS transistors 3b and M4b are driven by one current source I _O. This squaring circuit (MOS quad tail cell) 41f
When the input voltage is limited, the differential output current ΔI is expressed by the following Expression 36.

[0098]

[Equation 36]

FIG. 15 shows the input / output characteristics of the MOS quadritail cell. Similarly, if the input voltage range is limited,
The differential output current ΔI of the squaring circuit 41f has an ideal square characteristic with respect to the input voltage. That is, the MOS quadritail cell is a squaring circuit.

Therefore, the cross-coupled emitter coupling pair 42
Is a square circuit 41 composed of MOS quadritail cells.
The differential output current ΔI _OUT of the frequency multiplication / mixer circuit driven by the differential output current ΔI of f is obtained by the following Expression 37.

[0101]

(37)

Therefore, by using the squaring circuit 41f constituted by the MOS quadritail cells, a frequency multiplication / mixer circuit can be realized in the same manner.

As can be easily inferred, the differential output current Δ
With a square circuit having I, a frequency multiplication / mixer circuit can be realized.

FIG. 16 shows a frequency multiplier / mixer circuit for driving the cross-coupled emitter-coupled pair 42 with the differential output current of the squaring circuit 41g shown in the first conventional example.

Similarly, FIG. 6 (specifically, FIGS. 7, 8,
The frequency multiplier / mixer circuit shown in FIGS. 10, 11, 13, and 14) may drive the cross-coupled emitter-coupled pair by folding the output current of the squaring circuit with two current mirror circuits. In this case, current consumption increases, but the power supply voltage can be further reduced.

FIG. 17 shows a frequency multiplier / mixer circuit according to a third embodiment of the present invention. Frequency multiplying mixer circuit shown includes a squaring circuit 41A to a local frequency signal V _LO having a local frequency f _LO is supplied, the high-frequency frequency f _RE
And an emitter-coupled pair (differential pair) 42A supplied with a high-frequency signal _VRF having the following relationship. The emitter-coupled pair 42A is driven by the output current I of the squaring circuit 41A. The differential pair 42A is 2
The differential output current ΔI _OUT of the frequency multiplication / mixer circuit driven by the output current I of the multiplying circuit 41A is expressed by the following Expression 38.

[0107]

(38)

Here, as the squaring circuit 41A shown in FIG. 17, the square circuit 41A shown in FIGS.
By using one of the differential output currents in the multiplying circuit, it can be used as it is. At this time, the squaring circuit 4
The output current I of 1 A is represented by the following Expression 39.

[0109]

[Equation 39]

Here, _IE is the total value of the tail current. As described above, since the differential output current ΔI contains a dominant frequency component (2f _LO ) of the local frequency f _LO , similarly, the differential output current ΔI represented by the above equation (38) is obtained.
_OUT has the product of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency frequency f _RE cos ｛2π (2f _LO ) t｝ cos
A term containing (2πf _RE t) is obtained. That is, the frequency components (2f _LO + f _RF ) and (2f _LO −f _RF ) of the sum and difference of the second harmonic (2f _LO ) of the local frequency f _LO and the high frequency frequency f _RF.
RF ) and a frequency multiplication / mixer circuit can be realized.

FIG. 18 shows a modification of the frequency multiplier / mixer circuit according to the third embodiment of the present invention. In the frequency multiplication / mixer circuit shown in FIG.
A is vertically stacked, but the frequency multiplication shown in FIG.
In the mixer circuit, the output current of the squaring circuit 41A is folded back by the two current mirror circuits 43 and 44 to form a differential pair 4A.
2A is being driven. In the case of the frequency multiplication / mixer circuit shown in FIG. 18, the current consumption is increased as compared with that shown in FIG. 17, but the power supply voltage can be further reduced.

FIG. 19 shows a frequency multiplier / mixer circuit according to a fourth embodiment of the present invention. Frequency multiplying mixer circuit illustrated constant current source 2I _O to drive the emitter-coupled pair (differential pair) 42A that receives the radio frequency signal V _RF, of squaring circuit 41B which receives the local frequency signal V _LO Output current is flowing. More specifically, the current mirror circuit 43a including transistors Q9 and Q10
Output current of the multiplication circuit 41B a ([Delta] I or I), when poured into a constant current source 2I _O of the differential pair 42A composed of transistors Q5, Q6 through the transistor Q13, the differential frequency multiplier mixer circuit shown in FIG. 19 Output current ΔI
_OUT is represented by the following Expression 40 or Expression 41.

[0113]

(Equation 40)

[0114]

[Equation 41]

Therefore, a frequency multiplication / mixer circuit can be realized.

FIG. 20 shows a frequency multiplier / mixer circuit according to a fifth embodiment of the present invention. The illustrated frequency multiplying / mixing circuit has two differential pairs 42B composed of two pairs of cross-coupled emitter coupled pairs having an emitter area ratio of 1: 2 ± ２3.
It is driven by the output current of the multiplying circuit 41C. The differential output current ΔI _OUT of the frequency multiplication / mixer circuit is represented by the following equation 42, where ΔI is the output current of the squaring circuit.

[0117]

(Equation 42)

FIG. 21 shows that the emitter area ratio is 1: 2 ± √3
FIG. 22 shows input / output characteristics of a differential pair 42B composed of two pairs of cross-coupled emitter-coupled pairs, and FIG. 22 shows transconductance characteristics. The linearity is improved as compared to a matched differential pair. Therefore, third-order distortion is improved as a mixer circuit.

In the frequency multiplier / mixer circuit shown in FIG. 20, the output current of the squaring circuit may be turned back by two current mirror circuits to drive the cross-coupled emitter-coupled pair. In this case, current consumption increases, but the power supply voltage can be further reduced.

FIG. 23 shows a frequency multiplier / mixer circuit according to a sixth embodiment of the present invention. In the illustrated frequency multiplication / mixer circuit, similarly to the one shown in FIG. 20, a differential pair 42C composed of two pairs of cross-coupled emitter coupling pairs having an emitter area ratio of 1: 2 ± √3 is squared. It is driven by the output current of the circuit 41D. Also in this example, since the differential pair 42C composed of two pairs of cross-coupled emitter-coupled pairs having an emitter area ratio of 1: 2 ± 3 is used, the linearity is lower than that of the matched differential pair. Be improved. The differential output current ΔI _OUT of the frequency multiplication / mixer circuit is represented by the following Expression 43.

[0121]

[Equation 43]

Therefore, as described above, even if I is one of the differential output currents of the squaring circuit, a frequency multiplication / mixer circuit can be realized. Also in this case, the linearity is improved as compared with the matched differential pair.

Similarly, in the frequency multiplication / mixer circuit shown in FIG. 23, two current mirror circuits may be used to return the output current of the squaring circuit to drive the cross-coupled emitter-coupled pair. In this case, current consumption increases, but the power supply voltage can be further reduced.

FIG. 24 shows a frequency multiplier / mixer circuit according to a seventh embodiment of the present invention. The illustrated frequency multiplier / mixer circuit uses a current mirror circuit 43b including transistors Q9, Q10a, and Q10b to output the output current (ΔI or I) of the squaring circuit 41A to the transistors Q21, Q22,
Cross-coupled emitter-coupled pair 42C consisting of Q23 and Q24
If Nagashikome of the constant current source I _O, I _O, frequency multiplier mixer circuit equivalent characteristics shown in FIG. 18 is obtained. Therefore, a frequency multiplication / mixer circuit can be realized.

FIG. 25 shows a frequency multiplier / mixer circuit according to an eighth embodiment of the present invention. In the illustrated frequency multiplier / mixer circuit, the polarity of the transistor forming the squaring circuit 41 and the polarity of the transistor forming the cross-coupled emitter-coupled pair 42D are different from each other. That is, the frequency multiplier / mixer circuit according to the eighth embodiment is a modification of the frequency multiplier / mixer circuit according to the second embodiment shown in FIG. 6, and includes a transistor Q5a forming a cross-coupled emitter-coupled pair 42D,
The polarities of Q6a, Q7a, and Q8a are opposite to those of the transistors Q5, Q6, Q7, and Q8 that form the cross-coupled emitter-coupled pair 42 in the frequency-multiplier / mixer circuit shown in FIG. Assuming that the output current of the squaring circuit 41 is ΔI, the differential output current ΔI _OUT of the cross-coupled emitter-coupled pair 42D is
This is represented by the following Expression 44.

[0126]

[Equation 44]

Where α _Fp is the current amplification factor of the npn transistor.

FIG. 26 shows a frequency multiplier / mixer circuit according to a ninth embodiment of the present invention. In the illustrated frequency multiplying / mixing circuit, the polarity of the transistor forming the squaring circuit 41A and the polarity of the transistor forming the emitter-coupled pair (differential pair) 42E are different from each other. That is, the frequency multiplier / mixer circuit according to the ninth embodiment is a modification of the frequency multiplier / mixer circuit according to the third embodiment shown in FIG. 17, and the transistors Q5a and Q5 forming the emitter-coupled pair 42E.
Transistors Q5 and Q6a constitute an emitter-coupled pair 42A in the frequency multiplier / mixer circuit shown in FIG.
The polarity is opposite to 6. Assuming that the output current of the squaring circuit 41A is I, the differential output current ΔI _OUT of the frequency multiplication / mixer circuit in which the differential pair 42E is driven by the output current I of the squaring circuit 41A is expressed by the following equation 45. You.

[0129]

[Equation 45]

FIG. 27 shows a frequency multiplier / mixer circuit according to the tenth embodiment of the present invention. In the illustrated frequency multiplier / mixer circuit, the polarity of the transistor forming the squaring circuit 41C and the polarity of the transistor forming the two pairs of cross-coupled emitter coupled pairs 42F having an emitter area ratio of 1: 2 ± √3 are different from each other. . That is, the frequency multiplier / mixer circuit according to the tenth embodiment is a modification of the frequency multiplier / mixer circuit according to the fifth embodiment shown in FIG. 20, and includes a transistor Q2 forming two pairs of cross-coupled emitter-coupled pairs 42F.
1a, Q22a, Q23a, Q24a, Q25a, Q2
The polarities of 6a, Q27a and Q28a are two pairs of cross-coupled emitter-coupled pairs 4 in the frequency doubler / mixer circuit shown in FIG.
2B, transistors Q21, Q22, Q23,
The polarity is opposite to that of Q24, Q25, Q26, Q27, and Q28. The differential output current ΔI _OUT of the frequency multiplication / mixer circuit is represented by the following Expression 46 or Expression 47.

[0131]

[Equation 46]

[0132]

[Equation 47]

FIG. 28 shows a frequency multiplier / mixer circuit according to an eleventh embodiment of the present invention. In the illustrated frequency multiplier / mixer circuit, the polarity of the transistor forming the squaring circuit 41D and the polarity of the transistor forming the cross-coupled emitter coupling pair 42G having an emitter area ratio of 1: 2 ± ２3 are different from each other. That is, the frequency multiplier / mixer circuit according to the eleventh embodiment is a modification of the frequency multiplier / mixer circuit according to the sixth embodiment shown in FIG. 23, and includes transistors Q21a and Q22 forming a cross-coupled emitter-coupled pair 42G.
The polarities of a, Q23a, and Q24a are opposite to those of the transistors Q21, Q22, Q23, and Q24 that form the cross-coupled emitter-coupled pair 42C in the frequency multiplication / mixer circuit shown in FIG. The differential output current ΔI _OUT of the frequency multiplication / mixer circuit is represented by the following Expression 48.

[0134]

[Equation 48]

It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various changes / modifications can be made without departing from the spirit of the present invention. For example, in the embodiments shown in FIGS. 25 to 28, the squaring circuit is formed by npn transistors, and the differential pair or cross-coupled emitter pair forming the mixer circuit is formed by pnp transistors. With a pnp transistor, and a differential pair or a cross-coupled emitter pair forming a mixer circuit with np
It is needless to say that a frequency multiplication / mixer circuit can be similarly realized by using n transistors.

[0136]

As described above, the frequency multiplying / mixing circuit of the present invention can operate at a low voltage and has the effect of reducing the power supply voltage to 3 V or less.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a frequency multiplier / mixer circuit according to a first embodiment of the present invention.

2 is a circuit diagram showing a conventional 2 Nomawa path constituting the frequency multiplier mixer circuit shown in FIG.

FIG. 3 is a circuit diagram showing a second example of a squaring circuit constituting the frequency multiplication / mixer circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing a third example of a squaring circuit constituting the frequency multiplication / mixer circuit shown in FIG. 1;

FIG. 5 is an input / output characteristic diagram of the squaring circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing a frequency multiplier / mixer circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating the frequency multiplier / mixer circuit shown in FIG.
FIG. 9 is a circuit diagram showing a frequency multiplication / mixer circuit in a case where the multiplying circuit is constituted by two unbalanced differential pairs having an emitter area ratio of K: 1.

FIG. 8 is a circuit diagram showing the frequency multiplier / mixer circuit shown in FIG.
FIG. 9 is a circuit diagram showing a frequency multiplication / mixer circuit in the case where the multiplication circuit is constituted by an unbalanced differential pair including two pairs of MOS transistors having a gate W / L ratio of K: 1.

FIG. 9 is an input / output characteristic diagram of the squaring circuit shown in FIG. 8;

10 is a circuit diagram showing a frequency multiplier / mixer circuit in the case where the squaring circuit in the frequency multiplier / mixer circuit shown in FIG. 6 includes two unbalanced differential pairs to which equal offset voltages are applied.

11 is a diagram illustrating a frequency multiplier / mixer circuit shown in FIG. 6 in which a square circuit is provided with two pairs of Ms to which equal offset voltages are applied;
FIG. 3 is a circuit diagram illustrating a frequency multiplication / mixer circuit when configured from an OS unbalanced differential pair.

FIG. 12 is an input / output characteristic diagram of the squaring circuit shown in FIG. 11;

FIG. 13 shows a frequency multiplication / mixer circuit in the case of a quadruple cell in which two pairs of transistors whose collectors are commonly connected are driven by one current source in the frequency multiplication / mixer circuit shown in FIG. 6; FIG.

14 is a frequency multiplier / mixer circuit in the case of a MOS quadritail cell in which two pairs of transistors whose squaring circuits have drains commonly connected are driven by one current source in the frequency multiplier / mixer circuit shown in FIG. 6; FIG.

FIG. 15 is an input / output characteristic diagram of the squaring circuit shown in FIG. 14;

16 is a circuit diagram showing a frequency multiplication / mixer circuit using the squaring circuit shown in the first conventional example as a squaring circuit in the frequency multiplication / mixer circuit shown in FIG. 6;

FIG. 17 is a circuit diagram showing a frequency multiplier / mixer circuit according to a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a modification of the frequency multiplier / mixer circuit according to the third embodiment shown in FIG.

FIG. 19 is a circuit diagram showing a frequency multiplier / mixer circuit according to a fourth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a frequency multiplier / mixer circuit according to a fifth embodiment of the present invention.

FIG. 21 is an input / output characteristic diagram of the cross-coupled emitter coupling pair shown in FIG. 20;

FIG. 22 is a diagram showing transconductance characteristics of the cross-coupled emitter coupling pair shown in FIG. 20;

FIG. 23 is a circuit diagram showing a frequency multiplier / mixer circuit according to a sixth embodiment of the present invention.

FIG. 24 is a circuit diagram showing a frequency multiplier / mixer circuit according to a seventh embodiment of the present invention.

FIG. 25 is a circuit diagram showing a frequency multiplier / mixer circuit according to an eighth embodiment of the present invention.

FIG. 26 is a circuit diagram showing a frequency multiplier / mixer circuit according to a ninth embodiment of the present invention.

FIG. 27 is a diagram illustrating a frequency multiplication according to a tenth embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a mixer circuit.

FIG. 28 is a diagram illustrating a frequency multiplying operation according to an eleventh embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a mixer circuit.

FIG. 29 is a circuit diagram showing a frequency multiplier / mixer circuit according to a first conventional example.

30 is an input / output characteristic diagram of a squaring circuit used in the frequency multiplication / mixer circuit shown in FIG. 29;

FIG. 31 is a circuit diagram showing a frequency multiplier / mixer circuit according to a second conventional example.

32 is a diagram showing input / output characteristics of a squaring circuit used in the frequency multiplication / mixer circuit shown in FIG. 31, using an emitter area ratio K as a parameter.

[Explanation of symbols]

41 A squaring circuit composed of two unbalanced pairs having an emitter area ratio of K: 1 41a Cross-connect the inputs by applying equal offset voltages to the inputs of the two differential pairs, and connect the outputs in parallel Circuit 41b A squaring circuit 41c composed of a quaternary cell in which two transistor pairs having collectors connected in common are driven by one current source 41c Two pairs of MOSs having a gate W / L ratio of K: 1 A square circuit 41d composed of an unbalanced differential pair composed of transistors 41d Two pairs of M to which equal offset voltages are applied
A squaring circuit 41e composed of an OS unbalanced differential pair 41e A squaring circuit 41d composed of quadruple cells driven by one current source in which two pairs of transistors commonly connected to a collector 41f Two pairs commonly connected to a drain Circuit composed of a MOS quadritail cell in which the transistor pair is driven by one current source 41g square circuit 41A, 41B, 41C, 41D square circuit 42, 42C, 42D, 42G cross-connecting emitter coupling pair 42A, 42E Emitter-coupled pair (differential pair) 42B, 42F Two cross-coupled emitter-coupled pairs

Claims (2)

(57) [Claims] A high frequency signal is superimposed on a constant current driving a squaring circuit having a local frequency signal as an input, and a high frequency signal is mixed with a double frequency of the local frequency signal and a high frequency signal. 3. The frequency multiplying / mixing circuit according to claim 1, wherein said squaring circuit comprises two differential pairs to which an offset is applied. 2. A frequency multiplying / mixing circuit in which a high frequency signal is input superimposed on a constant current for driving a squaring circuit having a local frequency signal as an input, and a high frequency signal is mixed with a double frequency of the local frequency signal. A frequency multiplying / mixing circuit, wherein the squaring circuit comprises a quadritail cell in which four transistors are driven by a common current.