JP2883990B2 - Frequency synthesizer frequency switching method and frequency synthesizer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency synthesizer frequency switching method and a frequency synthesizer.

[Problems to be Solved by Conventional Techniques and Inventions] A frequency synthesizer is used for a frequency hopping method, a mobile communication, and the like, which are one of spread spectrum communication. In this field, an inexpensive frequency synthesizer capable of high-speed frequency switching is desired. Synthesizer structure methods include direct synthesis, indirect synthesis, and digital synthesis. Among them, the direct synthesis method and the digital synthesis method have a high frequency switching speed, but the former has disadvantages in that the cost is increased by using a large number of filters, and the latter cannot increase the maximum output frequency. On the other hand, indirect synthesis has a drawback that the circuit is simple, but because of the closed loop, it takes time to switch the frequency and cannot be used for high-speed hopping. The main reasons for this are that a reduction filter for obtaining a phase difference is required in the loop, and that the loop time constant increases as the frequency division ratio of the frequency divider increases.

FIG. 4 shows an example of a conventional frequency synthesizer using a PLL. The phase difference between the reference frequency f _ref (phase θ _ref ) and the reproduction output frequency f ₀ (phase θ ₀ ) from the frequency divider 106 is compared by a digital phase comparator 100, and the phase difference φ ( = Θ _ref −θ ₀ ) and input this to the VCO 104. The VCO 104 inputs the output frequency f ₀₁ (phase θ ₀₁ ) to the frequency divider 106 (frequency division ratio N) to obtain f ₀ .

In order to extract a phase difference with a small ripple from the phase comparator 100, a low-pass filter having a considerably low cutoff frequency is required.

Next, ignoring this low-pass filter and assuming that the VCO 104 is linear, this phase-locked loop becomes a first-order lag system as shown below.

That is, f ₀ = f ₀₁ / N or θ ₀ = θ ₀₁ / N by the frequency divider 106 (1) From the characteristics of the VCO 106 ωc; free-running frequency of VCO, k; angular frequency modulation sensitivity of VCO Using equations (1) and (2) and the definition equation of φ, Or Get. Here, τ = N / k; time constant.

From the equation (4), in a steady state, f ₀₁ = Nf _ref (5). By switching N, the frequency can be hopped. By solving equation (4), it can be seen that the time for 99% to settle to the target value equation (5) is 4.6τ, which increases in proportion to N.

As described above, in the conventional frequency synthesizer of indirect synthesis, first, the reduction filter causes a delay in the response, and even if the low-pass filter is ignored, the response delay due to the frequency division ratio of the frequency divider is It can be seen that there are two causes.

Therefore, an object of the present invention is to provide a frequency switching method and a frequency synthesizer of a high-speed indirect synthesis frequency synthesizer that responds with the cycle of the reference frequency.

[Means for Solving the Problems] According to the method of the present invention, a frequency divider is provided in a phase-locked loop, and when a frequency division ratio for the frequency divider is changed to switch an output frequency, a frequency division before the change is previously performed. An output pulse position of the frequency divider corresponding to a ratio is stored, and a pulse corresponding to the stored output pulse position is input to a phase comparator of the phase locked loop as an initial value of a loop, and the frequency division is performed. The response time required for the loop after changing the ratio to reach a steady state is reduced.

The present invention provides a frequency synthesizer in which a frequency divider is provided in a phase-locked loop and an output frequency is switched according to a frequency division ratio set in the frequency divider, wherein a phase difference between the reference frequency and the output frequency is detected. Means for storing a phase difference; and a memory for storing the phase difference; and, when changing a dividing ratio, generating a pulse having a phase difference stored in the memory with respect to the reference frequency, and comparing a phase of the phase locked loop. And pulse generating means for outputting to a vessel.

[Operation] In order to perform frequency hopping, the frequency division ratio N is changed. At this time, a method for quickly bringing the loop into a steady state will be described. By using a primary PLL in the phase locked loop,
The case where the next delay circuit is configured will be described. However, VCO
Has a linear characteristic, and is considered at a time sufficiently larger than the period of the reference frequency. At this time, the characteristics of the PLL are expressed by equations (4) and (5). Now, when the time t = 0 in the frequency division ratio N is to become N ₁ from N phase difference phi (t)
Is Becomes φ (0) is N if it is steady at N
(Ω _ref −ω _C / N) / k, which takes a response time (4.64.6τ ₁ ) due to the transient term in equation (6), and falls to a steady value. However, as φ (0), the value at the last hopping By using, the coefficient of the transient term is Becomes Here, assuming that a stable one is used as ω _ref and that k and ω _C change slowly with respect to temperature, Equation (7) can be regarded as almost zero.
φ (t) completes the response at T _ref . That is, if the previous phase difference with respect to the reference frequency, that is, the output pulse position of the frequency divider corresponding to the previous frequency division ratio is used as the initial value of the loop when changing the frequency division ratio N, a high-speed response can be obtained. It can be realized, and the method and apparatus according to the invention will work on this principle.

Hereinafter, an embodiment of a frequency synthesizer to which the present invention is applied will be described with reference to the drawings.

FIG. 1 shows a frequency synthesizer to which the present invention is applied.
For example, a JK flip-flop 12 that outputs a phase difference between the reference frequency f _ref (phase θ _ref ) and the reproduction output frequency f ₀ (phase θ ₀ ) is provided. Further, an integrator 14 for integrating the output of the JK flip-flop 12 is provided.
A sample hold circuit 16 for holding the output of the integrator 14 is provided. As will be described later, a voltage proportional to the phase difference φ can be obtained as an output of the sample-and-hold circuit 16, and the phase difference φ can be obtained at high speed every cycle as described later.

A VCO 20 is provided at the subsequent stage of the sample and hold circuit 16 and receives the phase difference φ from the sample and hold circuit 16 and outputs an output frequency f ₀₁ (phase θ ₀₁ ). A frequency divider 30 is provided in the middle of the phase locked loop, divides the output frequency f ₀₁ by a frequency division ratio N, and outputs the reproduction output frequency f ₀ (phase θ ₀ ). It is configured to output to the flip-flop 12.

Although the primary PLL is formed by the above configuration, the present embodiment further includes a counter 40 and a memory 50 in addition to a phase locked loop using the primary PLL. The counter 40 also functions as the phase difference detecting means and the pulse generating means of the present invention. This counter 40 is provided by the frequency divider
In order to measure the initial value φ (0) of the loop when the division ratio N of 20 is changed, it is set by the pulse of the reference frequency f _ref and reset by the pulse of the reproduction output frequency f _0. During this period, the reference clock counts up. The count value n corresponds to the output pulse position of the frequency divider 30 corresponding to the division ratio before the change, which is equivalent to the phase difference between the reference frequency f _ref and the reproduction output frequency f _0. The counter 40 stores the count value n in the memory 50. On the other hand, when the frequency division ratio N is changed, the count value n stored in the memory 50 is counted down according to the reference clock after the pulse of the reference frequency _fref is input, and at the timing when the count value becomes zero. It is configured to generate a pulse.

A switch S is provided between the frequency divider 30 and the flip-flop 12, and a movable contact of the switch S is in contact with the terminal a when forming a phase locked loop. On the other hand, when changing the frequency division ratio N, the movable contact of the switch S is moved to the terminal b before the pulse is output from the counter 40, and the pulse from the counter 40 is output to the flip-flop 12. It is configured to be.

 Next, the operation will be described.

First, it will be shown that the phase difference φ is immediately obtained by the sample-and-hold type phase comparator 10. Digital phase comparator
If, for example, a JK flip-flop 12 is used as 10, this operation is as shown in FIG. Here, assuming that T _φ is the time difference between the input phase and the output phase, the phase difference φ is obtained by averaging in the cycle of the input frequency. Given by If T _ref is constant, as in a frequency synthesizer, Next, obtained by the time integration, where theta to "1" when _{a ref} is input, if "0" when the theta ₀ came, and the integration time of "1", when "0" The output of the integrator 14 may be held by the hold circuit 16 and the integrator may be reset. Therefore, it can be understood that the output of the hold circuit 16 is proportional to the phase difference φ, and φ can be obtained at high speed every cycle as shown in FIG.

Therefore, it was found that the phase difference φ can be obtained at high speed without using a low-pass filter. Thus, it can be seen that the primary PLL is provided when the switch S is set to the a side.

Next, how to create and give the initial value φ (0) will be described. First, since _Tref is constant, a circuit for measuring the time difference _Tφ is constituted by the counter 40 as shown in FIG. Then, the hopping frequency is slowly switched to create a stationary phase difference, and the time difference _Tφ is measured by counting up with the counter 40, and this is stored in the memory 50 as the count value n. Then, given the way the initial value, reads out the count value n (T _φ) from memory 50, the third by counting down the counter 40 as shown in FIG, generates a pulse with only a time difference theta _ref and T _phi And set the switch to the b side and JK
Give to flip-flop 12. Thereafter, the switch S is set to the "a" side, and at the same time, the frequency dividing ratio N is preset to the dividing period 30 and returned to the normal PLL. Note that T _φ is used as an initial value in order to correspond to the temperature drift of the VCO 20, etc., and is compared with the time difference T _φ in the JK flip-flop 12 to update its value, and stored in the memory 50 before the next hopping. Keep it. There is no problem if the cycle of hopping to the same frequency is shorter than the temperature characteristic of the parameter of the VCO.

It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention.

For example, the present invention can be applied to a phase-locked loop using a first-order PLL for the fastest hopping, but can be applied to a phase-locked loop using a second-order PLL or the like.
Higher speed than before can be realized. The first-order PLL for realizing the first-order delay circuit is not limited to the one configured by the flip-flop 12, the integrator 14, and the sample-and-hold circuit 16 as in the above embodiment. Various primary PLLs that can detect a phase difference at high speed can be adopted.

Further, in the above embodiment, the phase difference detecting means and the pulse generating means are shared by the counter 40, but these may be constituted by separate circuits.

In the above-described embodiment, the initial value is measured from the information of the phase locked loop.
Can be given an initial value from outside.

[Effects of the Invention] As described above, according to the present invention, a value at which the phase locked loop should settle, that is, a phase difference corresponding to the hopping frequency is stored as an initial value, and this is set as an initial value. High-speed hopping that can respond within the cycle of the reference frequency is possible. In particular, by employing a first-order PLL capable of achieving a first-order delay circuit, only one initial value is required at the time of frequency hopping, so that higher-speed hopping can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency synthesizer to which the present invention is applied, FIG. 2 is an operation timing chart of the sample-hold type phase comparator shown in FIG. 1, and FIG. 3 is an initial timing chart of the counter shown in FIG. FIG. 4 is a timing chart for explaining a value measuring operation and a pulse generating operation based on the initial value. FIG. 4 is a block diagram of a conventional frequency synthesizer employing a low-pass filter. 10: sample-and-hold phase comparator, 12: JK flip-flop, 14: integration, 16: sample-and-hold circuit, 20: VCO, 30: frequency divider, 40: phase difference detection means, Pulse generating means (counter), 50 ... Memory.

Claims (3)

(57) [Claims] A frequency divider is provided in a phase locked loop, and when a frequency division ratio for the frequency divider is changed to switch an output frequency, a frequency divider corresponding to the frequency division ratio before the change is used in advance. An output pulse position is stored, and a pulse corresponding to the stored output pulse position is input to the phase comparator of the phase locked loop as an initial value of the loop, and the loop after the division ratio change is in a steady state. A frequency switching method for a frequency synthesizer, characterized in that the response time up to the point is shortened. 2. A frequency synthesizer in which a frequency divider is provided in a phase locked loop and an output frequency is switched according to a frequency division ratio set in the frequency divider, wherein a reproduction output obtained by dividing the output frequency by the frequency divider is provided. Phase difference detecting means for detecting a phase difference between a frequency and a reference frequency, a memory for storing the phase difference, and a phase difference stored in the memory with respect to the reference frequency when changing a frequency division ratio. And a pulse generating means for generating a pulse having the same and outputting the generated pulse to a phase comparator of the phase locked loop. 3. The method according to claim 2, wherein the phase difference detecting means and the pulse generating means store a value obtained by counting up a reference clock by a time corresponding to the phase difference in the memory, and store the value in the memory. A frequency synthesizer that also doubles as a counter that counts down the counted value and outputs the pulse when the count value becomes zero.