JP2883750B2 - Digital communication network with infinite channel expandability. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to digital communication networks and methods and apparatus for expanding networks without interrupting service.

Known digital communication network architectures limit unlimited channel spreading in a daisy-chain fashion and do not allow the network to extend to an infinite number of channels while retaining non-blocking conditions.

In particular, in known large networks, the probability of blocking increases as the number of channels increases. Blocking occurs when one node in the system is blocked from communicating with other nodes in the system that are not busy or with itself. The timing of the other networks is fixed, while the spatial stage (spac
This stage arises because the addition of e stages) adds an additional time delay.

Another problem with known networks is that they require two or more different printed circuit boards or modules to implement the network and expansion elements.

Another disadvantage of known digital networks is that they do not easily provide line expansion.

[0006]

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a digital communication network which overcomes the above problems and disadvantages of known networks, and in particular, the infinite non-blocking channel expandability of the online channel expandability. To provide a TST type digital communication network having the following.

In particular, it is an object to provide a digital communication network that provides time delay compensation in order to allow for expansion. In particular, said network comprises a first timestage consisting of a switching network having a number of input channels and a number of other output channels, and a number of input channels equal to the number of input channels of said first time stage. A second time stage comprising a switching network having a plurality of output channels;
A spatial switching matrix having a predetermined number of spatial stages interconnected to the input channels of the time stages, and a time delay introduced by said predetermined number of spatial stages of the spatial switching matrix between the first and second time stages. A device for providing a predetermined amount of compensation. Specifically, the first and second time stages are composed of time slot switches, and the spatial stages are composed of switching matrices.

In a preferred embodiment, at least one of the first and second time stages has a normal information memory, and the time delay compensator includes a back information memory for duplicating data storage by the normal information memory; A device for selectively time-shifting the data stored in the back information memory relative to the normal information memory by an amount to compensate for the delay. The number of output channels in the first time stage is no less than one less than twice the number of input channels, ensuring that the network is non-blocking.

Another object of the present invention is to provide an apparatus for storing communication data in a first memory, an apparatus for storing communication data identical to data stored in a first memory in a second memory,
A device which selectively uses one of the memory and the second memory as the normal information memory, and uses the other memory as the back information memory for storing the same data as that stored in the normal information memory. To provide a communication network.

Therefore, the communication data is temporarily stored in the first memory, the communication data is temporarily stored in the second memory, and a selected one of the first and second memories is turned off. Operating at least one of an input time stage and an output time stage for communication via the other of the first and second memories.
Interconnecting the three additional spatial stages, and selecting one of the first and second memories for a selected one of the memories with the network turned off to compensate for the delay caused by the additional spatial stage. An input time stage including the step of introducing a predetermined time shift to the data in the other and shifting the operation of the network from the selected one of the first and second memories to the other of the memories having a time delay requiring compensation. It is an object of the present invention to provide a method for extending a digital communication network having a spatial stage with a predetermined number of nodes interconnected between a stage and an output time stage.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a first type digital communication network 10 of the present invention is inserted between a first or input time stage 12 and a second or output time stage 14 therebetween. It is shown to have at least one spatial step. This architecture is referred to herein as TSnT
Cited as a network, where n equals the number of one or more spatial stages. In the case of the digital communication network 10 of FIG.
A SoT architecture is illustrated, where there is one or more voids, ie, one spatial stage. Associated with each spatial stage is a plurality of separate terminals or nodes (not shown), each of which is one for outgoing communication to provide full-duplex or two-way communication.
It requires a time slot or communication channel and one time slot or communication channel for inward communication.

In one aspect of the present invention, network 10 has inherent non-blocking characteristics. This is accomplished by providing one or more input channels, ie, input ports (ie, number of outputs ≧ 2 × number of inputs−1), at the input time stage. In the case of the input stage 12 of FIG. 1, the input stage 12 comprises four conventional configurable time slot switches.
time slot interchange, ie, defined by the CTSI circuits 12A, 12B, 12C, 12D, each of which has four input ports (T1I-
1 to T1I-4) and eight output ports (T1O-1 to T1O-8). The input signal of each input port (T1I-1 to T1I-4) is duplicated on the output pair (T1O-1 to T1O-8).

[0013] These outputs are coupled to an equal number of inputs of a space-time stage 16 which comprises eight conventional switching matrices.
x), i.e., SM16-1 to 16-8, each of which has four input ports (T1O-1 to T1O-8) respectively connected to different output ports (T1O-1 to T1O-8) of the CTSI circuits (12A to 12D). (SID from SIA).

Each of the eight switching matrices 16-1 to 16-8 has four outputs (SO-A to SO-
D), each of which has four associated second or output configurable time slot exchanges or CTSIs (14A to 1).
4B) is related to one of the eight inputs (T2I-1 to T2I-8). Output time slot exchange (1
4A-14B) has eight inputs (T2I-1 to T2I
-8) and four outputs (T2O-1 to T2O-4) except that the input CTSI (1
2A-12B). These output ports (T
20-1 to T2O-4) are input ports (T1I-1 to T1I-4) of the input CTSI 12A to 12D.
Or the input of the input CTSI (from T2I-1 to T2
1-4) is selectively coupled to an input of another network having an output coupled to one of the other networks.

Advantageously, the CTSI (14A-14
D) each input bus (T2I-1 to T2I-8) is connected to the other input bus (T2I-1 to T2I-8) (not shown).
Or, it is combined with the back input bus. This arrangement guarantees the non-blocking properties of the network.

3K port CTS as basic assembly block
Using I (12A-12D, 14A-14D), a set of eight CTSIs (12A-12D, 14A-14D) and eight SMs (16-1 to 16-8) has 12K ports.
Forming system. This TSoT architecture of the network 10 allows the number of ports to be extended to a 48K port network, which increases by 400% without the need for additional spatial stages 16.

However, referring to FIG. 2, the number of ports is advantageously expandable by daisy-chain expansion of the space stage 16 without having to change the timing. 8 SMs in the space stage 16 (16-1 to 16-8)
Each of the eight outputs (SO-A to SO-B) of FIG. 4 is driven by four trislatable elements 20 as shown schematically by fanout 17 in FIG. Related to the same fanout. This enables the four blocks 16A, 16B, 16C, 16D of the selected size to be connected to each other in a daisy-chain manner. Such blocks are 3K (small block), 12K (block),
48K (large block), 192K (large block), 7
68K (ultrablock), even larger sizes are possible. For the extension from the 12K block to the 24K block, the header B of the block 16A is changed to the space stage block 16B.
Cable to block header A. Cable up header B of block 16B is cabled to header A of block 16C to obtain an extension from 36K to 48K. 400% of this TSoT architecture
Is limited only by the considerable delay introduced by the high Z state of the tristable element 20. This factor can be significantly increased when using custom designed tristable elements with lower output capacitance than those currently available.

Referring to FIG. 3, there is illustrated the basic switching functions within the TSSoT network 10 of FIG. In the first time stage, the bandwidth of each input bus is doubled to provide non-blocking characteristics. Therefore, four input buses (T1I-1 to T1I-4)
Produces eight output buses (T1O-1 to T1O-8).
This is shown diagrammatically by the movement of data sample "A" in the vertical direction of arrow 21 (up or down) at the output of the first time stage 12 and the input of the spatial stage 16. Also, as shown in FIG. 3, at the output of the spatial stage and the input to the second time stage 14, the movement of the sample in the horizontal direction of arrow 23 (left or right), as shown schematically, Sample "A" is switched to a different time slot on the output bus by changing phase and position. Finally, the second time stage 14
Thus, the sample "A" is horizontally switched to its instruction output.

Two-dimensional x, y for assembling a database
If one uses the concept of a rectangular coordinate system, the schematic representation of these two time and space switchings is useful because the path search algorithm for controlling the switching in this TSnT architecture can be greatly simplified.
The switching of data samples is related to the x-coordinate, and the switching of data samples in space is related to the y-coordinate. This scheme is very similar to the one used for bit map system databases. Because all high-level languages include a two-dimensional array structure, producing this type of control software is straightforward.

Another important feature of the present invention is that it allows for expansion by additional spatial steps. The extension from 48K to 96K requires two additional spatial stages 22, 24 to create the TSnT configuration shown in FIG. In such a case, the CTSI back information memory in output time stage 14 is being used to accept the data transmitted by the spatial stage. The back information memory usually contains exactly the same data as the information memory. However, its output pointer points to the na value, while the pointer of the normal information memory points to the n value. The n value represents the current time slot and the a value is the additional space stage 2
2, 24 represents the time delay. The timing diagram of FIG. 5 illustrates the delay required for the back information memory output pointer to match the delay due to the additional spatial stages 22, 24 of FIG.

The back fanout of the first time stage 12 is sent to the first spatial stage 16, which is 4 times to allow for a four-fold expansion.
With a fan-out of One of the fan-outs of the second spatial stage 22 is sent to the third spatial stage 24. Space step 24
Receives this data and converts it to the CTS of the second time stage 14.
Send to I back information memory SIM. Once the CTSI receives data on its SIM, the existing large block (4
8K) The CTSI can switch a listen bus, which is an input for receiving input information, to the SIM side. From 48K to 192K, all CTSIs in the second time stage 14 use the SIM as operating information memory. Normally the information memory is held in a standby state and can be used as a spare to increase the fault tolerance of the system.

Upon powering up the new device, tristable element 20 receives a control word that places it in a high impedance state. It has been verified that it is desirable to reach this high impedance state before connecting to existing equipment, otherwise the connection will impair the flow of data within the network.

[0023] Advantageously, this feature allows for line extension processing that is lacking in known digital communication networks.
A method of performing a shift operation is performed by selectively changing the state of a tristable latch interconnected to the first and second memories. In the case of the TSnT architecture applied to set up a communication network in a multiprocessing environment, each processor is assigned a communication port number. Because the TSnT network 10 is non-blocking, any processor in this architecture can communicate with other processors in the network at any time with virtually no overload. Online expansion capabilities allow new equipment to be installed without disturbing tasks running in the network.

In the past, the use of hidden information memories has been limited to the storage of duplicate data to provide non-blocking characteristics in high performance networks. Conversely, the use of hidden information memory in the TSnT digital communication network 10 is a clear departure from this traditional role. This is because it is used to resynchronize the storage of the data. This resynchronization compensates for the extra delay introduced by the extended spatial matrix such as stages 22, 24 in FIG.

Referring to FIG. 6A, a preferred implementation of SIM control is illustrated. The SIM 32 has an independent counter 26
To provide a continuous address during the write cycle. This counter 26 has a 2: 1 multiplexer 2
4 and a programmable preload count from a control register that compensates for the delay of data through the additional space matrices 22, 24 of FIG. 4 by changing the write address passed to the SIM data address 32 via the latch 30. Receive.

According to another aspect of the invention, the back information memory is used as a standby memory, which normally replaces the failure of the information memory. As mentioned above, the back and normal information memories alternate roles during each extension, so that from time to time the normal information memory acts as a backup for the SIM 32.

Extensions beyond the 192K dimension require five spatial stages and are therefore referred to as TS4T networks. In such cases, an information memory is usually used to compensate for the additional spatial stage. In general, the table of FIG. 6B illustrates the different roles played by the normal and back information memories for different levels of extension.

For example, the CTSIs 12A and 14A have two possible configurations. Input time stage 12 of network 10 of FIG.
As shown in detail in FIG. 7, the CTSI is 1: 2 TS
II. In such a case, the driver link 33 between bus A and bus B is turned on, so that buses A and B have the same data, ie both outputs are turned on or energized. In the output time stage 14 of the network, the CTSI is configured as 2: 1 TSI. In such a case, the driver link between buses A and B is off. Buses A and B carry different data and only one of the two outputs is used.

The driver for each bus is divided into two equal parts. One drives the normal information memory (IM) 34 and the other drives the back information memory (SIM) 32. The normal information memory array receives data from the normal fanout 17 of FIG. 1 of the space stage 16 and the SIM memory array 32 receives data from the back fanout of the spatial matrix. The selection between IM 34 and SIM 32 is made by tristable latch 38. These latches 38 always latch to new data. However, only one of the two latches 38A, 38B associated with IM 34 and SIM 32, respectively, is activated at a particular time. 2: 1 multiplexer, ie, max (mu)
xes) 40 is used in conjunction with driver link 33 between buses A and B to reconfigure CTSI I / O.
In the 1: 2 configuration, the 2: 1 max 40 that generates the output OBUSNA is set to always select the A side, and the 2: 1 max 42 that generates the output OBUSNB is set to always select the B side. In this 1: 2 configuration,
The IBUSNB input is open and all eight output buses are used.

In the 2: 1 configuration, since the driver link 33 between the buses A and B is off, all eight input buses are connected. However, since the 2: 1 Max 42 that generates OBUSNB is turned off, only transmissions from Max 40 are output to the four OBUSNA ports. 2: 1 Max 40 that generates OBUSNA is OB
A or B side is dynamically selected to transmit and output to the USNA port.

As shown in FIG. 8, each of the space stages 16 has four stages.
Preferably, it is defined by a plurality of 4.times.4 spatial matrices having a number of input bus outputs (SIA to SID) and four output buses. 4 output buses (SO-A to S
O-D) each have four normal fanouts and four back fanouts transmitting the same data. All fan-outs are tristable and allow for daisy-chain expansion. SM also functions as a 1: 4 buffer. In the case shown in FIG. 8, each 4: 1 max is set to select a different input bus, and the fanout is always one.

While a detailed description of the preferred embodiment of the present invention has been given, it will be appreciated that many modifications may be made without departing from the spirit of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing objects, features and advantages will be described in detail, and other objects, features and advantages will become apparent from the detailed description of the preferred embodiments which is given with reference to the several drawings. .

FIG. 1 is a block diagram of a preferred embodiment of the TSnT digital communication network of the present invention for the special case n = 0.

FIG. 2 is a block diagram of a portion of the TSnT communication network of FIG. 1 for the special case of n = 0 with daisy-chain extension without introducing an extra time delay due to the spatial stage.

FIG. 3 is a schematic diagram of a basic switching procedure of the TSnT communication network of FIG. 1;

FIG. 4 is a block diagram of a preferred embodiment of the TSnT communication network of the present invention for the special case of n = 2 where fanout to other spatial stage blocks is provided for expansion without extra time delay; .

5 is a timing diagram illustrating the delay in the back information pointer of the CTSI of FIG. 4 to accommodate the delay through two extra spatial stages for the network of FIG. 1;

6A is a back information memory for the normal memory of FIG. 7,
That is, a functional block diagram of a preferred embodiment of a controller for time-shifting data in a SIM. B is n =
Normal information memory, ie IM and back information memory, ie SIM, for 1, 2, 3, 4 TSnT communication networks
3 is a table illustrating the shift function of FIG.

FIG. 7 and FIG. 4 with a 1: 2 input-to-output configuration
Configurable time slot switch, ie CTSI
The functional block diagram of a functional block.

FIG. 8 shows the spatial matrix of FIGS. 1 and 4, ie SM
Functional block diagram of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Digital communication network 12 1st time stage 14 2nd time stage 16,22,24 Space stage 20,38 Tristable element 32 Back memory 34 Normal memory

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04Q 11/04 H04Q 3/52

Claims (2)

(57) [Claims] 1. An input time stage consisting of a switching network, an output time stage consisting of a switching network, and a spatial stage consisting of a switching matrix having a predetermined number of nodes interconnecting the input time stage and the output time stage. A first time stage comprising a switching network having a predetermined number of input channels and another predetermined number of output channels, a predetermined number of input channels, and the first time stage. A second time stage comprising a switching network having a plurality of output channels equal to the number of input channels, and a predetermined number of switching matrices connecting the output channels of the first time stage to the input channels of the second time stage. A spatial switching matrix having the following spatial stages; and a spatial switching matrix between the first and second time stages. A timing delay compensator for providing a predetermined amount of compensation for the time delay of the data caused by the operation delay of the constant number of spatial stages, depending on the position of the data, wherein at least one of the predetermined number of spatial stages includes: A plurality of substantially identical spatial stage blocks; and means for interconnecting the spatial stage blocks in a daisy chain manner, wherein at least the second time stage has a first output indicative of a current time slot. A normal information memory having a pointer "n" and storing normal information; and a back information memory having a second output pointer "na" and storing back information.
Represents the amount of time delay caused by the added spatial stage, the amount of time delay being compensated by the time delay compensator when data storage resynchronization is performed, and the back information memory A TST type digital communication network used for synchronization, wherein the back information memory stores the same data as the normal information memory. 2. An input time stage comprising a switching network, an output time stage comprising a switching network, and a spatial stage comprising a switching matrix having a predetermined number of nodes interconnecting the input time stage and the output time stage. A first time stage comprising a switching network having a predetermined number of input channels and another predetermined number of output channels, a predetermined number of input channels, and the first time stage. A plurality of output channels equal to the number of input channels, a normal information memory for receiving data from a normal fan-out, a back information memory for receiving data from a back fan-out, and a normal information memory and a back information memory. A second time stage including means for outputting data from one of them, and an output channel of the first time stage to an input channel of the second time stage. A spatial switching matrix having a plurality of serially connected spatial stages comprising a switching matrix to be connected, each spatial stage including both a normal fan-out and a back fan-out transmitting the same data; and a first and a second time. A timing delay compensator for providing a predetermined amount of compensation for the time delay of the data caused by the operation delay of the plurality of spatial stages of the spatial switching matrix between the stages according to the position of the data; Normal information is stored with a first output pointer "n" indicating the current time slot, and the reverse information memory stores reverse information with a second output pointer "na". "Represents the amount of time delay caused by the added spatial stage, the amount of time delay being compensated by the time delay compensator when data storage resynchronization occurs. The back information memory is used for resynchronization of the data storage, the back information memory the information typically TST type digital communications network that is characterized by storing the same data as memory.