JP2878717B2 - Semiconductor device, semiconductor integrated circuit device - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device and a semiconductor integrated circuit device. It is used for a circuit suitable for processing.

(Prior Art) FIG. 15 shows a pattern layout of a conventional high-frequency differential amplifier corresponding to the first invention. FIG. 16 shows a circuit example including the peripheral portion.

In the above pattern and circuit, the emitters of the first transistor (Tr1) and the second transistor (Tr2) are connected in a differential manner in an envelope (not shown). That is, a local oscillation output is input to one of the two transistors (Tr1, Tr2), for example, the first transistor (Tr1) from the terminal 1001, which is a bonding pad, and its emitter 1111
And the emitter 1121 of the second transistor (Tr2) are connected to the collector 1133 of the third transistor (Tr3) together with the wiring 1141.
Are connected in common. The base 1122 of the second transistor is grounded at a high frequency from a terminal 1002 of the peripheral circuit shown in FIG. 16 by a capacitor. A high frequency signal is applied to the base 1132 of the third transistor through the peripheral circuit, and the base 1121 of the first transistor (Tr1) is applied.
Is supplied with an output from a local oscillator. Then, from the collector 1123 of the second transistor, a high frequency signal and a signal of a frequency difference between the local oscillator are output. In addition, the first and second
The collectors 1113 and 1123 of both transistors are connected to a power supply (Vcc) through a resistor, and the emitter 1131 of the third transistor is connected to a contact portion provided at a terminal 1005.
Due to 1151, the same potential as silicon substrate 1100 and a predetermined potential (normally ground).

A conventional differential amplifier circuit of a semiconductor device according to the second invention will be described.

The differential amplifier circuit shown in FIG. 17 is used for a high-frequency mixer or the like.
It is difficult to integrate, and conventionally, it was configured by combining discrete elements. For example, in a VHF band tuner of a television receiver, a transition frequency f _T = about 2 GHz, or
Bipolar transistors of about f _T = 4 GHz were often used in UHF tuners.

On the other hand, as the performance and miniaturization of devices such as TVs and VTRs have progressed, tuners have also been required to have higher performance and smaller size. Things are needed.

Seventeenth example of the related art example of the integrated circuit device according to the third invention.
This will be described with reference to FIGS.

In a general electric circuit, a circuit as shown in FIG. 18 is frequently used. As an example, there is a circuit as shown in FIG. 19. This circuit mixes an input signal f _S (200 MHz) with a signal f _L (260 MHz) from a local oscillator and outputs an output signal (60 MHz).
z) It has the function to take out. In the above circuit, the following is important.

(1) Since f _S and f _L is not preferable is a mutual interference,
In the case of each of the input terminals B1, B3 and FIG. 19, it is necessary to arrange the base terminal B1 of the first transistor (Tr1) and the base terminal B3 of the third transistor (Tr3) as far as possible.

(2) Since mutual interference between the input and output is not preferable, in the case of FIG. 19, the input and output terminals, the base terminal and the collector terminal of each transistor must be arranged as far as possible.

(3) At present, electronic devices tend to be downsized.
Even when a circuit as shown in the figure is sealed in one package, the size of the package needs to be very small.

FIG. 20 shows an example of an integrated circuit device in which the circuit shown in FIG. 18 is sealed in one package. In the integrated circuit device shown in the figure, two circuits shown in FIG. 18 are formed in one package. In the circuit shown in FIG. 20, inputs such as f _S to the terminal 5111, and enter the f _L to the terminal 5112, if to retrieve the output from the terminal 5113, the contents of the (1) (2) is satisfied Therefore, good characteristics can be obtained. Further, as can be seen from the figure, there is no portion where the wiring crosses, so that the manufacturing process is relatively easy. Further, since two circuits shown in FIG. 18 are formed, the pin arrangement is also rational.

(Problem to be Solved by the Invention) In the pattern layout shown in FIG. 15 corresponding to the first embodiment of the present invention, the terminal 1001 of the bonding pad to which the output from the local oscillator is applied is connected to the first transistor (Tr1). ) And a wiring 1143 from the terminal 1003 of the bonding pad to which the high-frequency signal is applied to the base 1132 of the third transistor (Tr3).
Between the terminal 1002 of the bonding pad, which is grounded in high frequency, and the base 112 of the second transistor (Tr2).
The wiring 1144 to 2 occupies only a part of the silicon substrate, and the first transistor (Tr1) and the third transistor (Tr
The high frequency separation between 3) is incomplete. For this reason,
It has been difficult to suppress unnecessary radiation and intermodulation caused by the output of the local oscillator entering the high-frequency signal line. In addition, since the output of the local oscillator cannot be increased due to the above problem, there is a serious problem that the conversion gain is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce unwanted radiation and intermodulation and increase conversion gain for a differential amplifier circuit formed on a silicon substrate.

In the circuit constituted by discrete elements in the prior art corresponding to the second invention, the occupied area is large, which has become a limiting factor in downsizing the device. In the case of a discrete configuration, since the wiring between the elements cannot be reduced to a certain level or less, there is a problem that the local oscillation high frequency to the mixer leaks to the antenna side and is radiated to the outside to interfere with other devices. I was

The prior art corresponding to the third invention does not sufficiently achieve the necessity of mounting an integrated circuit device on a circuit board at a high density in order to reduce the size of electronic devices, which is a recent trend. That is, the integrated circuit device shown in FIG.
It is advantageous when two circuits shown in FIG. 18 are used close to each other. However, when only one circuit is used as shown in FIG. 19 or when two circuits are used apart from each other, This is disadvantageous in terms of mounting area or wiring. Therefore, an integrated circuit device in which one circuit shown in FIG. 18 is sealed is also required.
When such an integrated circuit device is considered as an extension of the prior art shown in FIG. 20, it becomes as shown in FIGS. 21 and 22, but when it is used for an electric circuit shown in FIG. There is a problem as follows.

First, in the case of the integrated circuit device shown in FIG.
To f _S, enter the f _L terminal to the fourth terminal 5214, if retrieve output from the fifth terminal 5215, mentioned in the paragraph of the prior art (1)
Item (2) is satisfied, but the package is considerably large because four leads (5211 to 5214) are formed on one side of the package and two leads (5215, 5216) are formed on the other side.

Next, in the case of the integrated circuit device shown in FIG. 22, three leads are attached to opposing side surfaces of the package, so that the package can be considerably reduced in size.
However, f _L and f _S are respectively set to the first terminal 5311 and the second terminal 5312.
, The mutual interference of the respective signals becomes a problem because the respective leads are adjacent to each other. F _L , f _S
Is input from the fourth terminal 5314 and the second terminal 5312 (not shown), the input terminal (fourth terminal 5314) and the output terminal (fifth terminal 5315) are arranged adjacently. There is a problem that mutual interference between them becomes a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional technology, and has as its object to reduce the size of a semiconductor device and improve high-frequency electrical characteristics.

[Configuration of the invention]

(Means for Solving the Problems) In a semiconductor integrated circuit device according to a first invention, each of the emitters of a first transistor and a second transistor is connected in a differential manner in an envelope, and any one of these transistors is connected. A local oscillation output is input to a semiconductor integrated circuit device having a differential circuit element including a third transistor to which a collector is connected and a signal is input to a connection portion of each of the emitters. A wiring layer that is grounded in an external circuit between the transistor and a transistor to which a signal is input.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: first to third elements formed adjacently on a semiconductor substrate; first electrodes of the first and second elements; A metal layer for electrically connecting a third electrode of the first element, a first terminal connected to the second electrode of the first element and formed in a pad shape of metal for external connection, A second terminal for external connection arranged adjacent to the terminal and connected to a second electrode of the second element, and connected to a second electrode of the third element arranged adjacent to the second terminal A third terminal for external connection, a fourth terminal for external connection disposed adjacent to the third terminal and connected to a first electrode of the third element, and a third terminal for external connection. A fifth terminal for external connection arranged and connected to a third electrode of the second element, between the fifth terminal and the first terminal; Third placed first element
And a chip provided with a sixth terminal for external connection connected to the electrode.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device, comprising: a first to a third element formed adjacently on a semiconductor substrate;
The first electrodes of the element and the second element and the third electrode
A metal layer for electrically connecting a third electrode of the first element, a first terminal connected to the second electrode of the first element and formed in a pad shape of metal for external connection, A second terminal for external connection arranged adjacent to the terminal and connected to a second electrode of the second element, and connected to a second electrode of the third element arranged adjacent to the second terminal A third terminal for external connection, and the third terminal arranged next to the third terminal.
A fourth terminal for external connection connected to a first electrode of the element, and a fifth terminal for external connection disposed adjacent to the fourth terminal and connected to a third electrode of the second element And a third element of the first element disposed between the fifth terminal and the first terminal.
And a sixth terminal for external connection connected to the third electrode, and a conductive layer for connecting a second electrode of the second element to the second terminal is provided on the third terminal. Is formed on a part of the diffusion region constituting the third electrode of the element through an electric insulating layer.

(Operation) In the first invention, since the wiring layer grounded by an external circuit passes between the high-frequency signal line and the local oscillation line, mutual modulation of both signals and undesired transmission to the high-frequency signal line are prevented. Radiation is reduced. As a result, the output from the local oscillator can be increased, and the conversion gain can be increased.

The second invention relates to a bipolar transistor or a MOS transistor.
A circuit in which three FETs are combined is formed on a semiconductor substrate in a moss-nolithic manner, and by optimizing the arrangement of the electrodes, the mounting density can be improved. (Approximately 3.0 mm) and provide a high-performance differential amplification mixer element.

A third invention is, upon mounting the circuit of the high-frequency differential amplifier into a single package, the placement of the pin terminal which projects from opposite sides of the package to f _S to the third terminal, the f _L first
Input to the respective terminals, and output from the fourth terminal (f
i), the mutual interference between f _S and f _L and between the input and output is reduced, and an electric circuit having excellent high-frequency characteristics can be formed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

One embodiment of a circuit constituting a semiconductor device according to the first invention and a pattern layout thereof are shown in FIGS. 1 and 2. FIG. This semiconductor device has three npn transistors,
Or a third transistor (Tr1, Tr2, Tr3),
An emitter 1011 of the first transistor (Tr1), an emitter 1021 of the second transistor (Tr2), and a collector 1033 of the third transistor (Tr3) are connected to a wiring 1041, and a collector of the first transistor (Tr1). 1013 is the sixth
The collector 1023 of the second transistor (Tr2) is connected to the fourth bonding pad terminal 1004, and is connected to a power supply (Vcc) from a peripheral circuit through a resistor. The base 1012 of the first transistor (Tr1) is connected to the first bonding pad terminal 1001 by the wiring 1042, a local oscillation output from the outside is injected, and the base 1032 of the third transistor (Tr3) is connected to the wiring 1043. Is connected to the third bonding pad terminal 1003 to inject a high frequency signal from the outside. The base 1022 of the second transistor (Tr2) is a wiring 104
4 overlaps the part above the collector 1033 of the third transistor so as to overlap therewith, and passes between the third and first transistors (Tr3, Tr1) to be connected to the second bonding pad terminal 1002. The second bonding pad terminal 1002 is grounded at a high frequency by an external circuit. Emitter 1 of third transistor (Tr3)
031 is connected to the fifth bonding pad terminal 1005,
Further, the contact hole 1051 provided in the fifth bonding pad terminal 1005 is connected to the same potential as the silicon substrate 1100, and is set to the ground potential by an external circuit.

It is needless to say that the present invention is applicable even if the first to third transistors are MOS (Metal Oxide Semiconductor) FETs (field effect transistors).

The structure of the chip of the semiconductor device according to the present invention is changed to three transistors (Tr1, Tr1) as shown in FIG.
2, Tr3), three field effect transistors (FET-1, F-1
The present invention can also be applied to a device that performs differential amplification using ET-2, FET-3).

An embodiment of the second invention will be described below with reference to FIG. 4 to FIG.

FIG. 5 shows the arrangement of the bonding pads according to the first embodiment of the present invention corresponding to the circuit example of FIG. 4, and FIG. 6 shows the pattern of the surface metal layer. In the figure, the first transistor (Tr
1), the second transistor (Tr2), and the third transistor (Tr3) can be formed by a known bipolar integrated circuit manufacturing process, and have a fine pattern, a low-capacity structure, and a shallow junction to be suitable for high frequency. etc., so has achieved high f _T does not participate directly in the essence of the present invention will not be described in detail. The essence of the present invention lies in the layout of the device, particularly the arrangement of electrodes and bonding pads for external connection.

In the semiconductor substrate 4000 shown in FIG. 6, 4001 is a first transistor (Tr1) region, and 4002 is a second transistor (T1).
An r2) region 4003 is a third transistor (Tr3) region, and a base of the first transistor (Tr1) is led out by a metal wiring layer, and as shown in FIG.
A local oscillation high frequency (f _L ) is injected from a peripheral circuit (not shown) by being connected to the bonding pad B1 around the main surface. The base of a second transistor (Tr2) is connected to the bonding pad B2 adjacent to the bonding pad B1, and a high-frequency signal (f _S ) is injected from a peripheral circuit (not shown). Further, the bonding pad
The base of the third transistor (Tr3) is connected to a bonding pad B3 adjacent to B2, and is arranged along one side of the main surface of the semiconductor substrate together with the bonding pads B1 and B2. Next, the emitter of the third transistor (Tr3) is connected to the bonding pad E3 disposed along the one side adjacent to the one side of the semiconductor substrate, and the power supply is grounded in the peripheral circuit. Further, bonding pads C2 and C1 are arranged along the side adjacent to the adjacent side, and the collector of the second transistor (Tr2) is connected to the bonding pad C2 to be output (fi) to a peripheral circuit, The collector of the first transistor (Tr1) is lead-out connected to the bonding pad C1, and is grounded in a peripheral circuit.

FIG. 7 shows that the first to third transistors (Tr1 to Tr3) in the first embodiment are replaced by MOS FETs (MOST1, MOST1).
2 shows a circuit example of the second embodiment composed of MOST3). The names of the electrodes can be formed in the same manner as in the above embodiment by replacing the emitter with the source (S), the base with the gate (G), and the collector with the drain (D).

An embodiment of the third invention will be described below with reference to FIGS. 8 and 9.

As shown in FIG. 8, the chip has a first element (Tr1), a second element (Tr2), and a third element (Tr3) formed adjacently on a semiconductor substrate. And the first
The emitter electrodes of the element (Tr1) and the second element (Tr2) are connected to each other, and the collector electrode of the third element (Tr3) is further connected to this by a metal layer 5010. Next, the first
A first terminal 5001 which is connected to a base electrode of the element (Tr1) and is formed of metal in a pad shape for external connection;
A second terminal for external connection 5002 arranged next to the terminal 5001 and connected to the base electrode of the second element (Tr2); and a third element (Tr) arranged next to the second terminal 5002
Third terminal 500 for external connection connected to the base electrode of 3)
3, a fourth terminal 5004 disposed adjacent to the third terminal 5003 and connected to an emitter electrode of the third element (Tr3) for external connection, and a fourth terminal 5004 disposed adjacent to the fourth terminal 5004. A fifth terminal 5005 for external connection connected to the collector electrode of the second element (Tr2); the fifth terminal 5005 and the first terminal 50;
01 and a sixth terminal 5006 for external connection connected to the collector electrode of the first element (Tr1). Particularly, the base electrode of the second element (Tr2) A conductive layer 5012 connected to the second terminal 5002 is formed on a part of a diffusion region 5043 constituting a collector electrode of the third element (Tr3) via an electric insulating layer 5050 as shown in FIG. Have been.

Hereinafter, a method of manufacturing a main part when an NPN bipolar transistor is used will be described with reference to FIG.

An n ⁺ -type buried layer 50 is formed on the upper surface of the low-concentration p-type silicon substrate 5040.
After forming 21,5041, a p-type epitaxial layer 5020 is formed. Next, n-type impurities are selectively diffused to form n-type collector regions 5022, 5032, 5042 and n ⁺ -type collector region 502.
3,5033,5043 are formed. Next, p-type impurities are selectively diffused to form base regions 5024, 5034, 5044, and polycrystalline silicon layers 5025a, 5035a, 5050 each containing an n-type impurity.
Selective diffusion is performed from 45a (5035a is not shown in FIG. 12) to form n ⁺ -type emitter regions 5025, 5035, 5045 (5035 is not shown in FIG. 12). Next, the interlayer insulating film 5050
To form a first element (Tr) as shown in FIG.
1) For the third to third elements (Tr3), contact holes 5025a, 5024a, 5022a, 5035a, 5034a, 5054a, 5024a, 5022a, 5022a, for exposing a part of each region to each emitter region base region and collector region.
After forming 5032a, 5045a, 5044a, 5042a, wiring electrodes 5011, 5012, 5013, 5014, 5015, 5016 are provided with conductive members,
The electrodes are connected to the terminals 5001,5002,5003,5004,5005,5006 to attain lead-out, and a chip of a semiconductor integrated circuit device is formed.

Next, details of the manufacturing method will be described with reference to FIG.

First, a semiconductor substrate containing about 8 × 10 ¹⁴ cm ^-3 boron
Prepare 5040. An N ⁺ -type buried layer 502 selectively containing about 5 × 10 ¹⁹ cm ⁻³ of antimony is formed on the upper surface of the semiconductor substrate 5040.
After forming 1,5031,5041 (5031 is not shown in FIG. 9), an epitaxial layer 5020 containing about 2 × 10 ¹⁵ cm ⁻³ of boron is grown. Next, phosphorus was implanted by ion implantation at an acceleration voltage of 70 KeV, a dose of 3.0 × 10 ¹² cm ⁻³ , an acceleration voltage of 40 KeV, and a dose of 2 × 10 ¹⁵ cm ⁻³ , and then 11
The n-type collector regions 5022, 5032, 5042 are diffused in an N ₂ atmosphere at 50 ° C. for about 12 hours (5032 is not shown in FIG. 9).
And n ⁺ -type collector regions 5023, 5033, 5043 (5033 is not shown in FIG. 9), respectively. Next, remove the oxide film
Formed about 1000Å, acceleration voltage 40 KeV, dose amount 3.0 × 10 ¹⁴
After ion implantation of boron at cm ^-2 , in a nitrogen atmosphere 11
Anneal for about 50 minutes at 00 ° C, base area 5024, 5034, 50
44 (5034 is not shown in FIG. 9). Next, emitter regions 5025, 5035, and 5045 are formed by an arsenic-doped polysilicon layer. In FIG. 10 and FIG. 11, this polycrystalline silicon layer is also formed on a part of the n ⁺ type collector regions 5023, 5033, 5043, in order to reduce the contact resistance with the conductive member. It is. next,
After being deposited 8000Å thick by CVD (chemical vapor deposition) method, or the like, in a nitrogen atmosphere, subjected to a suitable time annealing at 1100 ° C., and controls the DC current amplification factor h _FE. Next, a contact hole for leading each element region in the wiring layer is provided in each region, and the wiring electrode layers 5010, 5011, 5012, 5013, and 501 are provided.
4,5015,5016 are made of aluminum and are connected to the terminals 5001,5002,5003,5004,5005,5006 by these.

Although the first to third elements have been described as being bipolar transistors in the embodiment, the MOS (metal oxide semiconductor device) FET (field effect transistor) also has emitter, base and collector electrodes. It goes without saying that the present invention can be applied to the source, gate, and drain electrodes. Further, the present invention can be applied to a case where a resistance element and a capacitance element are included.

〔The invention's effect〕

According to the first aspect, the wiring layer grounded by the external circuit passes between the high-frequency signal line and the local oscillation line.
Intermodulation of a signal and undesired radiation to a high-frequency signal line can be reduced. As a result, the output from the local oscillator can be increased, and there is a remarkable advantage that the conversion gain can be increased.

In the semiconductor device according to the second invention, first, the chip size can be reduced to about 0.6 mm square, and FIG.
By mounting and bonding to a frame as shown in the figure, the size of the molded body can be enclosed in an ultra-small surface mount type envelope of about 1.5 mm × 3 mm, which is smaller than that of a discrete configuration In both cases, three times higher density mounting is possible. Next, the superiority when the element of this semiconductor device is used in an actual application example will be described. FIG. 19 is a circuit example when the integrated device of the present invention is applied to a television tuner. The frequency f _S is provided at the base of the third transistor (Tr3).
Is input. The first transistor (Tr
The local oscillation high frequency of the frequency f _L is input to the base of 1). The emitter of the third transistor (Tr3) is connected to the power supply ground, and the collector of the first transistor (Tr1) and the base of the second transistor (Tr2) are grounded in terms of high frequency. A resistor for applying an optimum DC bias to the first transistor (Tr1), the second transistor (Tr2), and the third transistor (Tr3), and a capacitor and an inductance for controlling a high-frequency signal are appropriately added. However, a detailed description is omitted because it does not relate to the essence of the present invention. F _L from the collector of the second transistor (Tr2)
The difference is output frequencies and sum necessary components of the intermediate frequency fi of which the f _S is taken as. In this case round inclusive to f _S side of f _L, it is necessary to reduce as much as possible wraparound to f _S side of the fi. In the present invention, the bonding pads bonding pads of the ground terminal between the bonding pads (B1) to f _S is the bonding pads (B3) and f _L enters enters (B2), also to the bonding pad (B3) fi is output (C
The bonding pad (E3) of the ground terminal is inserted between 2), and all signals are grounded in the middle. Further, the frame at the time of assembling is also similarly shielded, and the arrangement of the bonding pads of the chip is easily compatible with this frame, so that an optimal assembly structure can be obtained.

The first transistor (Tr1) and the second transistor (T
r2) and the third transistor (Tr3) have the same effect when the MOS transistor is composed of both. However, the MOS FET has a lower distortion characteristic because the input-output characteristic is close to the ideal square characteristic. You can get it. When the third transistor is a MOS FET (MOST3) and the first transistor (Tr1) and the second transistor (Tr2) are bipolar transistors, low distortion of the MOSFET and high gm characteristics of the bipolar transistor are obtained. At the same time, a higher performance mixer can be realized.

As described above, by using the integrated device of the semiconductor device according to the present invention, it is possible to achieve a mounting density three times or more as compared with the conventional circuit, and also to reduce an interference wave due to unnecessary radiation. It greatly contributes to miniaturization and high performance of devices such as televisions and videos.

The present invention is not limited to the mixer circuit, but can be used as a general differential amplifier, and can be applied to an oscillator and many other applications.

The semiconductor integrated circuit device according to the third invention has the following effects.

First, when the circuit shown in FIG. 11 is mounted on one package, the lead arrangement as shown in FIG. 12 becomes possible.
In the application circuit example shown in Figure 13, the f _S type third terminal, the f _L from the first terminal, if retrieve output from the fourth terminal,
Mutual interference between f _S and f _{L and} between input and output can be reduced, and an electric circuit with good high-frequency characteristics can be formed.

Next, since a complicated process such as multilayer wiring is not required, and the wiring does not need to be extended for a long time, the chip size can be reduced. As an example, when a circuit is composed of three bipolar transistors as shown in FIG. 10, the chip size can be 0.54 mm × 0.54 mm.
When mounted on a lead frame as shown in Fig. 14 to form an integrated circuit device, the size of the envelope 5060 is 2.9 mm x 1.6 mm
Degree. This is the same size as a conventional microminiature surface mounting device, and is suitable for high-density surface mounting.

In the above description, the case of an integrated circuit device formed of only bipolar transistors has been described. However, the present invention may be applied to a case where the integrated circuit device is formed of a MOSFET, or a case where a resistance element and a capacitance element are included.

[Brief description of the drawings]

1 (a) and 1 (b) relate to an embodiment according to the first invention. FIG. 1 (a) is a circuit diagram of a semiconductor device according to the first invention, and FIG. 1 (b) is a diagram of FIG. FIGS. 2A and 2B show a pattern layout of FIG. 2A and FIG. 3A and FIG. 3B show a configuration of a chip of a semiconductor device, FIG. 4 shows an embodiment according to the second invention, and FIG. FIG. 5 is a top view showing the arrangement of bonding pads, FIG. 6 is a top view showing a pattern of a surface metal layer, FIG. 7 is a structural circuit diagram of the semiconductor device of the second embodiment, FIG. 8 and 9 show FIG.
9 is a top view showing a pattern of a surface metal layer of a semiconductor integrated circuit device, FIG. 9 is a cross-sectional view for explaining a method of manufacturing the semiconductor integrated circuit device,
FIG. 10 is a top view for explaining the correlation between the configuration and the effect of the embodiment according to the second invention, and FIGS.
FIG. 4 is a diagram for explaining the correlation between the configuration of the present invention and the effect.
FIG. 11 is a circuit diagram, FIG. 12 is a top view showing a lead arrangement, and FIG.
FIG. 14 is an application circuit diagram, FIG. 14 is a top view of an envelope, FIGS. 15 to 22 are diagrams for explaining a conventional example, and FIG.
15 is a top view showing a pattern layout of a high-frequency differential amplifier, FIG. 16 is a circuit diagram including a peripheral portion, and FIGS. 17 to 22 are related to the prior art of the third invention. 17 to 19 are circuit diagrams, and FIGS. 20 to 22 are diagrams each showing the configuration inside the envelope. Tr1, Tr2, Tr3 ... first to third transistors, MOST1, MOST2, MOST3 ... first to third MOS FETs, fl ... local oscillation output, fs ... high frequency signal, fi ... output signal.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Endo 1 Komagi Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (72) Inventor Takahiro Ito 1 Kochi-Mukotoshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Tamagawa Plant (72) Inventor Shoichi Tanzen 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center (72) Inventor Noboru Tada Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 580 No. 1 Toshiba Corporation Semiconductor System Technology Center (56) References JP-A-63-202948 (JP, A) JP-A-62-283636 (JP, A) JP-A-61-234055 (JP, A) (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/06 H01L 21/82

Claims (3)

(57) [Claims] An emitter or a source of each of a first transistor and a second transistor is connected in a differential manner in an envelope, a local oscillation output is inputted to one of these transistors, and an emitter of each of the emitters is connected to one of the transistors. In a semiconductor integrated circuit device having a differential circuit element including a third transistor to which a collector or a drain is connected to a connection portion and to which a signal is input, a transistor to which a local oscillation output is input and a transistor to which a signal is input And a wiring layer grounded in an external circuit. 2. A semiconductor device comprising: first to third elements formed adjacently on a semiconductor substrate; first electrodes of the first and second elements; and a third electrode of the third element. A metal layer electrically connecting the first and second electrodes, a first terminal connected to the second electrode of the first element and formed in a pad shape with a metal for external connection, and disposed next to the first terminal A second terminal for external connection connected to a second electrode of the second element, and an external connection disposed next to the second element and connected to a second electrode of the third element. A third terminal, a fourth terminal for external connection disposed adjacent to the third terminal and connected to a first electrode of the third element, and a third terminal disposed next to the fourth terminal. A fifth terminal for external connection connected to the third electrode of the second element; and a fifth terminal of the first element disposed between the fifth terminal and the first terminal. The semiconductor device having a chip comprising comprises a sixth terminal for connection to an external connection to the third electrode. 3. The first to third elements formed adjacently on a semiconductor substrate; first electrodes of the first and second elements; and third electrodes of the third element. A metal layer electrically connecting the first and second electrodes, a first terminal connected to the second electrode of the first element and formed in a pad shape with a metal for external connection, and disposed next to the first terminal A second terminal for external connection connected to a second electrode of the second element, and an external connection disposed next to the second element and connected to a second electrode of the third element. A third terminal, a fourth terminal for external connection disposed adjacent to the third terminal and connected to a first electrode of the third element, and a third terminal disposed next to the fourth terminal. A fifth terminal for external connection connected to the third electrode of the second element; and a fifth terminal of the first element disposed between the fifth terminal and the first terminal. A sixth terminal for external connection connected to the third electrode, and a conductive layer for connecting a second electrode of the second element to the second terminal. A semiconductor integrated circuit device, wherein a part of a diffusion region forming a third electrode of the third element is formed via an electric insulating layer.