JP2877808B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a memory for detecting a power supply voltage drop. [Prior Art] In recent years, with the development of electronic technology, a voice synthesizer has been used in automobiles and the like. These speech synthesizers are mainly used to alert the driver.
Here, if the power supply voltage drops and the voice synthesizer does not operate normally, the driver cannot be notified even if the driver is in danger. In order to avoid this, a means for informing the driver of a drop in the power supply voltage is required prior to any warning. Conventionally, in order to notify the driver of a power supply voltage drop with this type of voice synthesizer, the power supply voltage drop is detected by an operational amplifier or the like,
The arithmetic control circuit generates a voltage drop notification signal (hereinafter, referred to as an ALM signal). That is, the warning sound program is coded and arranged at the address of the ROM which is started by the ALM signal. FIG. 4 shows a block diagram of a conventional speech synthesizer. In FIG. 4, reference numeral 1 denotes a battery used as a power supply of the speech synthesizer, and its power supply voltage is _VBAT . Reference _numeral 2 denotes a battery for supplying a reference voltage for detecting a drop in the voltage V _BAT , and its power supply voltage is set to V _ALM . Reference numeral 3 denotes a large-scale integrated circuit (hereinafter, referred to as LSI), and reference numeral 4 denotes a sound generator. 5 is L
Arithmetic control circuit in the SI3, 6 is an operational amplifier for detecting a drop in voltage V _BAT. 7 is a RO in which a program for issuing a warning to the driver other than the decrease in the voltage _VBAT is written.
M is a ROM in which a program for notifying a decrease in the voltage V _BAT is written. 9 and 10 are address decoders included in the ROMs 7 and 8, and 11 is an audio output port. [Problems to be Solved by the Invention] The above-described conventional speech synthesizer requires a battery for supplying a reference voltage in addition to a battery as a power source of the speech synthesizer, and thus has a disadvantage that the device cannot be downsized. is there. In addition, an operational amplifier for voltage comparison is required, and a program memory cell area for notifying a voltage drop, in addition to a program memory cell area for issuing a warning other than a voltage drop, is required. The occupied area increases, and the chip size also increases. That is, there is a disadvantage that the product cost cannot be reduced. [Means for Solving the Problems] The semiconductor device of the present invention includes a plurality of word lines and a plurality of bit lines to which a power supply voltage is selectively applied, and an intersection of the plurality of word lines and the plurality of bit lines. A semiconductor memory device including a memory configured by a plurality of first memory cells and a plurality of second memory cells connected to a portion, wherein the memory responds to an input address. A first memory cell that supplies the power supply voltage to a word line and is connected to the corresponding word line is connected to the first memory cell when the applied power supply voltage is equal to or higher than a first threshold voltage. When the bit line is in a first state and the applied power supply voltage is lower than a first threshold voltage, the bit line connected to the first memory cell is switched to a second state.
And the second memory cell connected to the corresponding word line is connected to the second memory cell when the applied power supply voltage is equal to or higher than a second threshold voltage lower than the first threshold voltage.
Setting the bit line connected to the second memory cell to the first state, and setting the bit line connected to the second memory cell to the first state when the power supply voltage is lower than the second threshold voltage. By setting the second state, in response to the input address when the power supply voltage is equal to or higher than the first threshold voltage and when the power supply voltage is lower than the first threshold voltage and equal to or higher than the first threshold voltage. And outputs different memory outputs. Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram in which a semiconductor device according to the present invention is applied to a speech synthesizer as one embodiment of the present invention. First
In the figure, reference numeral 12 denotes a battery, the power supply voltage of which is _VBAT . 13 is an LSI to which the present invention is applied, and 14 is a voice generating device. Reference numeral 15 denotes an arithmetic control circuit in the LSI 13, reference numeral 16 denotes a ROM having a plurality of memory cells having threshold values, and reference numeral 17 denotes an address decoder included in the ROM 16. Reference numeral 18 denotes an audio output port. Here, the threshold value of the ROM 16 consisting of a plurality of memory cells
Will be described. In Figure _{2, P 1, P 2, ...} P n is P
N ₁₁ , N ₁₂ , N ₂₂ , N _2n ,
N _{n1 and the} like are N-channel transistors. Among the N-channel transistors, N ₁₁ , N ₂₂ , N _{2n and the} like are connected to the power supply voltage V _BAT.
There lowered, warn the threshold value to conduct even when the voltage V _ALM to be emitted, as N _12, N _n1 like conducting at a higher voltage than V _ALM, will Threshold values that do not conduct the V _ALM ions It is manufactured by adjusting the amount of implantation. _{Further, A 1, A 2, ...} A n are each address _{line, B 1, B 2, ...} B n is the bit lines. P-channel transistor _{P 1, P 2, ... P} n are coupled source respectively to a power supply (voltage V _BAT), the drain-side bit line B _1, B _2, ... are connected to the B _n, to the gate pre A charging signal φ _P is applied. These transistors P ₁ , P ₂ ,... _Pn are turned on when a low level is applied to their gates, and are turned off when a high level is applied. N-channel transistors N ₁₁ , N ₁₂ , N ₂₂ , N _2n , N
_{In n1 and the} like, the gate is connected to the address line, the drain side is connected to the bit line, and the source side is grounded. Next, the operation of the speech synthesizer shown in FIGS. 1 and 2 will be described with reference to the time chart of FIG. (1) supply voltage V _BAT when the precharge signal phi _P goes low when higher than the voltage V _ALM P-channel transistor _{P 1, P 2, ... P} n are conductive, the bit line
The stray capacitance of B ₁ , B ₂ ,..., B _n is charged to a high level. Then, P-channel transistor P _1, P ₂ precharge signal phi _P becomes high, ... P _n are rendered non-conductive. In this case the address line A ₁ is set to the high level, and conducting the N-channel transistors N ₁₁ and N _12, the charge of the bit lines B ₁ and B ₂ are discharged to ground through N _11, N _12, respectively. Therefore, when the address line A ₁ is selected, the bit lines B ₁ ,
B ₂ ,..., B _n become low level, low level,. (2) When the power supply voltage V _BAT decreases and becomes equal to the voltage V _ALM The operation of the P-channel transistors P ₁ , P ₂ ,... _Pn is the same as in (1). When the address line A ₁ is set to the high level, N-channel transistor N ₁₁ is rendered conductive, the bit line B
₁ charge is discharged to ground through N _11. Incidentally, the level of the address line A ₁ in this case because the voltage V _ALM, N-channel transistor N ₁₂ is non-conductive, the charge of the bit line B ₂ is not discharged. Therefore the bit lines B ₁ when the address line A ₁ is chosen, B _2, ..., respectively B _n is the low level, high level, ..., a high level. When A ₂ ,..., _An is selected, the operation is the same as when A ₁ is selected, and thus the description is omitted here. By automatically arranging the memory cell including the low-voltage non-conductive transistor in the case of the above (2) so as to have a memory output that branches to the head address of the memory address of the voltage drop warning, the voltage drop is automatically performed. To detect. [Effects of the Invention] As described above, the present invention uses a memory cell that is non-conductive when the power supply voltage drops,
Since a change in the power supply voltage can be detected by a change in data output from the memory, a drop in the power supply voltage can be detected without a battery for supplying a reference voltage. for that reason,
There is an effect that the device can be downsized. Furthermore, since an operational amplifier for voltage comparison is not required, the number of parts can be reduced, and the product cost can be reduced. Further, different levels can be taken out from the same memory cell at the normal time and at the time of voltage drop, so that a program for warning other than voltage drop (for example, speed over, door unlock, etc.)
By properly combining the program for reporting the voltage drop with low voltage, non-conductive transistors in mind, the number of required memory cells can be reduced. As a result, the area occupied by the ROM can be reduced, which leads to a reduction in the chip size. This also has the effect of reducing the product cost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a speech synthesizer according to the present invention;
FIG. 2 is a circuit diagram showing a ROM in FIG. 1, FIG. 3 is a timing chart showing the operation of FIG. 1, and FIG. 4 is a block diagram of a conventional speech synthesizer. 1,2,12… Battery, 3,13… LSI, 4,14… Sound generator, 5,15… Calculation control circuit, 6… Op amp, 7,8,16
... ROM, 9, 10, 17 ... Address decoder, 11, 18 ... Audio output port.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G10L 3/00 G06F 1 / 00,12 / 16

Claims (1)

(57) [Claims] A plurality of word lines, a plurality of bit lines, a plurality of first memory cells connected to intersections of the plurality of word lines and the plurality of bit lines to which a selection voltage is applied at the time of selection; A memory device including a memory configured by a memory cell, wherein the memory supplies the selection voltage to a corresponding word line in response to an input address and is connected to the corresponding word line. The first memory cell sets the bit line connected to the first memory cell to the first state when the applied selection voltage is equal to or higher than a first threshold voltage, and the applied selection voltage is applied to the first threshold voltage. When the voltage is lower than the threshold voltage of 1, the bit line connected to the first memory cell is set to the second state, and the second memory cell connected to the corresponding word line has the applied selection voltage. Said When the threshold voltage is equal to or higher than a second threshold voltage lower than the first threshold voltage, the bit line connected to the second memory cell is set to the first state, and the selection voltage is equal to the second threshold voltage. When the selection voltage is lower than the first threshold voltage, the bit line connected to the second memory cell is set to the second state when the selection voltage is higher than the first threshold voltage. A semiconductor device which outputs a different memory output in response to the input address when the voltage is equal to or higher than the first threshold voltage. 2. 2. The semiconductor device according to claim 1, wherein the memory output is used as a next memory access address.