JP2876722B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2876722B2 JP2876722B2 JP2161003A JP16100390A JP2876722B2 JP 2876722 B2 JP2876722 B2 JP 2876722B2 JP 2161003 A JP2161003 A JP 2161003A JP 16100390 A JP16100390 A JP 16100390A JP 2876722 B2 JP2876722 B2 JP 2876722B2
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- poly
- resistance
- fusing
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のヒューズ回路に関する。Description: TECHNICAL FIELD The present invention relates to a fuse circuit of a semiconductor integrated circuit.
半導体集積回路（以下ICと称す。）においてICの外部
より何らかの操作を行うことによってICの特性や機能を
変更することがあった。たとえばプログラマブル・ロジ
ック・デバイスやPROMは書き込み操作によりユーザー自
身の思いのままの機能を達成することができた。また、
アナログICの特性を合わせ込む場合にもそのIC特性の操
作により特性を合わせ込むことができるものがある。こ
のようにICができあがった後に調整、あるいは機能の変
更を行う場合、従来主な技術としてはFAMOSやヒューズ
があった。ヒューズとしては従来のバイポーラPROMやプ
ログラマブル・ロジック・デバイスでは昇華のしやすい
金属・NiCr,TiW,PtSi等を用いている。第３図に代表的
なヒューズ回路を示す。ここで40はAL配線、41はPOLY
Siヒューズで42はコンタクトである。40のAL配線の両端
に高電位を印加すると41のPOLY Siヒューズに大電流が
流れヒューズは溶断する。2. Description of the Related Art In a semiconductor integrated circuit (hereinafter, referred to as an IC), the characteristics and functions of an IC may be changed by performing some operation from outside the IC. For example, programmable logic devices and PROMs were able to achieve the functions desired by the user through writing operations. Also,
In the case where the characteristics of an analog IC are adjusted, there is a type in which the characteristics can be adjusted by manipulating the IC characteristics. Conventionally, when making adjustments or changing functions after the completion of an IC, there have been FAMOS and fuses as main technologies. As the fuse, a metal such as NiCr, TiW, PtSi or the like, which is easily sublimated in a conventional bipolar PROM or a programmable logic device, is used. FIG. 3 shows a typical fuse circuit. Where 40 is AL wiring and 41 is POLY
42 is a contact in the Si fuse. When a high potential is applied to both ends of the AL wiring 40, a large current flows through the POLY Si fuse 41 and the fuse is blown.
この従来のヒューズは最も一般的なものであるがヒュ
ーズの材質としては前述した様に昇華しやすい金属とし
てICの標準プロセスには無い工程が必要となる場合、ま
たは標準プロセス工程内での金属（POLY Si）を使う場
合の二通りが考えられる。しかし、ここで特殊な金属を
用いる場合はプロセスの工程が増加しウェファコストが
アップしてほんの数ビットのヒューズについては非常に
不向きである。またCMOSのIC等におけるヒューズでPOLY
Siを用いる場合CVDで覆われている場合にはPOLY Siは
溶断しにくく通常はヒューズ部分のPOLY Siの上はCVDを
オープンとしておく。この場合ウェファ検査でヒューズ
を切る場合には問題ないが、モールド実装後はモールド
材がヒューズ部のCVDオープンをふさいでしまいPOLY Si
が溶断しなくなってしまう。この様に従来の技術では少
数ビットでかつモールド実装後プログラムする製品に対
しては最適ではなかった。This conventional fuse is the most common one. However, as described above, the material of the fuse is a sublimable metal that requires a process that is not included in the standard IC process. There are two ways to use POLY Si). However, when a special metal is used here, the number of process steps is increased, and the cost of the wafer is increased, which is very unsuitable for a fuse of only a few bits. POLY with fuse in CMOS IC etc.
When using Si, if it is covered with CVD, the POLY Si is hard to be blown, and usually, the CVD is left open on the POLY Si in the fuse portion. In this case, there is no problem if the fuse is blown by the wafer inspection, but after the mold mounting, the mold material blocks the CVD open of the fuse part, and the POLY Si
Will not melt. As described above, the conventional technique is not optimal for a product having a small number of bits and programmed after the mounting of the mold.
本発明はかかる問題点を解決するためのもので標準プ
ロセスの工程内で特殊な工程を設ける必要がなく、信頼
性のある安価でかつ、確実にヒューズとしての機能を果
たすヒューズを提供するものである。The present invention is intended to solve such a problem, and does not require a special process in the standard process, and provides a reliable, inexpensive, and reliable fuse that functions as a fuse. is there.
本発明の半導体装置は、高抵抗導体と低抵抗導体とが
接続され、該高抵抗導体と該低抵抗導体とのなす角が鋭
角をなすヒューズを具備することを特徴とする。The semiconductor device according to the present invention is characterized in that a high resistance conductor and a low resistance conductor are connected, and a fuse is formed in which the angle between the high resistance conductor and the low resistance conductor forms an acute angle.
本発明の一実施例を第１図に示す。第１図はヒューズ
の構成で10は配線用のAL、11はPOLY Siの高抵抗、12はP
OLY SiとALのコンタクトを表している。また13はコンタ
クトを介してALと接続される低抵抗のPOLY Siである。1
1と12のなす角度が14,15で鋭角となっている。POLY Si
の溶断特性は次の要素が大きく影響する。１つは発熱量
当りの表面積、１つは電流が流れる部分の断面積、１つ
は電界の集中である。すなわちもっとも効率よく溶断さ
せるには、発熱量が大きく表面積が小さくかつ断面積を
少なくすることが必要である。発熱量を大きくするため
には抵抗を高くする必要があり、通常のプロセスにおい
てはPOLY Siのシート抵抗はプロセスで固有であり、ま
たPOLY Siの幅はそのプロセスのデザインルールで制限
される。抵抗を高くするとPOLY Siの長さをのばす必要
があるが、表面積が増えてしまう。この様に通常の構造
では最適な溶断特性を得るのが難しい。本発明はヒュー
ズの形状を変え電界を集中させその部分の発熱量を集中
的に高め溶断特性を上げるものである。POLY Siのヒュ
ーズにおいてAL配線とコンタクトで接続される低抵抗の
部分13と細くなった高抵抗の部分11の形成する角度が鋭
角となるとその部分14,15には非常に電界が集中し、ま
た発熱量も集中する。したがって特にそこで溶断しやす
くなる。この様にPOLY Si抵抗の形状はさまざまなもの
が考えられ第２図に本発明の他の実施例を示す。この実
施例も第１図の説明と全く同様である。これは11の部分
を折り曲げて16という鋭角となる部分を形成せしめ、こ
の部分の溶断の可能性も付加し、トータル的に溶断特性
の向上を図っている。この様にして溶断部分をある特定
の部分に起こさせ易くすることによって溶断に必要なエ
ネルギーを減らすことができる。One embodiment of the present invention is shown in FIG. Fig. 1 shows the fuse configuration, 10 is AL for wiring, 11 is high resistance of POLY Si, 12 is P
Shows the contact between OLY Si and AL. Reference numeral 13 denotes a low-resistance POLY Si connected to the AL through a contact. 1
The angle between 1 and 12 is 14,15, which is an acute angle. POLY Si
The following factors greatly affect the fusing characteristics of One is the surface area per calorific value, one is the cross-sectional area of the portion where the current flows, and one is the concentration of the electric field. That is, for the most efficient fusing, it is necessary to generate a large amount of heat and have a small surface area and a small cross-sectional area. In order to increase the calorific value, it is necessary to increase the resistance. In a normal process, the sheet resistance of POLY Si is inherent in the process, and the width of POLY Si is limited by the design rule of the process. If the resistance is increased, the length of POLY Si must be increased, but the surface area increases. Thus, it is difficult to obtain the optimum fusing characteristics with a normal structure. According to the present invention, the shape of the fuse is changed to concentrate the electric field, thereby intensively increasing the amount of heat generated at that portion and improving the fusing characteristics. When the angle formed by the low-resistance portion 13 connected to the AL wiring and the contact and the thinned high-resistance portion 11 in the POLY Si fuse becomes an acute angle, the electric field is extremely concentrated on the portions 14 and 15, and The calorific value also concentrates. Therefore, it is particularly easy to melt there. As described above, various shapes of the POLY Si resistor can be considered, and FIG. 2 shows another embodiment of the present invention. This embodiment is completely the same as the description of FIG. This bends the portion 11 to form a portion having an acute angle of 16, adds the possibility of fusing this portion, and improves the fusing characteristics as a whole. In this way, the energy required for fusing can be reduced by making the fusing portion easily occur at a specific portion.
この様に本発明のヒューズを用いれば新たに特殊なプ
ロセス工程を付け加える必要がないので、ほんの少数bi
tのヒューズでも十分にコストパフォーマンスが良く非
常に安価にできる。またこれは特殊なヒューズ用金属を
用いた場合と比べ面積的にもその小ささは遜色のないも
ので大容量のヒューズアレイにも容易に適用できる。ま
たプログラム特性としても通常のPOLY Siヒューズに比
べ確実な書き込み特性が実現できる。また書き込み特性
が非常に低エネルギーの溶断によるために周囲のCVDやA
L、拡散等への破壊的影響を与えないのでICの信頼性に
とっても非常に有益である。Thus, if the fuse of the present invention is used, it is not necessary to add a new special process step.
Even a fuse of t can be made sufficiently cost-effective and very inexpensive. Also, this is as small in area as the case of using a special fuse metal, and can be easily applied to a large capacity fuse array. As for the program characteristics, more reliable writing characteristics can be realized as compared with ordinary POLY Si fuses. Also, because the writing characteristics are very low energy fusing, the surrounding CVD and A
Since it does not have a destructive effect on L, diffusion, etc., it is very useful for IC reliability.
以上の様に、本発明を用いれば簡単にできるヒューズ
として価格的にも、特性的にも非常によいものを提供で
きる。As described above, according to the present invention, it is possible to provide a fuse which can be simplified and which is very good in terms of cost and characteristics.
第１図は、本発明の実施例でヒューズ構造を示す図。 第２図は、本発明の実施例でヒューズ構造を示す図。 第３図は、従来例を示す図。 10……配線用AL 11……POLY Siの高抵抗 12……コンタクト 13……POLY Siの低抵抗部分 14,15,16……POLY Siの鋭角形成部分 40……配線用AL 41……POLY Siの抵抗 42……コンタクト FIG. 1 is a diagram showing a fuse structure in an embodiment of the present invention. FIG. 2 is a diagram showing a fuse structure in an embodiment of the present invention. FIG. 3 is a diagram showing a conventional example. 10… AL for wiring 11… High resistance of POLY Si 12… Contact 13… Low resistance part of POLY Si 14,15,16… Poly angle forming part of POLY Si 40… AL for wiring 41 …… POLY Si resistance 42 ... Contact
Claims (1)
高抵抗導体と該低抵抗導体とのなす角が鋭角をなすヒュ
ーズを具備することを特徴とする半導体装置。1. A semiconductor device comprising: a high resistance conductor and a low resistance conductor connected to each other; and a fuse having an acute angle between the high resistance conductor and the low resistance conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161003A JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161003A JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0451563A JPH0451563A (en) | 1992-02-20 |
| JP2876722B2 true JP2876722B2 (en) | 1999-03-31 |
Family
ID=15726729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2161003A Expired - Fee Related JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2876722B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008054073A1 (en) | 2008-10-31 | 2010-05-12 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device with electronic fuses with increased programming efficiency |
| JP6989460B2 (en) | 2018-08-10 | 2022-01-05 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
| CN109166841B (en) * | 2018-08-29 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Electrically programmable polysilicon fuse device structure |
| CN114464595A (en) * | 2022-04-12 | 2022-05-10 | 晶芯成(北京)科技有限公司 | Electric fuse structure |
-
1990
- 1990-06-19 JP JP2161003A patent/JP2876722B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0451563A (en) | 1992-02-20 |
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