JP2875808B2 - Trace control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (FIGS. 5 and 6) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Embodiment (FIGS. 2, 3, and 4) Effects of the Invention [Summary] Regarding the trace control method of the high-speed interface bus, data generated when the next trace data is generated before the previous trace data is transferred to the memory. In the trace control method for tracing the data on the high-speed interface bus to the memory based on the control of the direct memory access control means for the purpose of indicating the absence of Holding means, latch control means for outputting a latch signal to the temporary holding means when the specific signal reaches a specific level, and A tracer means having flag control means for indicating the presence / absence of the high-speed interface bus is detected by the latch control means, and the direct memory access control means is operated; When the data to be traced is output to the high-speed interface bus before the transfer is completed, a signal indicating the lack of the trace data is output from the flag control means to temporarily This is set in the holding means.

[Industrial applications]

The present invention relates to a trace control method, and particularly to a GPIB (Genera
l The purpose is to trace data of a high-speed interface, such as a Purpose Interface Bus.

2. Description of the Related Art In recent computer systems, there is a demand for distributed processing for high-speed processing and high-speed transfer of data. Therefore, when a failure or the like occurs in the computer system, it is necessary to trace the data of the high-speed interface to pursue the cause and analyze the result promptly.

[Conventional technology]

Computers using conventional high-speed interfaces
The system is shown schematically in FIG.

In FIG. 5, 41 is a system processor, 42 is a main memory, 50 is a high-speed interface bus such as GPIB, 5
Reference numerals 1 and 52 denote input / output devices connected to the high-speed interface bus 50, for example, devices such as facsimile devices, and 30 denotes an adapter, which is a data speed between the processor 41 and the IO side connected to the high-speed interface bus 50. The adapter 30 includes a microprocessor (hereinafter referred to as an MPU) 31, a memory 32, a high-speed interface control unit 33, a transfer unit 34, a direct
A memory access control unit (hereinafter, referred to as DMAC) 35, a bus register unit 36, and the like are provided.

Here, the MPU 31 decodes the command transmitted from the processor 41 and performs various controls for data transmission and reception. The memory 32 temporarily holds commands from the processor 41 and data to be sent to the high-speed interface bus 50, and temporarily holds data transmitted from the input / output devices 51, 52 to the main memory 42 side. The high-speed interface control unit 33 outputs a talker address (sender) or a listener address (receiver) according to an instruction from the MPU 31, or outputs an attention signal ATN indicating transmission of the talker address and the listener address. , Transmission or reception data. DMAC35
Controls transmission and reception of data between the memory 32 and the high-speed interface control unit 33. Bus register section 36
Is for transmitting and receiving data between the adapter 30 and the processor 41 side, has a register not shown, and has a DM
Equipped with AC37. The DMAC 37 controls transmission and reception of data between the main memory 42 and the memory 32 in the adapter 30.

The high-speed IF control unit 33 outputs an ATN (attention) to the L level and outputs an interrupt signal to the MPU 31 based on the instruction of the MPU 31 as shown in FIG. Address (TA) indicating the specified talker (transmitting side), and listener address (LA1 indicating 8-bit data output Dio1
8 to perform operations such as outputting data and transmitting / receiving data. Therefore, the fact that ATN becomes H indicates the head position of the data.

[Problems to be solved by the invention]

By the way, conventionally, such a high-speed interface bus
When tracing 50 data, the high-speed IF control unit 33
Had gone by. By the way, this high-speed IF control unit 33 is LS
It is designed to perform another process by accepting an interrupt so that the general-purpose MPU is easy to use, so the control information on the high-speed interface bus 50 and the state of the control signal (For example, command UNL for all I / O, device ID information such as TA and LA, ATN status, presence / absence of interface clear, etc.)
There is a case where such information is not recorded in the trace area of the memory 32 because the process is controlled and controlled by the application control unit 33 and no interrupt is output to the MPU 31.

Therefore, only a part of all data flowing on the high-speed interface bus 50 can be seen, and necessary data is missing when tracing and analyzing the state of the bus, for example, when decoding the operation at the time of error. There were such drawbacks.

In order to solve this problem, the present invention traces the data flowing on the high-speed interface bus 50, the attribute of the data (data or bus control data), and information indicating the presence / absence of missing data to the memory in the adapter. Or
It is an object of the present invention to provide a trace control method capable of controlling a DMAC by hardware or software to stop a trace and smoothly analyzing trace data, which is an object of the present invention.

[Means for solving the problem]

For this reason, in the present invention, as shown in FIG. The tracer unit 18 includes a register 18-1, a flag control unit 18-2, and a latch control unit 18-3. Register 18-1 is a transfer unit
The data transmitted via the high-speed interface bus 4, such as GPIB, transmitted through the DIO1
In addition to ~ 8 bits, the state of control signals such as ANT indicating the beginning of data, signal EOI indicating end of data, IFC (Inter Face Clear) signal for resetting high-speed interface bus 4, and the presence of missing data Is set. The flag control unit 18-2 outputs a flag signal indicating the presence or absence of the missing data.
This flag is set to ON when the next data is output before the data transfer is completed. The latch control section 18-3 outputs a register set pulse for setting each data and the like on the high-speed interface bus to the register 18-1.

The processor 1 and the main storage device 2 in FIG. 1A correspond to the processor 41 and the main storage device 42 in FIG. 4, and the high-speed interface bus 4, the input / output devices 5, 6
Corresponds to the high-speed interface bus 50, the input / output devices 51 and 52, the MPU 11, the memory 12, the high-speed IF control unit 13, the transfer unit 1
4, DMAC15, bus register section 16, DMAC17 are each MPU3
1, memory 32, high-speed IF control unit 33, transfer unit 34, DMAC 35,
They correspond to the bus register section 36 and the DMAC 37, respectively.

[Action]

In the present invention, when the talker outputs the output data Dio1 to Dio8 and sets the valid signal DAV indicating the validity of the output data to "L", the latch control unit 18-3 detects this and sends it to the register 18-1. Outputs register set pulse. As a result, the register 18-1 sets a flag FLAG indicating the presence / absence of missing data in addition to the data such as the output data Dio1-8, ATN, EOI, and IFC on the high-speed interface bus 4. A request signal is also sent to the DMAC 15 based on the register set pulse, and each data set in the register 18-1 is held in the trace area of the memory 12 by the DMAC 15.

By the way, when the next valid signal DAV is output before the transfer by the DMAC 15 is completed, the flag control unit 18-2 sets the flag indicating the existence of the missing data.
Since the FLAG is turned on, the DMAC 15 transfers the set information of the register 18-1 in which the flag is turned on to the trace area of the memory 12 this time.

Therefore, by analyzing the trace data held in the trace area, the operation state of the system can be smoothly analyzed.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3 and other drawings.

FIG. 2 is a block diagram of one embodiment of the present invention, showing details of the tracer section 18 of FIG. 1 (A), and FIG. 3 is an explanatory diagram of the operation of the present invention.

2, the same symbols as those in FIG. 1 indicate the same parts. The tracer unit 18 includes a register 18-1, a flag control unit 18
-2, in addition to the latch control unit 18-3, a request control unit 18-4 that outputs a request signal to the DMAC 15, a pulse shift unit 18-5, a transfer unit 18-6, and AND circuits 18-7 and 18-
8, an inverter 18-9 and the like.

Further, the transfer unit 14 includes a first transfer unit 14-1 for transferring data to the 8-bit data lines Dio1 to 8 and ANT, EOI, DAV, I
A second transfer unit 14-2 for transferring data to the FC is provided. Here, ANT represents the attribute of the data and is output by the high-speed IF control unit 13. When this signal line is at the L level, that is, in the state of logic "0", data is output to the Dio1 to Dio8. To indicate that EOI indicates that the final data has been output, DAV indicates that the talker has output data to Dio1 to 8, and IFC is a clear signal of a high-speed interface bus such as GPIB.

The internal clock is, for example, a 10 MHZ square wave, and is supplied to the respective control units and pulse shift units.

The latch control unit 18-3 is provided with two sets of internal flip-flops (hereinafter referred to as internal FF1 and internal FF2) and outputs a pulse of a fixed width (in this case, a latch pulse) as is well known.

The operation of the present invention will be described with reference to the time chart of FIG.

Here, the request control unit 18-4 outputs "0" at first, and outputs "1" when there is a request.

(1) In FIG. 3, Dio1～8 data is output to the talker, the time t ₀ talker indicates the validity of the data
If the DAV is set to “0”, the DAV “0” becomes the second transfer unit 14−
2, and is input to the latch control unit 18-3. Thus the latch control unit 18-3 outputs a latch pulse having a constant width at time t _1. At this time, the request control unit 18-4 sends the DM
A Since the request signal is not output, inverter 1
8-9 outputs "1", and the register set pulse is output from the AND circuit 18-8. This register set pulse is delayed by the pulse shift unit 18-5 and output as a reset pulse. If the data missing flag FLAG is output from the flag control unit 18-2, it is reset. In this manner, the DMAC 15
If the DAV becomes "0" when there is no DMA request, Dio1 to Dio8, ATN, EOI, IF
C and FLAG "0" are set. The latch pulse output from the latch control unit 18-3 is also applied to the request control unit 18-4, and the request control unit 18-4 outputs a DM pulse.
A DMA request signal is output to AC15. As a result, the DMAC 15 transfers the data held in the register 18-1 to the transfer unit 18-
Then, the transfer control is performed to the trace area of the memory 32 via the control unit 6.

(2) The DMA request signal is dropped when the data transfer is completed.
In t _4, Dio1~8 next data is outputted, when DAV to indicate this becomes "0" again at time t _5, the latch control unit 18-3 outputs a latch pulse at time t _6. At this time, since the DMA request signal output from the request controller 18-4 is "1", the AND circuit 18-7 is turned on and the AND circuit 18-8 is turned off. Therefore, the set pulse is output from the AND circuit 18-7 by the latch pulse output from the latch control section 18-3.
2 and the flag FLAG indicating data loss is
18-1 will be set. Thus, if data loss has occurred, it is possible to display the words that the 3 t ₄ less data loss, such as Dio1~8 of view occurs when the value of the register is protected.

After transferring the data held in the register 18-1 to the memory 32, the DMA request signal is turned off by the data transfer end pulse, and the data can be latched in the register 18-1. And if DAV at time t ₈ receives data from the high speed interface bus is "0", the signal ATN like indicating the head of data from the high speed interface bus is sent, data of those signal lines state together, latches the data missing flag fLAG output in the time t ₇ to the register. After that, the value of the flag is reset to deal with the next data loss. In this way, even when data loss occurs, it can be detected and notified.

When a general-purpose LSI is used as the high-speed IF control unit 13, TA and LA are deleted, and instead, when the address value matches an address value previously set in this LSI, an interrupt is issued from the high-speed IF control unit 13 to the MPU. In the present invention, data attributes and UNL, T
Trace the values of A and LA.

An input terminal is prepared on a board having a tracer unit, and inputting "1" into the input terminal generates an unmasked interrupt signal NMI in the internal MPU. The MPU uses this interrupt signal
When an NMI occurs, the NMI processing program is executed,
There, DMAC is stopped. In order to stop from the common bus, an interrupt signal NMI can be generated to the MPU by turning on a specific pit of the bus register from the CPU. When the NMI rises to the MPU, the MPU performs processing of a program called "NMi routine" that can run only when the NMI rises. In this program, an instruction for forcibly terminating the DMAC is issued to the DMAC and stopped. At this time, DMAC
Ignores the rise of the DMA request signal from the tracer unit and does not transfer the latched data. Therefore, the DMA request signal is kept rising, the DMAC is activated again by the program, and this state is maintained until the latch data is transferred.

When transferring trace data to memory, DMA chains can also be used. DMA chaining is a method of performing DMA by setting a plurality of head addresses and lengths of an area in advance to transfer data to a discontinuous area. Of course, in the present invention, tracing can be performed without interruption by designating the same region and using this region cyclically.

Also, when you want to stop the trace function by detecting an error in the device as a trigger, issue a trace stop command from the CPU1 connected to the trace function via a common bus, and trigger a hard error signal. Prepare the input means of those signals in the hardware on the trace function to stop as a trigger, use this as a trigger to generate an interrupt signal NMI in the MPU 11 mounted inside the tracer function, and stop the trace function in the NMI processing routine You may prepare the technique of making it do. That is, as shown in FIG. 4, the CPU 1 is set to the debug mode and the keyboard 20 connected to the common bus is set.
Enter a trace stop or trace start command. In the debug mode, the CPU 1 always searches for what has been input to the keyboard 20 when command processing is not being performed. When a trace stop command is issued, the CPU 1 detects this and accesses the bus register section 16 in the adapter 3 of the present invention to issue a trace stop command. Then, from the bus register section 16 to the adapter 3
The NMI is notified to the MPU 11 inside the MPU, and the MPU 11 runs the NMI routine to stop the trace.

Also, from the I / O connected to GPIB4, when the data to be received from GKPIB4 is not normal, the input unit 19 in the adapter is notified by a signal line different from GPIB4 to that effect,
The input unit 19 in the adapter notifies the MPU 11 of the NMI. The MPU 11 having received the NMI runs the NMI routine and stops tracing.

 Further, the flag FLAG may be a value by a counter.

〔The invention's effect〕

According to the present invention, the start of data, the presence or absence of missing data, and the like can be determined from the trace data, so that the trace data can be analyzed quickly.

[Brief description of the drawings]

 FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention, FIG. 3 is a diagram illustrating the operation of the present invention, FIG. FIG. 5 is an operation explanatory diagram of the conventional example, and FIG. 6 is an operation explanatory diagram of the conventional example. DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Main storage device 3 ... Adapter 4 ... High-speed interface bus 5, 6 ... I / O device 11 ... MPU 12 ... Memory 13 ... High-speed IF control unit 14 ... Transfer unit 15 ... DMAC 16 ... Bus register unit 17 ... DMAC 18 ... Tracer section

──────────────────────────────────────────────────続 き Continuation of the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 13/00 301 G06F 13/36 520 G06F 11/30

Claims (1)

(57) [Claims] 1. A trace control method for tracing data on a high-speed interface bus onto a memory under the control of a direct memory access control means, a temporary holding means for temporarily holding data on a high-speed interface bus, and a specific signal A latch control means for outputting a latch signal to the temporary holding means when a signal attains a specific level, and a tracer means having a flag control means for indicating whether or not data is lost, and latching data on the high-speed interface bus. Is detected by the latch control means, the direct memory access control means is operated, the data held in the temporary holding means is transferred to the memory, and the data to be traced before the transfer is completed is transferred to the high-speed interface. Indicates that this trace data is missing when output on the bus A trace control method, wherein a signal is output from the flag control means and set in the temporary holding means.