JP2874745B2 - Encoded data decoding method and encoded data decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. BACKGROUND OF THE INVENTION Conventional Technology (FIGS. 16 to 18) Problems to be Solved by the Invention (FIG. 19) Means for Solving the Problems Embodiments of the Invention (1) Entire Moving Picture Encoding / Decoding Device Configuration (FIGS. 1 to 5) (2) Recording order of moving image encoded data according to the embodiment (FIG. 6)
(9) (3) Editing process of moving image encoded data according to the embodiment (FIGS. 6 to 11) (4) Decoding method of edited encoded data according to the embodiment (FIGS. 8 and 12) (5) Other Embodiments (FIGS. 13 to 15) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for decoding coded data, and more particularly, to a method and an apparatus suitable for decoding coded data which has been encoded so as to be editable.

[0003]

2. Description of the Related Art Conventionally, a video signal, which is a moving image, is highly efficiently coded into intra-frame coded data and inter-frame coded data, and is recorded at a high density on, for example, a compact disk (CD-MO disk) having a magneto-optical disk configuration. There has been proposed a recording / reproducing apparatus capable of retrieving and reproducing the recorded encoded video data as needed (Japanese Patent Application Laid-Open No. 63-1183, Japanese Patent Application No. 1-267049). .

That is, as shown in FIG. 16A, for example, at time t = t ₁ , t ₂ , t _3, ..., Each image PC1, PC2, PC3,. When transmitting to a transmission system including a CD-MO recording / reproducing apparatus, image data to be transmitted is compressed using a point that a video signal has a feature that has a large autocorrelation with time, thereby improving transmission efficiency. Intra-frame encoding is performed using image PC
1, PC2, PC3,... Are subjected to a compression process of, for example, comparing pixel data with a predetermined reference value to obtain a difference.
Thus, for each of the images PC1, PC2, PC3,..., Image data of a compressed data amount is transmitted using autocorrelation between pixel data in the same frame.

[0005] In addition, the inter-frame encoding process is shown in FIG.
As shown in (B), the images PC1 and PC adjacent to each other
2, PC2 and image data PC12 consisting of differences of pixel data between PC3 ..., PC 23 obtains a ......, which the initial image PC1 at the time t = t ₁ transmitting with intraframe coded processed image data. Thus, the images PC1, PC2, PC3,... Can be highly efficiently coded into digital data having a significantly smaller data amount than when all the image data is transmitted, and transmitted to the CD-MO recording / reproducing apparatus. .

[0006] Such a video signal encoding process is executed in the moving picture encoded data generator 1 having the configuration shown in FIG. The moving picture coded data generator 1 receives the input video signal VD
Is processed in the pre-processing circuit 2 to perform one-field dropping processing and one-field line thinning processing. Then, the luminance signal and the chroma signal are divided into 16 pixels (in the horizontal direction) × 16 pixels (in the vertical direction). Transmission unit block of data (this is called a macro block) data S11
And supplies it to the image data encoding circuit 3.

The picture data coding circuit 3 receives the predicted current frame data S12 formed in the prediction coding circuit 4 and calculates the difference from the macroblock data S11 to generate inter-frame coded data. Is referred to as an inter-frame coding mode), or intra-frame coded data is formed by calculating the difference between the macroblock data S11 and the reference value data, and this is referred to as difference data S1.
3 is supplied to the transform encoding circuit 5.

The transform coding circuit 5 is composed of a discrete cosine transform circuit. The transform coding circuit 5 transforms the differential data S13 by orthogonal transform and provides transform coding data S14 obtained by high efficiency coding to the quantizing circuit 6 to perform quantization. The converted image data S15 is transmitted. Thus, the quantized image data S15 obtained from the quantizing circuit 6 is again subjected to the high-efficiency encoding process in the re-conversion encoding circuit 7 including the variable-length encoding circuit, and then supplied to the transmission buffer memory 8 as transmission image data S16. Is done.

In addition, the quantized image data S15 is subjected to inverse quantization and inverse transform coding in the predictive coding circuit 4 so as to be decoded into differential data, and then the unpredicted frame data is converted into differential data. By performing the correction operation, new pre-prediction frame data is stored, and motion compensation is performed on the pre-prediction frame data stored in the prediction encoding circuit 4 using motion detection data formed based on the macroblock data S11. As a result, the predicted current frame data can be formed and supplied to the image data encoding circuit 3, whereby the macroblock data S of the frame to be transmitted at present (that is, the current frame) is obtained.
11 is obtained as the difference data S13 between the current frame data S11 and the predicted current frame data S12.

[0010] In the configuration of FIG. 17, when transmitting the moving image described above with reference to FIG. 16, first, when the image data of the image PC1 at time t ₁ shown in FIG. 16 (A) is given as a macro Bro poke data S11, the image data The encoding circuit 3 enters the intra-frame encoding mode and supplies it to the transform encoding circuit 5 as differential data S13 subjected to intra-frame encoding processing, and through the quantization circuit 6 and the re-transform encoding circuit 7, Then, the transmission image data S16 is supplied to the transmission buffer memory 8.

At the same time, the quantized image data S15 obtained at the output terminal of the quantizing circuit 6 is subjected to predictive encoding processing in the predictive encoding circuit 4, thereby representing the transmitted image data S16 sent to the transmission buffer memory 8. predicted previous frame data is held before the frame memory, it followed when the macro Bro poke data S11 representing an image PC2 at time t ₂ is supplied to the image data coding circuit 3, the motion compensated prediction current frame data S12 by the image The data is supplied to the data encoding circuit 3.

At time t = t ₂ , the image data encoding circuit 3 supplies the inter-frame encoded difference data S 13 to the transform encoding circuit 5, whereby the difference data representing the change of the image between the frames is obtained. Is supplied to the transmission buffer memory 8 as the transmission image data S16, and the quantized image data S15 is supplied to the prediction encoding circuit 4, whereby the pre-prediction frame data is formed and stored in the prediction encoding circuit 4. You.

By repeating the same operation as described above, while the image data encoding circuit 3 executes the inter-frame encoding process, only the difference data representing the change of the image between the previous frame and the current frame is obtained. The data is sequentially transmitted to the transmission buffer memory 8. The transmission buffer memory 8 temporarily stores the transmission image data S16 transmitted in this manner, and sequentially transmits the transmission image data S16 stored at a predetermined data transmission speed determined by the transmission capacity of the transmission line 9 to the transmission data D _TRANS. And transmit it to the transmission line 9.

At the same time, the transmission buffer memory 8 detects the amount of remaining data and feeds back the remaining data S17, which changes according to the remaining data amount, to the quantization circuit 6, and performs quantum quantization according to the remaining data S17. The amount of data generated as the transmission image data S16 is adjusted by controlling the size of the transmission step, thereby maintaining an appropriate remaining amount of data (a data amount that does not cause overflow or underflow) in the transmission buffer memory 8. It has been made possible.

When the remaining amount of data in the transmission buffer memory 8 has increased to the allowable upper limit, the quantization step STPS of the quantization circuit 6 is performed by the remaining amount data S17 (FIG. 1).
By increasing the step size of 8), coarse quantization is performed in the quantization circuit 6, thereby reducing the data amount of the transmission image data S16.

Conversely, when the remaining amount of data in the transmission buffer memory 8 decreases to the permissible lower limit, the remaining amount data S17 decreases the step size of the quantization step STPS of the quantization circuit 6 to a smaller value. , Thereby causing the quantization circuit 6 to perform fine quantization, thereby increasing the data generation amount of the transmission image data S16.

[0017]

The transmission data D _TRANS transmitted from the moving picture coded data generator 1 having such a configuration is subjected to intra-frame coding processing as shown in FIGS. 19A and 19B. A1, A9,... A1, A9,..., A previous frame prediction processing frame (hereinafter, referred to as a prediction frame) , Symbol “B”) B3, B5, B
.., And an interpolation prediction processing frame corresponding to them (hereinafter, referred to as an interpolation frame and represented by a code “C”) C
2, C4, C6,... Are transmitted in the order of the input frames of the image data VD.

However, upon receiving such transmission data D _TRANS and decoding, for example, the interpolated frame C2, an intra frame A1 and a predicted frame B3 are required as shown in FIG. As a data decoding device, an intra frame A1 and a predicted frame B
Until receiving the signal No. 3, a memory for delaying the interpolation frame C2 and a control circuit for the memory are required, and the circuit configuration becomes complicated and the delay amount cannot be avoided.

For this reason, the transmission data D _TRANS is shown in FIG.
It is conceivable that the data is transmitted in the order necessary for the decoding process as shown in FIG.
_TRANS is for eight frames between intra frames A1, A9,... (A1, C2, B3, C4, B5, C6, B7,
C8), the frame groups GOF1 and GOF2 are CD-M
It is recorded as 20 sectors of the O disk.

However, in such a frame order, the CD-M
For example, an edit process for editing and rewriting the frame group GOF1 is performed on the moving picture encoded data recorded on the O disk, and when the video data is reproduced sequentially from the beginning, the eighth interpolation frame C8 in the frame group GOF1 is replaced with a frame. Interpolation based on the new seventh predicted frame B7 in the group GOF1 and the old first intraframe A9 in the frame group GOF2 makes it impossible to obtain a video signal, and consequently cannot correctly reproduce the edited result. There was a problem.

[0021] The present invention has been made in view of the above points, and solves the conventional problems at a glance so that encoded moving picture encoded data can be correctly reproduced with a simple configuration. It is intended to propose a data decoding method and apparatus.

[0022]

According to the present invention, in order to solve the above-mentioned problems, when an input image which is a moving image is encoded, intra-encoding, second inter-encoding (for predicting preceding and succeeding images, Code) and first inter-coding (only the preceding image is used as a predicted image) in order, to form a group,
A second inter-coded image (C0) of the previous group;
A frame group (GOF) composed of the order of the intra-coded image (A1), the first inter-coded image (B3), and the second inter-coded image (C2) is configured, and the frame group (GOF) ) Is added with a link flag (LPG) indicating the connection relationship with the previous frame group, and the moving image encoded data formed by the image encoding method of transmitting and recording is decoded. 3 (which is decoded from the decoded image of the intra-coded image and the decoded image of the previous frame group) and the first decoded image (which is decoded from the intra-coded image) , A fourth decoded image (which is decoded from the decoded image of the intra-coded image and the second decoded image) and the second decoded image in this order, and outputs the link flag. (LPG)
Indicates that there is no continuity with the previous frame group, the third decoded image is not output.

If the link flag indicates that there is no continuity with the previous frame group, the third decoding is performed from the decoded image of the intra-coded image and the decoded image of the previous frame group. By not outputting an image, it is possible to realize an encoded data decoding method and apparatus capable of correctly restoring encoded image data between frame groups that are not in a continuous relationship.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a moving picture encoded data recording / reproducing apparatus will be described below in detail with reference to the drawings.

(1) Overall Configuration of Moving Picture Encoding / Decoding Apparatus In FIGS. 1 and 2, the moving picture encoding / decoding apparatus 21 is composed of a moving picture encoding apparatus 21A and a moving picture decoding apparatus 21B. 21A is an input video signal VD _IN
Is preprocessed in the input circuit unit 22, and the analog / digital conversion circuit 23 converts the transmission unit block data consisting of 16 × 16 pixel data, that is, the input image data S21 consisting of macroblock MB pixel data, into pixel data processing. At the timing when pixel data is processed in each processing stage of the pixel data processing system SYM1 in units of macroblocks MB, processing information data corresponding to the processed data is transmitted via the header data processing system SYM2. The pixel data and the header data are sequentially transmitted in the pixel data processing system SYM1 and the header data processing system SYM2, respectively.

In the case of this embodiment, the input image data S21
The macro block data sequentially transmitted as is extracted from the frame image data FRM by a method as shown in FIG. First, when the input video signal VD _IN has an image size of QCIF (176 × 144 pixels), first, one frame image data FRM is one (in the horizontal direction) × 3 as shown in FIG. (In the vertical direction) are divided into block groups GOB.
As shown in FIG. 3B, 11 (in the horizontal direction) × 3 (in the vertical direction) macroblocks are included, and each macroblock MB has 16 × 16 pixels as shown in FIG. Luminance signal data Y _{00 to} Y ₁₁ (each composed of 8 × 8 pixel luminance signal data) and luminance signal data Y _{00 to} Y 11
It comprises color signal data _Cb and _Cr which are color signal data corresponding to all ₁₁ pixel data.

On the other hand, second, when the input video signal VD _IN has a CIF image size (252 × 288 pixels), two frame image data FRM are used as shown in FIG. 3 (A2). Each block group GOB is divided into (in the horizontal direction) × 6 (in the vertical direction) block groups GOB.
As shown in FIG. 3B, 11 (in the horizontal direction) × 3 (in the vertical direction) macroblocks MB are included, and each macroblock MB has 16 (as shown in FIG. 3C).
× 16 pixels of luminance signal data Y _{00 to} Y ₁₁ (each 8 ×
8 made of pixels of luminance signal data) and comprising a color signal data C _b and C _r consisting of the corresponding color signal data in all the pixel data of the luminance signal data Y ₀₀ to Y _11.

Thus, the input image data S21 transmitted for each macroblock MB is supplied to the motion compensation circuit 25, and the motion compensation circuit 25 receives the motion supplied from the motion compensation control unit 26 provided for the header data processing system SYM2. In response to the detection control signal S22, the pre-prediction frame data S23 of the pre-prediction frame memory 27 is compared with the input image data S21 to determine the motion vector data MVD (x).
And MVD (y) are detected and the motion compensation control unit 26
And the motion vector data MVD (x) and the motion vector data MVD (x) for the frame data S23 before prediction in the motion compensation circuit main body 25A.
By performing motion compensation for MVD (y), predicted current frame data S24 is formed and supplied to the image data encoding circuit 28 together with the current frame data S25 composed of the input image data S21 to be currently processed.

Here, the motion compensation control unit 26 corresponds to FIG.
As shown in (1), the transmission frame number data TR Cou indicating the transmission order of the frame image data FRM is provided for each macro block currently processed as the first header data HD1.
nter and its block group GOB (FIG. 3 (A1),
(A2)) Block group number data representing GOB addres
By adding s and macro block number data MB address representing the macro block MB, the macro block MB sequentially transmitted to each processing stage of the pixel data processing system SYM1 is displayed. At the same time, flag data FLAGS indicating the processing or processing format of the macroblock MB to be processed, motion vector data MVD (x) and MVD (y) of the macroblock MB, and difference data Σ | A− B |.

The flag data FLAGS is, as shown in FIG.
A flag corresponding to a maximum of one word (16 bits) can be provided. The 0th bit includes a motion compensation control flag MC on / off indicating whether or not the processing target macroblock MB should be processed in the motion compensation mode. Is set. The first bit of the flag data FLAGS contains an interframe / intraframe indicating whether the macroblock MB to be processed should be processed in the interframe coding mode or the intraframe coding mode. Flag Inter / Intr
a is set.

In the second bit of the flag data FLAGS, a filter flag Filter on / off indicating whether or not to use the loop filter 25B of the motion compensation circuit 25 is set. The third bit of the flag data FLAGS contains block data Y ₀₀ included in the macro block to be processed.
-C _r are made to be able to set transmission flag Coded / Not-coded indicating whether it should be transmitted (FIG. 3 (C)) a.

In the fourth bit of the flag data FLAGS, a drop frame flag indicating whether or not the processing target macroblock MB is dropped can be set. The fifth bit of the flag data FLAGS contains a forced refresh flag Refres indicating whether or not the target macroblock MB is to be forcibly refreshed.
h on / off can be set.

In the sixth bit of the flag data FLAGS, a macro block power evaluation flag MBP appreciate can be set. Also, the difference data Σ | A
-B | is the minimum value of the difference between the macroblock data A to be currently processed in the current frame data S25 and the macroblock data B compensated by the motion vector for detection in the frame data S23 before prediction. In this way, the detected motion vector can be evaluated.

The image data encoding circuit 28 supplies the current frame data S25 supplied from the motion compensating circuit 25 as it is as the differential data S26 to the transform encoding circuit 29 as it is in the intra-frame encoding mode. In the conversion mode, difference data S26, which is a difference between the pixel data of the current frame data S25 and the pixel data of the predicted current frame data S24, is supplied to the transform coding circuit 29.

The header data processing system SYM2 is provided with an inter-frame / intra-frame encoding control unit 30 corresponding to the image data encoding circuit 28. The header data HD1 and the image data encoding supplied from the motion compensation control unit 26 are provided. Operation data S3 supplied from the circuit 28
1, an inter-frame / intra-frame flag Inte for designating the encoding mode of the image data encoding circuit 28.
r / Intra (FIG. 5) and a filter flag Filter for controlling the operation of the loop filter 25B of the motion compensation circuit 25
Data required to obtain on / off (FIG. 5) is calculated and sent to the filter control unit 31 as second header data HD2.

As shown in FIG. 4, the second header data HD2 inherits the transmission frame number data TR Counter to the difference data {| AB} constituting the header data HD1 as it is, and the filter control unit 31 Power data necessary for forming the intra-frame encoding mode switching signal S33 and the filter on / off signal S34 {(A) ² (L) and {(A) ² (H),}
(AB) ² (L) and Σ (AB) ² (H), Σ (AF
B) ² (L) and Σ (A-FB) ² (H), Σ (A) are added in the inter-frame / intra-frame coding control unit 30.

Here, the power data Σ (A) ² (L) and Σ (A) ² (H) represent the lower bit and the upper bit of the sum of squares of the macroblock pixel data A of the current frame data S25. The data Σ (AB) ² (L) and Σ (A-
B) ² (H) is the sum of squares of the difference AB between the macroblock pixel data A of the current frame data S25 and the macroblock pixel data B of the predicted current frame data S24 formed without passing through the loop filter 25B. The power data Σ (A-FB) ² (L) and Σ (A-FB) ² (H) represent the lower bit and the upper bit, respectively, and are formed via the macroblock pixel data A of the current frame data S25 and the loop filter 25B. The lower bit and the upper bit of the sum of squares of the difference A-FB from the predicted current frame data S24 and the macroblock pixel data FB, and the power data Σ (A) is the macroblock pixel data A of the current frame data S25. Represents the sum and expresses the data amount as a power value in order to evaluate the size of the data to be processed (the sum of squares is independent of the sign Is obtained) as a.

The filter control unit 31 is provided with the second control unit 30 passed from the inter-frame / intra-frame coding control unit 30.
Based on the header data HD2 and the remaining amount data S32 supplied from the transmission buffer memory 32, an inter-frame / intra-frame encoding mode switching signal S33 is sent to the image data encoding circuit 28 and the loop filter 25B is sent to the loop filter 25B. A filter on / off signal S34 is sent out, and a filter flag Filter on / off representing the content of the filter on / off signal S34 is added to the second header data HD2 and passed to the threshold control unit 35 as third header data HD3. . Here, first, the filter control unit 31 activates the image data encoding circuit 28 when the amount of transmission data in the case of performing inter-frame encoding processing is larger than the amount of transmission data in the case of performing intra-frame encoding processing. Control to intra-frame encoding mode.

Secondly, the filter control unit 31 comprises:
In the case where the processing is performed in the inter-frame encoding mode, if the difference value of the predicted current frame data S24 that has not been subjected to the processing is smaller than that of the predicted current frame data S24 that has been processed in the loop filter 25B, the filter is turned on / off. The loop filter 25B is controlled so as not to perform the filtering operation by the OFF signal S34.

Thirdly, the filter control unit 31 is:
When the forced refresh mode is entered, the image data encoding circuit 28 is switched to the intra-frame encoding mode by the inter-frame / intra-frame encoding mode switching signal S33. Fourth, the filter control unit 31 should detect the overflow of the transmission buffer memory 32 based on the remaining amount data S32 supplied from the transmission buffer memory 32, and perform the frame drop processing. The third header data HD3 including a flag for instructing the threshold control unit 35 is sent to the threshold control unit 35.

Thus, the image data encoding circuit 28 supplies to the conversion encoding circuit 29 difference data S26 encoded in a mode in which the difference between the current frame data S25 and the predicted current frame data S24 is minimized.

As shown in FIG. 4, the third header data HD3 carries over the transmission frame number data TR Counter to the motion vector data MVD (x) and MVD (y) from the header data HD2, and the block data in the filter control unit 31. is added to Y ₀₀ -C corresponding to _r of 6 bits partial filter flag Filter on / off.

The transform coding circuit 29 is the discrete cosine transform circuit becomes discrete cosine transformed block coefficients values of the six _{Y 00, Y 01, Y 10} , Y 11, C b,
It is sent to the transmission block setting circuit 34 as transformed encoded data S35 zigzag scanned for each C _r .

The square of the transmission block setting circuit 34 is six Bro poke data Y coming sent as converted coded data S35 ₀₀ -C _r (FIG. 3 (C)), from the beginning of the coefficient data, respectively to the n The sum is calculated and the calculation result is passed to the threshold control unit 35 as power detection data S36.

The power detection data S every this time Sureshiyorudo control Yunitsuto 35 each blow poke data Y ₀₀ -C _r
36 is compared with a predetermined threshold. When the power detection data S36 is smaller than the threshold, transmission of the block data is not permitted. When the power detection data S36 is larger than the threshold, transmission permission / non-permission data CBPN of 6 bits is formed. This is added to the third header data HD3 passed from the filter control unit 31 and passed to the quantization control unit 36 as fourth header data HD4.
The blow poke data Y ₀₀ -C _r corresponding from the transmission block setting circuit 34 is sent as the transmission to the quantization circuit 37 Bro poke patterned data S37.

[0046] Here, the fourth header data HD4, as shown in FIG. 4, the transmission frame number data TR Counter～ filter flag Filter on / off of the header data HD3 with take over as it is, block Y ₀₀ -C _r in Sureshiyorudo control Yunitsuto 35 , A transmission enable / disable flag CBPN corresponding to 6 bits generated corresponding to.

The quantization control unit 36 is the fourth header data HD4 passed from the threshold control unit 35.
And a quantization step size control signal S38 obtained by executing a quantization step size determination process based on the remaining amount data S32 transmitted from the transmission buffer memory 32.
Is given to the quantization circuit 37, whereby the quantization circuit 37 is subjected to quantization processing with a quantization step size adapted to the data included in the macroblock MB, and as a result, a quantized image obtained at the output terminal of the quantization circuit 37 is obtained. The data S39 is supplied to the variable length coding circuit 38.

[0048] This quantization control Yunitsuto 36 together, as shown in FIG. 4, a fifth header data HD5, Bro poke data Y ₀₀ -C based on header data HD4
_r (FIG. 3 (C)) respectively corresponds to the flag data FLAG
S and the motion vector data MVD (x) and MVD (y) are separated and serially arranged to form data, which are passed to the variable length coding circuit 38 and the inverse quantization circuit 40.

Here, as shown in FIG. 4, the header data HD5 includes the transmission frame number data TR Counter to the macro block number data MB addre in the header data HD4.
ss is taken over as it is, and the quantization control unit 36
Quantized size data QNT and block data Y
₀₀ -C flag for _r data FLAGS, adds the motion vector data MVD (x) and MVD (y).

The variable-length encoding circuit 38 includes header data HD
5 and the quantized image data S39 are subjected to variable-length encoding to form transmission image data S40, which is supplied to the transmission buffer memory 32. Variable-length coding circuit 38 during the variable-length coding the blow poke data Y ₀₀ -C _r, the corresponding flag data "frame dropping" on the basis of the FLAGS, or when the "not sent" is specified, the block Processing is performed to discard the data without sending it as transmission image data S40.

The transmission buffer memory 32 stores the transmission image data S40, reads out the transmission image data S40 at a predetermined transmission speed, and combines the transmission image data S40 with the transmission audio data S41 transmitted from the audio data generating device 42 in the multiplexer 41, thereby combining the moving image encoded data. It is sent to the CD-MO device as VD _REC .

The inverse quantization circuit 40 converts the quantized image data S39 sent from the quantization circuit 37 into header data HD5.
After the inverse quantization, the inverse quantized data S42
Is supplied to the inverse transform encoding circuit 43 to be converted into the inverse transform encoded data S43 and then supplied to the decoder circuit 44. Thus, the encoded difference data S44 representing the image information transmitted as the transmission image data S40 is predicted. It is supplied to the previous frame memory 27. At this time, the pre-prediction frame memory 27 modifies the pre-prediction frame data stored up to that time using the encoded difference data S44 and stores it as new pre-prediction frame data.

Thus, the moving picture coding apparatus 21 having the configuration shown in FIG.
According to A, pixel data is pipeline-processed in macroblock units in the pixel data processing system SYM1 based on the header information supplied from the header data processing system SYM2, but the header data processing is synchronized with this. By transferring the header data in the system SYM2, the header data processing system SY
Pixel data can be adaptively processed as needed by adding or deleting header data as needed in each processing stage of M2.

As shown in FIG. 2, the moving picture decoding apparatus 21B decodes the moving picture encoded data V reproduced from the CD-MO apparatus.
D _PB is received by the transmission buffer memory 52 via the demultiplexer 51, and the transmission audio data S 51 is received by the audio data receiving device 53.

The image data received by the transmission buffer memory 52 is received by the variable-length inverse conversion circuit 54 into the received image data S5.
2 and header data HD11, inversely quantized to inversely quantized data S53 by an inverse quantization circuit 55, and subjected to inverse discrete transform processing by an inverse transform encoding circuit 56 to inversely transform to inverse transformed encoded data S54. Is done.

The inverse transform coded data S54 is supplied to the decoder circuit 57 together with the header data HD12 formed in the inverse quantization circuit 55, and the coded difference data S5
5 is stored in the frame memory 58.

Thus, the image data transmitted to the frame memory 58 based on the encoded difference data S55 is decoded, and the decoded image data S56 is converted into an analog signal by the digital / analog conversion circuit 59. Output video signal VD _OUT via output circuit section 60
Is sent as

(2) Recording Order of Encoded Moving Image Data According to Embodiment FIG. 6 in which parts corresponding to those in FIG. 1 and FIG.
In the figure, 70 indicates a moving picture encoded data recording / reproducing apparatus to which the encoded data decoding method according to the present invention is applied as a whole. In the case of the moving picture encoded data recording / reproducing device 70,
The input video signal VD _IN is encoded with high efficiency through the above-described moving image encoding / decoding device 21, and the resulting moving image encoded data VD _REC is input to the CD-MO device 71 and is input to a CD-MO disk (not shown). ).

[0059] reproduced signal obtained from the CD-MO unit 71 conversely as moving picture coded data VD _PB, is inputted to the moving picture coding / decoding apparatus 21, as a result moving picture coded data V
An output video signal VD _OUT obtained by decoding D _PB is transmitted. In the case of the moving image encoded data recording / reproducing device 70, the moving image encoding / decoding device 21
Recording / reproduction control circuit 73 including PU (central processing unit)
It is connected to the encoding and decoding of moving picture coded data VD _PB of the recording and reproducing control circuit 73 by connexion input video signal VD _IN is controlled.

In addition to this, the CD-MO device 71 has an SCS
Built-in I (small computer system interface), SC
The recording / reproducing control circuit 73 controls the recording / reproducing operation via the SI bus 74, SCSI control circuit 75, and bus 72.

The moving picture coded data VD _REC transmitted from the moving picture coding / decoding device 21 is a format having a hierarchical (layer) structure as shown in FIG.
The data is input to the O device 71 and is input to the moving image encoding / decoding device 21 from the CD-MO device 71 as moving image encoded data VD _{PB in} the same format.

That is, the moving picture encoded data VD _REC and VD _REC
In D _PB , data corresponding to eight frames of the input image signal VD _IN as a frame group layer is defined as one frame group GOF, and a frame group start code (GOFSC) indicating the start of the one frame group and the immediately preceding GOF. Link flag (LPG) indicating the continuity relationship, horizontal of the frame to be transmitted,
Data (HORSIZE, VERSIZE, HVPRAT) representing the vertical size and the ratio of the number of pixels in the horizontal and vertical directions, data representing the rate of a transmission frame (RATE), picture layer data consisting of image data for one frame (P.data) (8) and a stuffing bit (TSB) (FIG. 7 (A)).

One frame of the picture layer data (P.data) includes a frame start code (PSC) indicating the start of one frame, a frame number (TR), data (PEI, PSPARE) indicating extended information, and a block unit. It is composed of one frame of block group layer data (GOB data) composed of image data (FIG. 7B).

Block group layer data (GOB dat
The data of one block group of a) includes a block group start code (GBSC) indicating the start of one block group, address data (GN) of the block group, and data (GQUAN) relating to the requantization step size of each block group.
T), data (GEI, GSPARE) representing extended information, and macroblock layer data (MB data) for one block group (FIG. 7C).

Macro block layer data (MB data)
One macro block is composed of data (MBA) representing the address of the macro block, data (MTYPE) representing the type of the macro block, data of the requantization step size in the macro block (MQUANT), and the motion vector of each macro block. The data (MVD1 and MVD2), one macroblock of block pattern data (CBP) in the macroblock and block layer data (Block data) (FIG. 7 (D)).

1 of the block layer data (Block data)
The block is composed of a predetermined number of coefficient data (TCOEF) and data (EOB) indicating the end of the block layer (FIG. 7 (E)).

Here, the moving picture coding apparatus 2 according to this embodiment
In FIG. 1A, the frame recording order based on the input image signal VD _IN as shown in FIG.
As shown in (B), the moving picture encoded data V in the frame recording order according to the decoding processing on the moving picture decoding apparatus 21B side.
The D _REC is sent to the CD-MO device 71 for recording, and the moving image coded data VD _PB reproduced from the CD-MO device 71 is stored in the moving image decoding device 2 in this frame recording order.
1B.

By doing so, for example, the interpolation frame C
2 when decoding the intra frame A required for decoding
1 and the predicted frame B3 have already been input, and for example, when decoding the interpolation frame C4, the prediction frames B3 and B5 required for decoding have already been input, whereby the video decoding device 21B immediately starts the interpolation frame C2 or C4.
Can be executed.

Here, the moving picture coding apparatus 21A of this embodiment
In the case of, as shown in FIG. 9, the frame recording order based on the input image signal VD _IN is changed using the frame order rearranging circuit 80 built in the motion compensating circuit 25 as described above. The recording order is changed.

In this frame order rearranging circuit 80, first to third one-frame delay circuits 81, 82 and 8
3 so that a motion vector detection process can be executed in addition to a frame order rearrangement process. That is, the input image signal VD _IN is subjected to predetermined processing in the input circuit section 22 and the analog digital conversion circuit 23, and the input image data S
21 is input to the first one-frame delay circuit 81.

The first delay data S _D1 sent from the first one-frame delay circuit 81 is input to the second one-frame delay circuit 82 and the first delay data S _D1 It is input to the input terminal a. Also, the second delay data S sent from the second one-frame delay circuit 82
_D2 is further delayed by one frame through a third one-frame delay circuit 83, and is input to the second input terminal b of the first frame selection circuit 84 as third delay data S _D3 .

Thus, the frame order rearranging circuit 8
0, the input image data S21 is sequentially input at the timing of each frame, and the first or second input terminal a or b of the first frame selection circuit 84 is sequentially input at the timing of the frame pulse FP synchronized with the input image data S21. Is selectively controlled so that the rearrangement process in the frame order can be executed.

The input image data S21 and the first delay data S _D1 are input to the first motion vector detection circuit 85, and the resultant motion vector data between the input image data S21 and the first delay data S _D1 is obtained. D _MV1 and the difference data D _DR1 are sent to the motion compensation unit 26.

The second and third delay data S _D2 and S _D2
D3 is input to the first and second input terminals a and b of the second frame selection circuit 86, and one of them is selected at the timing of the frame pulse FP and input to the second motion vector detection circuit 87. . In addition to this, the first delay data S _D1 is input to the second motion vector detection circuit 87, and the resulting first delay data S _D1 and second or third delay data S _D1 are obtained. _D2 or motion vector data D _MV2 and the difference data D _DR2 between S _D3 is sent to the motion compensation Yunitsuto 26. Thus when the input image signal VD _IN by high efficiency coding process to obtain a moving picture coded data VD _REC, instead of the frame order based on the input image signals VD _IN, as rearranged in the frame order according to the decoding process This makes it possible to realize a moving image encoded data transmission method that can simplify and improve the circuit configuration and control on the decoding processing side.

(3) Edit processing of moving picture coded data according to the embodiment The recording / playback control circuit 73 of the moving picture coded data recording / reproducing apparatus 70 responds to an edit command inputted from the outside, as shown in FIG. The edit processing procedure RT0 shown is executed, whereby, as shown in FIG. 11, the moving picture coded data VD _REC recorded for one frame group recorded every 20 sectors on the CD-MO disc is rewritten in one frame group unit. Edit processing is performed.

In this embodiment, the moving picture encoded data V
In D _IN , as shown in FIG. 8C, the interpolated frame and the predicted frames A1, C
Instead of the conventional method in which eight frames of 2, B3, C4, B5, C6, B7, and C8 are set to one frame group GOF1, GOF2,..., An intraframe following the interpolated frame C0 immediately before the intraframe A1 is interpolated. Frames and predicted frames C0, A1, C2, B3, C4, B5, C
6, B7 is one frame group GOF11, GOF12,.
It is made to transmit as.

Thus, one frame group GOF11,
GOF12,..., A frame in another frame group GO
The inconvenience included in F11, GOF12,... Can be prevented beforehand. Actually, the recording / reproduction control circuit 73 performs the edit processing procedure RT0 shown in FIG.
In the next step SP1, the edit instruction is analyzed.

Here, for example, when it is instructed to rewrite the moving image encoded data VD _REC for 40 sectors of the third and fourth frame groups GOF3 and GOF4 shown in FIG. Move to the next step SP2.

In this step SP2, the recording / reproducing control circuit 73 sends a control command corresponding to the edit command to the SCSI control circuit 75, whereby the SCSI bus 74
Control of the rewriting of the CD-MO disc is executed. At this time, the recording / reproduction control circuit 7 via the bus 72
3, the new two-frame group GOF3N, G
The input video signal VD _{IN for} OF4N is passed through the moving image encoding / decoding device 21 as moving image encoded data VD _{REC to} be CD.
-Input to the MO device 71.

Subsequently, the recording / reproducing control circuit 73 executes the next step SP3, determines whether or not the rewriting process has been completed. If a negative result is obtained here, the process returns to step SP2 to return to the CD.
-The rewriting control of the MO disk is continued, and when an affirmative result is finally obtained, the process proceeds to step SP4. This step SP4
, The recording / reproduction control circuit 73 outputs the edited CD
-The head sector of the MO disk (in this embodiment, the 40th sector
Read the contents of a sector).

Thus, in the next step SP5, the recording / reproduction control circuit 73 sets the link flag (LPG) of the frame group layer present at the 25th bit from the head of the head sector as an edit flag, and sets this as the edit flag of the CD-MO disk. Write to the read sector position.

Subsequently, the recording / reproduction control circuit 73 proceeds to step S
At P6, the contents of the sector following the last sector of the edited CD-MO disk (in this embodiment, the 80th sector) is read. Thereby, the recording / reproduction control circuit 7
In the next step SP7, the link flag (LPG) of the frame group layer existing at the 25th bit from the head of the sector is set as an edit flag in the same manner as described above, and this is set at the sector position where the CD-MO disk is read. In the next step SP8, the edit processing procedure RT0 is completed.

In practice, the edited data is
Moving picture encoded data VD recorded on a D-MO disc
_{The REC} is read under the control of the recording / playback control circuit 73, and the moving picture coded data VD _PB obtained as a result of this is input to the moving picture coding / decoding device 21.

(4) Decoding Method of Edited Encoded Data According to Embodiment In this embodiment, in the moving picture decoder 21B, as shown in FIG. with, and executes an input image signal VD _iN rearranging inverse rearranging the frame order based on the frame order according to the decoding process, see Edeitsutofuragu set in frame group layer link flag (LPG) Then, the edit reproduction process is executed.

That is, the inverse transform encoded data S54 sent from the inverse transform encoding circuit 56 is directly input to the first input terminal A of the selector circuit 91 of the decoder circuit 57, and is also transmitted through the frame memory 92 to, for example, two frames. Secondly, the signal is input to the input terminal B.

Each of the selector circuit 91 and the frame memory 92 operates at the timing of the frame pulse FP, whereby the frame sequence (FIG. 8) corresponding to the decoding process is performed.
(B)), a reverse rearrangement process from the frame order (FIG. 8A) based on the input image signal VD _IN is executed.

[0087] Note that the selector circuit 91, Edeitsutofuragu signal S _LPG in accordance with the Edeitsutofuragu set in the link flag of header data HD12 formed in the inverse quantization circuit 55 (LPG) is input, the Edeitsutofuragu signal S _LPG Is interrupted only when it indicates that is set, and the next arriving frame is output as it is.

For example, with respect to the new frame data GOFN3 and GOFN4 thus edited, the old frame data GOF1, GOF2, G
OF5,... Can prevent the possibility that the reproduced image is disturbed due to the mixing of the frame data in the OF5. When the edit flag is set in the frame group GOF12 shown in FIG. 8D, two frames of the intra frame A9 are output instead of the eighth interpolated frame C8 after the reverse rearrangement.

According to the above arrangement, when decoding the edited moving image encoded data in which the edit flag S _LPG is set in the link flag (LPG) of the edited frame group and the frame group immediately after the editing, The presence or absence of the edit flag S _LPG is detected, and the edit flag S _LPG is detected.
When is set, an image belonging to the original preceding frame group is used as a predicted image and an interpolated frame is not output, and the immediately preceding intra frame is output and decoded. Thereby, the edited moving image encoded data can be correctly reproduced.

(5) Other Embodiments (5-1) In the above-described embodiment, when the editing process is performed on the recorded moving picture encoded data in frame group units, the edited frame group and immediately after the editing are executed. The case where the edit flag is set in the link flag (LPG) of the frame group has been described.
For example, when the recording and reproduction control circuit 73 stores the edited frame group, the editing process can be performed well only by setting the edit flag in the link flag (LPG) of the frame group immediately after the editing.

(5-2) In the above embodiment,
When edit processing is performed on the recorded moving image encoded data in frame group units, the link flag (L) of the edited frame group and the frame group immediately after editing is set.
(PG) is set as the edit flag, but instead of this, a serial number starting from a predetermined random number generated by the recording / reproduction control circuit 73 is sequentially assigned to the frame number (TR) of the picture layer on the moving image encoding device 21A side. The edit flag signal S _{LPG is} added at the timing when the discontinuity of the frame number (TR) is detected during the edit reproduction process.
If the same signal is generated, the same effect as in the above-described embodiment can be realized.

In this case, the discontinuity of the frame number (TR) is detected by the discontinuity detecting circuit 95 as shown in FIG. That is, in the discontinuity detection circuit 95, the frame number (TR) of the picture layer included in the inversely-transformed coded data S54 is input to the comparison circuit 96 and the latch circuit 97, which is provided in parallel with the above-described frame order / reordering circuit 90. .

The latch circuit 97 has a frame pulse FP
The latch operation is executed at the timing of (1). As a result, the frame number (TR) delayed by one frame is input to the adding circuit 98, the value “1” is added, and the value is input to the comparing circuit 96 as the comparison frame number C _TR. . Thereby, the comparison circuit 96
Compares the values of the frame number (TR) and the comparison frame number C _TR , generates a mismatch detection signal having a logic “H” level when they do not match, and sends it to the AND circuit 99.

In addition to this, in the AND circuit 99, the head frame group signal GOFF having a logical "H" level is input through the inversion circuit 100 after being inverted during the playback processing of the head frame group. At the time of group reproduction processing, the mismatch detection signal is controlled to a logic "L" level, and otherwise, an edit flag signal S _LPG having a logic level corresponding to the mismatch detection signal is sent to the selector circuit 91 of the frame order reverse sorting circuit 90. Send out.

(5-3) Further, in the above-described embodiment, when the edit processing is performed on the moving picture coded data on a frame group basis, the edited frame group is identified using the edit flag and the frame number (TR). However, for each interpolated frame C in the frame group, the intra frame A and the predicted frame B in the frame group
If only interpolation is performed using only the data and the relationship between each frame is completed within the frame group, a moving picture encoded data recording method that can easily and freely execute edit processing even if the image quality slightly deteriorates is realized. it can.

(5-4) Further, in the above-described embodiment, the intra-frame A, the predicted frame B, and the interpolated frame C are arranged in the frame order of the moving picture coded data arranged as shown in FIG. Although the case of changing is described, the frame arrangement of the moving image encoded data is not limited to this, and even in the case shown in FIG. 14A or FIG. If the data is rearranged and transmitted in the frame order according to the processing order on the decoding side as shown in FIG. 15 (B), the same effect as in the above-described embodiment can be realized.

In this case, FIG. 14 (C) and FIG. 15 (C)
Are replaced by the frame groups GOF21, GOF22,..., GOF31, GOF as shown in FIG. 14 (D) and FIG.
With the arrangement of 32,..., The same effect as in the above-described embodiment can be realized for the edit processing.

(5-5) Further, in the above-described embodiment, a case has been described in which a video signal is encoded with high efficiency and recorded and reproduced on a CD-MO disk. However, the recording medium is not limited to this, and other optical media may be used. It is suitable for wide application to disks, magnetic disks, magnetic tapes and the like.

(5-6) Further, in the above-described embodiment, the case where the video signal is encoded with high efficiency and recorded on the CD-MO disc and reproduced is described. However, the present invention is not limited to this, and the video signal is not limited to this. The present invention is suitable for wide application to a moving picture encoded data transmission method for highly efficient encoding and transmission.

[0100]

As described above, according to the present invention, when the link flag indicates that there is no continuous relationship with the previous frame group, the decoded image (I) of the intra-coded image is obtained.
And the third image decoded from the decoded image of the previous frame group
By not outputting the decoded image (B ′), it is possible to realize a coded data decoding method and apparatus capable of correctly restoring coded image data between frames that are not in a continuous relationship.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a moving picture coding apparatus according to an embodiment.

FIG. 2 is a block diagram showing a configuration of a moving picture decoding apparatus according to an embodiment.

FIG. 3 is a schematic diagram illustrating a configuration of frame image data.

FIG. 4 is a block diagram showing a detailed configuration of a header data processing system.

FIG. 5 is a schematic diagram illustrating a configuration of flag data.

FIG. 6 is a block diagram showing a configuration of a moving picture coded data recording / reproducing apparatus according to an embodiment.

FIG. 7 is a schematic diagram for explaining a format of recording / reproducing data;

FIG. 8 is a schematic diagram for explaining a recording order of encoded moving image data according to the embodiment.

FIG. 9 is a block diagram showing a configuration of a frame order rearranging circuit.

FIG. 10 is a flowchart for explaining an edit process.

FIG. 11 is a schematic diagram for explaining a recording area of a CD-MO disc;

FIG. 12 is a block diagram showing a configuration of a frame order reverse sorting circuit.

FIG. 13 is a block diagram showing a discontinuity detection circuit according to another embodiment.

FIG. 14 is a schematic diagram for explaining a recording order of encoded moving image data according to another embodiment.

FIG. 15 is a schematic diagram for explaining a recording order of moving image encoded data according to another embodiment.

FIG. 16 is a schematic diagram used for describing intra-frame / inter-frame encoding processing.

FIG. 17 is a block diagram showing a conventional moving picture encoded data generator.

FIG. 18 is a characteristic curve diagram showing the quantization step.

FIG. 19 is a schematic diagram for explaining a recording order of conventional moving image encoded data.

[Explanation of symbols]

21 moving picture encoding / decoding apparatus, 21A moving picture coding apparatus, 21B moving picture decoding apparatus, 25 motion compensation circuit, 26 motion compensation control unit, 27 frame memory before prediction, 28 image data encoding circuit, 29
... A transform coding circuit, 30... An inter-frame / intra-frame coding control unit, 31... A filter control unit,
32: Transmission buffer memory, 34: Transmission block setting circuit, 35: Threshold control unit, 36 ...
Quantization control unit, 37... Quantization circuit, 38.

Claims (4)

(57) [Claims] 1. An intra-encoding (A) wherein only an image temporally preceding in display order is used as a predicted image.
The first inter-coding (B) that can be used, and images that are temporally before and after in the display order are used as predicted images.
When encoding a moving image using three types of encoding methods, the second inter-encoding (C) that can be used, the input image is encoded using the above-described intra-encoding, at least one image.
The second inter coding and the first inter code
Into one group by encoding in at least one of the second inter-codes of the previous group.
Encoded image (C0) and the intra-encoded image (A1)
And the first inter-coded image (B3)
And one of the second inter-coded images (C2)
A frame group (GOF) consisting of an order is constructed,
Group (GOF) at least with the previous frame group
A link flag (LPG) indicating the relationship is added for transmission / recording.
Moving images formed by an image encoding method
Coded data decoding method for decoding coded data
Te, a first decoded image of the intra-coded picture is decoded from the decoded image of the intra-coded picture
A second decoded image, a decoded image of the intra-coded image, and a previous frame.
At least one image decoded from the
A third decoded image, a decoded image of the intra-coded image, and the second decoded image.
At least one fourth decoding decoded from the encoded image
Forming a coded image, the at least one third decoded image, the first condensate
Encoded image, the at least one fourth decoded image, and
And outputs the decoded image in the order of the second decoded image.
And the link flag (LPG) is continuous with the previous frame group.
When there is no relationship , the third decoded image
Coded data characterized in that no image is output
Data decoding method. The link flag is linked to a previous frame group.
The third decryption when there is no connection
A contract that outputs another image instead of an image
The encoded data decoding method according to claim 1. 3. Intra-encoding (A), wherein only an image temporally preceding in display order is used as a predicted image.
The first inter-coding (B) that can be used, and images that are temporally before and after in the display order are used as predicted images.
3 types of second inter-coding (C) that can be
When encoding a moving image using a kind of encoding method, the input image is subjected to the intra-encoding,
The second inter coding and the first inter code
Into one group by encoding in at least one of the second inter-codes of the previous group.
Encoded image (C0) and the intra-encoded image (A1)
And the first inter-coded image (B3)
And one of the second inter-coded images (C2)
A frame group (GOF) consisting of an order is constructed,
Group (GOF) at least with the previous frame group
A link flag (LPG) indicating the relationship is added for transmission / recording.
Depending on the image encoding method to be recorded,
For decoding moving image encoded data formed in the device
A first decoded image of the intra-coded image and a decoded image of the intra-coded image.
A second decoded image, a decoded image of the intra-coded image and a previous frame
At least one third image decoded from the group of decoded images
, The decoded image of the intra-coded image, and the second decoding
At least one fourth decoding decoded from the encoded image
Decoding means for forming a decoded image , the at least one third decoded image, and the first decoded image.
Encoded image, the at least one fourth decoded image, and
And output the decoded image in the order of the second decoding
In both cases, the link flag (LPG) is a continuation of the previous frame group.
When there is no relationship, the third decoded image
Patent in that it comprises a control means to prevent output image
A coded data decoding device. 4. The control means according to claim 1 , wherein said link flag is set to a previous value.
When it indicates that there is no continuous relationship with the frame group,
Instead of the third decoded image, this outputting another image
4. The encoded data decoding apparatus according to claim 3, wherein
Place.