JP2874071B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2874071B2
JP2874071B2 JP31207291A JP31207291A JP2874071B2 JP 2874071 B2 JP2874071 B2 JP 2874071B2 JP 31207291 A JP31207291 A JP 31207291A JP 31207291 A JP31207291 A JP 31207291A JP 2874071 B2 JP2874071 B2 JP 2874071B2
Authority
JP
Japan
Prior art keywords
film
hole
organic resin
silicon nitride
resin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP31207291A
Other languages
Japanese (ja)
Other versions
JPH05152242A (en
Inventor
能充 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31207291A priority Critical patent/JP2874071B2/en
Publication of JPH05152242A publication Critical patent/JPH05152242A/en
Application granted granted Critical
Publication of JP2874071B2 publication Critical patent/JP2874071B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、微細なパターンを有
し、高集積な素子の配置を可能とする半導体装置の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a fine pattern and capable of arranging highly integrated elements.

【0002】[0002]

【従来の技術】たとえば16MDRAMに代表されるよ
うに半導体素子の集積度を上げるためにその微細化が進
んでいる。素子自身の専有面積は電気特性より決まる各
層の必要寸法とホトリソグラフィー技術上の解像度およ
び重ね合せ精度によって律速されている。この中で特に
重ね合せに対する余裕分は相当量を必要とする必要悪で
ある。
2. Description of the Related Art In order to increase the degree of integration of semiconductor devices, as typified by, for example, 16 MDRAMs, miniaturization of the semiconductor devices is progressing. The area occupied by the element itself is determined by the required dimensions of each layer determined by the electrical characteristics, the resolution in photolithography, and the overlay accuracy. Among them, particularly, a margin for superposition is a necessity that requires a considerable amount.

【0003】ところでDRAMをはじめとする多くのデ
バイスの製造工程において穴の底面のポリシリコンの一
部を除去し、その下の基板や導電膜と上部の配線層との
接続を行う工程が必要である。図2に従来法によってこ
のような穴の底面のポリシリコン層に開口する場合の工
程を示す。図において、1はシリコン基板、2Aは薄い
酸化膜、2Bはシリコン窒化膜、3はBPSG(Borond
oped Phospho-Sillicate Glass)膜、4はポリシリコン
膜、5はホトレジスト膜である。この場合、図2(a)
に示すように、ホトレジスト膜5によって開口部のパタ
ーンを形成してから下のポリシリコン膜4をエッチング
することになる。この方法によればホトレジスト膜5の
開口パターンと穴の側壁の間にアライメントに対する余
裕が必要となる。この量は現在のステッパーを用いると
約0.2μm程度となる。
In the process of manufacturing many devices such as DRAMs, it is necessary to remove a portion of the polysilicon at the bottom of the hole and connect the underlying substrate or conductive film to the upper wiring layer. is there. FIG. 2 shows a process for forming an opening in the polysilicon layer at the bottom of such a hole by a conventional method. In the figure, 1 is a silicon substrate, 2A is a thin oxide film, 2B is a silicon nitride film, and 3 is a BPSG (Borond
oped Phospho-Sillicate Glass) film, 4 is a polysilicon film, and 5 is a photoresist film. In this case, FIG.
As shown in FIG. 6, after the pattern of the opening is formed by the photoresist film 5, the lower polysilicon film 4 is etched. According to this method, a margin for alignment is required between the opening pattern of the photoresist film 5 and the side wall of the hole. This amount is about 0.2 μm using a current stepper.

【0004】[0004]

【発明が解決しようとする課題】このような従来の構成
では、16MDRAMをはじめとする微細なデバイスの
集積度を向上する上で、前述のアライメント余裕は極め
て大きな妨げとなる。
In such a conventional configuration, the above-mentioned alignment margin becomes a great hindrance in improving the degree of integration of fine devices such as a 16 MDRAM.

【0005】本発明は、このような従来の課題を解決す
るもので、アライメント余裕分を全く必要としないポリ
シリコン膜の底面の自己整合的な開口方法による半導体
装置の製造方法を提供することを目的とするものであ
る。
The present invention solves such a conventional problem, and provides a method of manufacturing a semiconductor device by a self-aligned opening method on the bottom surface of a polysilicon film which does not require any alignment margin. It is the purpose.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体基板表面のBPSG膜等の膜の所定
部に形成された穴部を含む領域にポリシリコン膜を形成
する工程と、そのポリシリコン膜の表面にシリコン酸化
膜とシリコン窒化膜を形成する工程と、上記穴部内のみ
に少なくともその穴部底面に形成されたシリコン窒化膜
を覆うようにホトレジスト等の有機樹脂膜を形成する工
程と、その有機樹脂膜をマスクにして、少なくとも穴の
底面に形成されたシリコン窒化膜を残して他のシリコン
窒化膜を除去する工程と、有機樹脂膜を除去した後シリ
コン窒化膜の除去されたポリシリコン膜上に熱酸化でシ
リコン酸化膜を形成する工程と、そのシリコン酸化膜を
マスクにして穴部底面に形成されたポリシリコン膜をエ
ッチングによって自己整合的に除去する工程とを少なく
とも有する構成による。
In order to achieve the above object, the present invention comprises a step of forming a polysilicon film in a region including a hole formed in a predetermined portion of a film such as a BPSG film on the surface of a semiconductor substrate; Forming a silicon oxide film and a silicon nitride film on the surface of the polysilicon film, and forming an organic resin film such as a photoresist only in the hole so as to cover at least the silicon nitride film formed on the bottom surface of the hole. Using the organic resin film as a mask, removing the other silicon nitride film while leaving at least the silicon nitride film formed on the bottom surface of the hole, and removing the silicon nitride film after removing the organic resin film. Forming a silicon oxide film on the formed polysilicon film by thermal oxidation, and etching the polysilicon film formed on the bottom of the hole by using the silicon oxide film as a mask. By at least a structure and a step for himself consistent removed.

【0007】[0007]

【作用】上記構成によれば、穴の底面のポリシリコン膜
を底面全面で開口できるため、穴の側面とポリシリコン
膜開口部の重ね合せ余裕が不要となる。
According to the above construction, since the polysilicon film on the bottom surface of the hole can be opened over the entire bottom surface, there is no need for a margin for overlapping the side surface of the hole and the opening of the polysilicon film.

【0008】[0008]

【実施例】以下に本発明の一実施例を図1を参照して説
明する。図1は本発明の半導体装置の製造方法における
穴の底面部分のポリシリコン膜を開口する工程断面図で
ある。従来例と同様に図1(a)に示すようにシリコン
基板1上に20nmの酸化膜2Aを形成した後、40n
mのシリコン窒化膜2Bを減圧CVD法によって形成し
た。この後厚さ800nmのBPSG膜3を常圧CVD
法によって形成した。この時BPSG膜中のボロン濃度
は3wt%、リン濃度は6wt%とした。その後窒素中
で900℃30分の熱処理を行った後、直径が1.6μ
mの穴をレジストをマスクにしたドライエッチングによ
って形成した。次にその上に減圧CVD法によって厚さ
300nmのポリシリコン膜4を堆積した。このポリシ
リコン膜4はリンを含み、シート抵抗は20Ω/□であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view showing a step of opening a polysilicon film at a bottom portion of a hole in a method of manufacturing a semiconductor device according to the present invention. After forming a 20 nm oxide film 2A on the silicon substrate 1 as shown in FIG.
m silicon nitride film 2B was formed by low pressure CVD. After that, a BPSG film 3 having a thickness of 800 nm is formed by atmospheric pressure CVD.
Formed by the method. At this time, the boron concentration in the BPSG film was 3 wt%, and the phosphorus concentration was 6 wt%. Then, after a heat treatment at 900 ° C. for 30 minutes in nitrogen, the diameter is 1.6 μm.
A hole m was formed by dry etching using a resist as a mask. Next, a polysilicon film 4 having a thickness of 300 nm was deposited thereon by a low pressure CVD method. This polysilicon film 4 contains phosphorus and has a sheet resistance of 20Ω / □.

【0009】この後本発明の特徴とする工程に入る。す
なわちポリシリコン膜4上に厚さ20nmのシリコン酸
化膜11をジクロルシランガスの熱分解による減圧CV
D法によって形成し、さらに減圧CVD法によって16
0nmのシリコン窒化膜12をその上に形成した。次に
シプレー社S−1400型ホトレジストを厚さ1.2μ
mで塗布した後、ステッパーによって80mJ/cm2
436nmの紫外光を露光し、さらに東京応化工業
(株)製のNMD−3型現像液で45秒間の現像を行う
ことによって同図に示すように穴の内部にのみホトレジ
スト膜13を残した。次に図1(b)のようにCHF3
ガスによるドライエッチを行って穴の外のシリコン窒化
膜12を除去した後穴中のホトレジスト膜13を除去後
水蒸気雰囲気中で900℃、30分の熱酸化を行い、ポ
リシリコン膜4上に約200nmのシリコン酸化膜14
を選択的に形成した。そして同図(c)のように溝中の
シリコン窒化膜12を熱リン酸によって除去し、さらに
その下のシリコン酸化膜をフッ酸とフッ化アンモニウム
の混合液で除去した後シリコン酸化膜14をマスクにし
てポリシリコン膜4の異方性ドライエッチングをHBr
とO2の混合ガスによって行うことにより穴の底面部分
のポリシリコン膜4を穴の側面に対して自己整合的に開
口することができた。本実施例では穴の中にのみホトレ
ジスト膜13を残す方法としてステッパーによる露光を
行ったが、これはエッチバック法によっても全く同様の
効果を得ることが可能である。
Thereafter, a process which is a feature of the present invention is started. That is, the silicon oxide film 11 having a thickness of 20 nm is formed on the polysilicon film 4 by decompression CV by thermal decomposition of dichlorosilane gas.
Formed by the D method, and further formed by the reduced pressure CVD method.
A 0 nm silicon nitride film 12 was formed thereon. Next, Shipley S-1400 type photoresist was applied to a thickness of 1.2 μm.
After coating with m, the film is exposed to 436 nm ultraviolet light of 80 mJ / cm 2 by a stepper, and further developed with NMD-3 type developer manufactured by Tokyo Ohka Kogyo Co., Ltd. for 45 seconds, as shown in FIG. Then, the photoresist film 13 was left only inside the hole. Next, FIG. 1 CHF 3 as (b)
The silicon nitride film 12 outside the hole is removed by performing dry etching with a gas, and then the photoresist film 13 in the hole is removed. 200 nm silicon oxide film 14
Was selectively formed. Then, as shown in FIG. 3C, the silicon nitride film 12 in the trench is removed by hot phosphoric acid, and the underlying silicon oxide film is removed by a mixed solution of hydrofluoric acid and ammonium fluoride. Anisotropic dry etching of the polysilicon film 4 is performed using HBr as a mask.
And it could be self-aligned manner opening the polysilicon film 4 on the bottom portion of the hole by making with respect to the side surface of the hole by a gas mixture of O 2. In this embodiment, the exposure by the stepper is performed as a method of leaving the photoresist film 13 only in the hole, but the same effect can be obtained by the etch-back method.

【0010】底面のポリシリコン膜4を開口後この内部
にさらにシリコン基板1と上層の配線層のコンタクトホ
ールを形成する場合、このコンタクトホールを直径0.
6μmとすると本方法では重ね合せ余裕を片側0.2μ
mとすると前述の実施例のBPSG膜の開口部の直径は
1.6μm(開口部0.6μm+ポリシリコン膜2×
0.3μm+アライメント余裕2×0.2μm)であ
る。
After the bottom polysilicon film 4 is opened, a contact hole for the silicon substrate 1 and an upper wiring layer is further formed in the polysilicon film 4.
When the thickness is 6 μm, in this method, the overlapping margin is 0.2 μm on one side.
m, the diameter of the opening of the BPSG film of the above embodiment is 1.6 μm (0.6 μm of opening + polysilicon film 2 ×
0.3 μm + alignment margin 2 × 0.2 μm).

【0011】従来のように底面にホトレジストマスクに
よるポリシリコン膜開口部を形成し、さらにその中にコ
ンタクトホールを形成する方法ならばBPSG膜の開口
部の直径は少なくとも2.0μm(開口部0.6μm+
ポリシリコン膜2×0.3μm+アライメント余裕4×
0.2μm)必要である。本発明によって大幅な専有面
積の低減が可能である。
If a polysilicon film opening is formed on the bottom surface by using a photoresist mask and a contact hole is formed in the polysilicon film as in the prior art, the diameter of the opening of the BPSG film is at least 2.0 μm (opening 0.2 mm). 6 μm +
Polysilicon film 2 x 0.3 µm + alignment margin 4 x
0.2 μm). According to the present invention, it is possible to significantly reduce the occupied area.

【0012】[0012]

【発明の効果】以上の実施例から明らかなように本発明
は、穴部を含む領域に形成されたポリシリコン膜に開口
を行う場合穴部底のポリシリコン膜を自己整合的に除去
する構成によるので、穴の側面とポリシリコン膜開口部
の重ね合せ余裕を必要とせず、最も広い開口面積を得る
ことができ、開口部専有面積の低減による集積度の向上
を図った半導体装置を提供できる。
As is apparent from the above embodiments, the present invention has a structure in which, when an opening is formed in a polysilicon film formed in a region including a hole, the polysilicon film at the bottom of the hole is removed in a self-aligned manner. Therefore, it is not necessary to have a margin for overlapping the side surface of the hole and the opening of the polysilicon film, the widest opening area can be obtained, and a semiconductor device which improves the degree of integration by reducing the area occupied by the opening can be provided. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例による半導体装置の製造方法
を説明するための工程断面図
FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

【図2】従来の半導体装置の製造方法を説明するための
工程断面図
FIG. 2 is a process cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板(半導体基板) 2A 酸化膜 2B シリコン窒化膜 3 BPSG膜 4 ポリシリコン膜 11 シリコン酸化膜 12 シリコン窒化膜 13 ホトレジスト膜(有機樹脂膜) 14 シリコン酸化膜 Reference Signs List 1 silicon substrate (semiconductor substrate) 2A oxide film 2B silicon nitride film 3 BPSG film 4 polysilicon film 11 silicon oxide film 12 silicon nitride film 13 photoresist film (organic resin film) 14 silicon oxide film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板表面のBPSG膜等の膜の所定
部に形成された穴部を含む領域にポリシリコン膜を形成
する工程と、そのポリシリコン膜の表面にシリコン酸化
膜とシリコン窒化膜を形成する工程と、前記穴部内のみ
に少なくともその穴部底面に形成されたシリコン窒化膜
を覆うようにホトレジスト等の有機樹脂膜を形成する工
程と、前記有機樹脂膜をマスクにして、少なくとも前記
穴の底面に形成されたシリコン窒化膜を残して他のシリ
コン窒化膜を除去する工程と、前記有機樹脂膜を除去し
た後前記シリコン窒化膜の除去されたポリシリコン膜上
に熱酸化でシリコン酸化膜を形成する工程と、そのシリ
コン酸化膜をマスクにして穴部底面に形成されたポリシ
リコン膜をエッチングによって自己整合的に除去する工
程とを少なくとも有することを特徴とする半導体装置の
製造方法。
A step of forming a polysilicon film in a region including a hole formed in a predetermined portion of a film such as a BPSG film on a surface of a semiconductor substrate; and forming a silicon oxide film and a silicon nitride film on the surface of the polysilicon film. Forming an organic resin film such as a photoresist so as to cover at least the silicon nitride film formed on the bottom of the hole only in the hole, and using the organic resin film as a mask, Removing the other silicon nitride film while leaving the silicon nitride film formed on the bottom surface of the hole, and thermally oxidizing the silicon oxide film on the polysilicon film from which the silicon nitride film has been removed after removing the organic resin film. At least a step of forming a film and a step of self-aligningly removing the polysilicon film formed on the bottom of the hole by etching using the silicon oxide film as a mask are described. The method of manufacturing a semiconductor device which is characterized in that.
【請求項2】穴部内のみに少なくともその穴部底面に形
成されたシリコン窒化膜を覆うようにホトレジスト等の
有機樹脂膜を形成する工程に代えて、穴部内を含む全面
にホトレジスト等の有機樹脂膜を塗布した後、その有機
樹脂膜全面をドライエッチングして前記有機樹脂膜の表
面を後退させ、前記穴部内のみに有機樹脂膜を形成する
工程としたことを特徴とする請求項1記載の半導体装置
の製造方法。
2. The method according to claim 1, wherein the step of forming an organic resin film such as a photoresist so as to cover at least the silicon nitride film formed on the bottom surface of the hole only in the hole is performed. 2. The method according to claim 1, wherein after the film is applied, the entire surface of the organic resin film is dry-etched to retreat the surface of the organic resin film, and the organic resin film is formed only in the hole. A method for manufacturing a semiconductor device.
【請求項3】穴部内のみに少なくともその穴部底面に形
成されたシリコン窒化膜を覆うようにホトレジスト等の
有機樹脂膜を形成する工程に代えて、穴部内を含む全面
にホトレジスト等の有機樹脂膜を塗布した後、その有機
樹脂膜の所定部を露光し、現像して穴部内のみに有機樹
脂膜を形成する工程としたことを特徴とする請求項1記
載の半導体装置の製造方法。
3. An organic resin film such as a photoresist is formed on the entire surface including the inside of the hole instead of forming an organic resin film such as a photoresist so as to cover at least the silicon nitride film formed on the bottom surface of the hole only in the hole. 2. The method for manufacturing a semiconductor device according to claim 1, wherein after the film is applied, a predetermined portion of the organic resin film is exposed and developed to form an organic resin film only in the hole.
JP31207291A 1991-11-27 1991-11-27 Method for manufacturing semiconductor device Expired - Fee Related JP2874071B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31207291A JP2874071B2 (en) 1991-11-27 1991-11-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31207291A JP2874071B2 (en) 1991-11-27 1991-11-27 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05152242A JPH05152242A (en) 1993-06-18
JP2874071B2 true JP2874071B2 (en) 1999-03-24

Family

ID=18024897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31207291A Expired - Fee Related JP2874071B2 (en) 1991-11-27 1991-11-27 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2874071B2 (en)

Also Published As

Publication number Publication date
JPH05152242A (en) 1993-06-18

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