JP2870261B2 - Scanning circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning circuit mainly used for a peripheral driving circuit such as a liquid crystal display, a contact image sensor and a liquid crystal shutter.

[0002]

2. Description of the Related Art There is a technique for integrally manufacturing a thin film drive circuit for the purpose of miniaturization, cost reduction, and high reliability of a liquid crystal display, a contact image sensor, a liquid crystal shutter, and the like. This is caused by the fact that the number of connection terminals and the number of external drive ICs can be significantly reduced by installing a peripheral drive circuit on the same substrate as the pixel electrodes, and the limitation of a large-area, high-density bonding process. It is based on the concept of solving reliability problems.

A scanning circuit composed of a shift register and an output buffer is an important component of the thin film driving circuit as a circuit for scanning a block switch of a vertical driving circuit or a horizontal scanning circuit in an active matrix liquid crystal display, for example.

FIG. 4 is a diagram showing a (2N-1) -th stage and a (2N) -th stage of a conventional CMOS static scanning circuit using a clocked inverter. FIG. 7 is a diagram showing symbols and configurations of the clocked inverter. Clocked inverter 101 shown in FIG. 7, the clock signal phi is at the high level, when the inverted clock signal phi _r of the clock signal phi is at low level, and outputs the reflected input signal signal. Conversely, the clock signal φ is low and the clock signal φ
_{While i} is at the high level, the output maintains the previous state regardless of the input signal. In the scanning circuit of FIG. 4, the shift register 401 can transmit the input signal for a certain period by the clock signals φ and φ _i and sequentially transfer the signals to the next-stage shift register. Is output as a scanning pulse signal through the output buffer circuit 103.

FIG. 5 is a diagram showing a (2N-1) -th stage and a (2N) -th stage of a conventional CMOS dynamic scanning circuit using a clocked inverter. In a dynamic circuit, there is a state in which a signal is held for a half period of a clock cycle. Therefore, a stable operation as in the static circuit shown in FIG. 4 cannot be expected, but the circuit is simpler because the feedback circuit is eliminated. Become.

FIG. 6 is a timing chart of the conventional scanning circuit shown in FIGS. 4 and 5. in this case,
The (2N-1) -th and (2N) -th scanning pulse signals are output at the same timing as the outputs A and B of the shift register 401, and the scanning cycle T is equal to the clock cycle.

[0007]

As image input / output devices such as a liquid crystal display, a contact image sensor, and a liquid crystal shutter become larger and longer, it is difficult to form a defect-free peripheral drive circuit by using current process technology. It is very difficult. In particular, in a conventional scanning circuit in which shift registers are connected in series, if at least one defect exists in the middle stage, the scanning signal cannot be transferred normally after that stage, and in a two-dimensional image device such as a liquid crystal display. Appears as a surface defect. This occurs even when there is no defect in the pixel array section, so that a defect in the scanning circuit is a major cause of lowering the device yield.

[0008] Further, as the resolution of the image input / output device increases, a higher-speed scanning circuit is required. The speeding up of the scanning circuit can be achieved mainly by improving the mobility of the thin film transistor or reducing the gate length of the transistor, but in that case, a major problem arises in that the transistor manufacturing process needs to be changed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-yield and high-speed scanning circuit for eliminating at least surface defects of an image device and a method of driving the same, in order to solve the above problems.

[0010]

SUMMARY OF THE INVENTION In a CMOS static scanning circuit formed by integrating transistors,
A clocked inverter which uses a signal sent from a preceding stage as an input signal, is controlled by two clock signals having a phase relationship opposite to each other, and uses an input signal to the next stage as an output signal; A feedback circuit controlled by the two clock signals, and an output signal of the feedback circuit as an input signal, and an output signal of an N-th stage of the scanning circuit is N ( (N is a positive integer) The odd-numbered stages are output so that the clocked inverter of the (N + 1) th stage outputs a signal delayed by a half cycle of the clock signal from the timing of transferring the signal to the (N + 1) th stage of the clocked inverter. Eyes or even
Depending on the number of stages, which of the two clock signals
Output buffer times controlled by either clock signal
A scanning circuit, characterized in that consists of a road, in the scanning circuit, the output buffer circuit of the odd-
An inverter using an output signal of the feedback circuit as an input signal, an output signal of the inverter, and a NOR signal inputting a clock signal input to an n-type MOS transistor forming the odd-numbered clocked inverter Circuit, and a non-inverting buffer circuit that receives an output signal of the NOR circuit as an input signal, and the output buffer circuit of an even-numbered stage includes an output signal of the feedback circuit and the clocked inverter of an even-numbered stage. And a non-inverting buffer circuit having a clock signal input to an n-type MOS transistor constituting the input circuit as an input signal and a non-inverting buffer circuit having an output signal of the NOR circuit as an input signal. In a CMOS dynamic scanning circuit formed by integrating circuits and transistors, a The Kita signal as an input signal, and is controlled by two clock signals in anti-phase relation to each other,
And a clocked inverter having an output signal as an input signal to the next stage, and an output signal of the clocked inverter as an input signal, and an output signal of an N-th stage of the scanning circuit,
The clocked inverter of the Nth (N is a positive integer) stage is output at a timing delayed by a half cycle of the clock signal from the timing of transferring a signal to the (N + 1) th stage of the clocked inverter, Odd or even
Which one of the two clock signals is used,
An output buffer circuit controlled by one of the clock signals;
In the scanning circuit, the output buffer circuit of the odd-numbered stage forms an output signal of the clocked inverter and the clocked inverter of the odd-numbered stage. NOR using clock signal input to n-type MOS transistor as input signal
Circuit, and a non-inverting buffer circuit using an output signal of the NOR circuit as an input signal, and the output buffer circuit of an even-numbered stage includes an inverter using an output signal of the feedback circuit as an input signal, and an inverter using the inverter. , And a clock signal input to the n-type MOS transistor constituting the clocked inverter of the even-numbered stage as an input signal, and a non-inverting circuit using the output signal of the NOR circuit as an input signal. A scanning circuit comprising a buffer circuit.

[0011]

The yield of the peripheral drive circuit decreases significantly in accordance with the exponential function as the circuit area increases. In the scanning circuit of the present invention, since the portion for delay-transferring the signal from the preceding stage to the next stage is composed of only one clocked inverter, the portion of the scanning circuit is compared with the conventional scanning circuit composed of a shift register. The area can be significantly reduced. Therefore, the probability that the signal can be delayed and transferred to the last stage is significantly improved. That is, it is possible to significantly reduce the defects of the scanning circuit that appear as surface defects.

Further, in the method for driving a scanning circuit according to the present invention,
When the scanning period is T, the period of the clock signal is (2 ×
T) and the clock cycle T required conventionally has a margin twice as fast as the clock cycle T. Further, in this driving method in which the clock signal is supplied as an enable signal to the output buffer circuit, if the output signal of the clocked inverter or the feedback circuit rises within half a cycle of the clock signal, the internal signal delay of the clocked inverter or the feedback circuit is delayed. Does not appear in the scan pulse signal. As described above, the speed of the scanning circuit can be increased.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the scanning circuit and the driving method of the present invention will be described below in detail.

FIG. 1 is a diagram showing an embodiment of the scanning circuit of the present invention. In this embodiment, the scanning circuit is realized by a CMOS static circuit, and the (2N-1) -th and (2N) -th stages are shown in the drawing (where N is a natural number). This scanning circuit as shown in FIG., The clock signal phi signals from the preceding stage, a clocked inverter 101 for inverting and delaying the transfer to the next stage by phi _i, prevents the decay of the amplitude of the pulse signal to continue to delay transfer a feedback circuit 102 for, by the clock signal phi is at odd-numbered stages, and a output buffer circuit 103 which is controlled by the clock signal phi _i in even-numbered stage. The odd-numbered output buffer circuit includes an inverter for inverting the output of the feedback circuit, a NOR circuit receiving the output signal of the inverter and the clock signal φ, and a non-inverting buffer receiving the output of the NOR circuit. It is composed of On the other hand, consists of the output buffer circuit of the even-numbered stage and the NOR circuit for receiving the output signal and the clock signal phi _i of the feedback circuit 102, and forward buffer circuit which receives the output of the NOR circuit. With the configuration described above, the circuit area of the portion for delay-transferring the pulse signal from the previous stage to the next stage can be reduced to 1/5 of that of the conventional scanning circuit shown in FIG.

FIG. 2 is a timing chart of the main scanning circuit shown in FIG. In the driving method of the present scanning circuit, the period of the clock signal is 2 × T with respect to the scanning period T, whereby the scanning pulse signal having the same period is driven at a frequency which is の of the driving frequency conventionally used. be able to. The (2N-1) -th and (2N) -th scanning pulse signals are output at a timing delayed by T from the timing at which the output signal of the feedback circuit 102 is output. If the rise and fall times are within T, the clocked inverter 101 and the feedback circuit 10
2 does not affect the delay of the scan pulse signal.

A 2000-stage CMOS static scanning circuit employing the scanning circuit of the present invention was manufactured by actually integrating polycrystalline silicon thin film transistors on a glass substrate. As a result, the probability that the pulse signal is normally transferred to at least the final stage has been improved from 40% of the related art to 80%.

Next, a second embodiment of the scanning circuit of the present invention will be described.

FIG. 3 is a diagram showing an embodiment of the scanning circuit of the present invention. In this embodiment, the scanning circuit is realized by a CMOS dynamic circuit, and the (2N-1) -th and (2N) -th stages are shown in the figure (N is a natural number). The difference from the first embodiment is that the feedback circuit 102
Are not used, and the configuration of the output buffer circuits of the odd-numbered and even-numbered stages is reversed. This scanning circuit as shown in FIG., A signal from the preceding stage clock signal phi, the clocked inverter 101 for delaying transfer inverted to the next stage by phi _i, the clock signal phi is at odd-numbered stage, even- And the output buffer circuit 103 controlled by the clock signal φ _i . With this configuration, the circuit area of the portion for delay-transferring the pulse signal from the previous stage to the next stage can be reduced to (１ ／) as compared with the conventional scanning circuit shown in FIG.

The driving method and timing chart of the scanning circuit of the present embodiment are the same as those of the first embodiment. The (2N-1) -th and (2N) -th scanning pulse signals are output at a timing delayed by T from the timing at which the output signal of the clocked inverter 101 is output. If the rise and fall times are within T, the internal delay generated by the clocked inverter 101 does not affect the delay of the scan pulse signal.

A 2000-stage CMOS dynamic scanning circuit employing the scanning circuit of the present invention was manufactured by actually integrating polycrystalline silicon thin film transistors on a glass substrate. As a result, the probability that the pulse signal is normally transferred to at least the final stage has been improved from 60% of the related art to 80%.

[0021]

As described above, when the scanning circuit of the present invention is applied, the circuit area of the portion for transferring the pulse signal from the previous stage to the next stage can be reduced to (従 来) or (１ ／) of the conventional circuit area.
Therefore, at least surface defects of the two-dimensional image device caused by defects of the driving circuit can be significantly reduced. That is, the scanning circuit of the present invention is extremely useful for improving the yield of the liquid crystal display, the contact image sensor, the liquid crystal shutter, and the like. The driving method of the scanning circuit according to the present invention can obtain the same scanning frequency at half the frequency of the conventional driving frequency, so that it is extremely useful as a driving method capable of coping with higher resolution of an image input / output device. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the scanning circuit of the present invention.

FIG. 2 is a diagram showing a timing chart of the scanning circuit of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the scanning circuit of the present invention.

FIG. 4 is a diagram illustrating an example of a conventional scanning circuit.

FIG. 5 is a diagram illustrating an example of a conventional scanning circuit.

FIG. 6 is a diagram showing a timing chart of a conventional scanning circuit.

FIG. 7 is a diagram showing symbols and configurations of a clocked inverter.

[Explanation of symbols]

 Reference Signs List 101 clocked inverter 102 feedback circuit 103 output buffer circuit 401 1-bit shift register

Claims (4)

(57) [Claims] 1. A CM formed by integrating transistors
In the OS static type scanning circuit, a clock signal which is controlled by two clock signals having a phase relationship opposite to each other as a signal sent from a preceding stage as an input signal, and an input signal to the next stage as an output signal. An inverter, an output signal of the clocked inverter as an input signal, a feedback circuit controlled by the two clock signals, an output signal of the feedback circuit as an input signal, and an N-th stage of the scanning circuit. Output signal is N (N
Is a positive integer) and the clocked inverter at the stage is (N +
1) The odd-numbered stage or the even-numbered stage so that the signal is output at a timing delayed by a half cycle of the clock signal from the timing of transferring the signal to the clocked inverter in the stage.
One of the two clock signals
And an output buffer circuit controlled by a clock signal
Scanning circuit, characterized in that it is. 2. The scanning circuit according to claim 1, wherein the odd-numbered output buffer circuit comprises: an inverter having an output signal of the feedback circuit as an input signal; an output signal of the inverter; An NOR circuit comprising a NOR circuit having a clock signal inputted to an n-type MOS transistor constituting the clocked inverter as an input signal, and a non-inverting buffer circuit having an output signal of the NOR circuit as an input signal; A NOR circuit that receives, as input signals, an output signal of the feedback circuit and a clock signal input to an n-type MOS transistor included in the clocked inverter of an even-numbered stage; A scanning circuit comprising: a non-inverting buffer circuit that receives an output signal of the NOR circuit as an input signal; 3. A CM formed by integrating transistors.
In the OS dynamic type scanning circuit, a clock signal which is controlled by two clock signals having a phase relationship opposite to each other as a signal sent from the preceding stage as an input signal, and an input signal to the next stage as an output signal. An output signal of the inverter and the clocked inverter is an input signal, and an output signal of an N-th stage of the scanning circuit is N (N is a positive integer)
The odd-numbered or even-numbered stage is output so that the clocked inverter of the stage is output at a timing delayed by a half cycle of the clock signal from the timing of transferring the signal to the (N + 1) th stage of the clocked inverter. According to the above
One of the two clock signals
A scanning circuit comprising: an output buffer circuit controlled by a signal. 4. The scanning circuit according to claim 3, wherein the odd-numbered output buffer circuit includes an output signal of the clocked inverter and an n-type MOS constituting the odd-numbered clocked inverter. A NOR circuit having a clock signal input to a transistor as an input signal;
A non-inverting buffer circuit using an output signal of an OR circuit as an input signal, and the output buffer circuit of an even-numbered stage includes an inverter using an output signal of the feedback circuit as an input signal, and an output signal of the inverter. , The n-type MO constituting the clocked inverter of the even-numbered stage
A scanning circuit comprising: a NOR circuit using a clock signal input to an S transistor as an input signal; and a non-inverting buffer circuit using an output signal of the NOR circuit as an input signal.