JP2864514B2 - Image reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention subdivides an original image into pixels by a one-dimensional image sensor in which a plurality of imaging chips are arranged in a main scanning direction and reads the original image to correspond to each pixel. The present invention relates to an image reading device that outputs an image signal, and more particularly, to quantization of a one-dimensional image sensor output.

[Conventional technology]

2. Description of the Related Art Conventionally, a still image such as a document is read by an image sensor as an image input unit of a computer or a document image reading unit of a digital copying machine or a facsimile, and the obtained image data is subjected to various image processing. An image reading device that outputs an image signal as an image signal is used.

As an optical system of such an image reading apparatus, an equal-magnification type in which a light receiving area of each pixel is large and high sensitivity is generally used as compared with a reduction type.

The same-magnification type optical system usually includes a light source for certification, a rod lens array (erecting equal-magnification lens) that collects the reflected light from the manuscript, and a CCD (charge-coupled device), etc., below the platen glass. A one-dimensional image sensor (line sensor) in which solid-state imaging devices are arranged in the main scanning direction (horizontal direction) is moved in the sub-scanning direction (vertical direction).

The photoelectric conversion output of the solid-state imaging device, which is obtained by subdividing the original image into pixels and read, is differentially amplified with reference to the analog value (black level) in the light-off state of the light source sampled and held in one line cycle, -Quantized by digital (A / D) conversion means, and converted into image data according to the intensity of reflected light at each pixel.

Various image processing is performed on the image data, and an image signal to be transmitted to an image forming apparatus such as a printer is generated.

Although the solid-state imaging chip has a large number of imaging elements formed in a semiconductor wafer at one time, the number of elements that can be made into one chip is limited due to the limitation due to the size of the semiconductor wafer.

For this reason, in an image reading device that reads A4 or A3 size images, the line sensor is composed of a plurality of solid-state imaging chips, and these solid-state imaging chips are usually driven simultaneously to shorten the reading time. Each of the solid-state imaging chips reads a predetermined width of one line.

[Problems to be solved by the invention]

When driving a plurality of solid-state imaging chips at the same time, black level sampling and A / D conversion are performed for each solid-state imaging chip. The level is fixed to the black level, and each A / A
When the input reference level of the D conversion means fluctuates, level adjustment is performed by offset adjustment of the differential amplifier.

However, offset adjustment requires skill and it is difficult to maintain a certain accuracy, and the reference level varies depending on the use environment such as temperature drift.

For this reason, image data correction processing such as pseudo correction for uniforming the contrast of one line cannot be performed correctly, and the reproducibility of an image formed based on an image signal output from the image reading device is impaired. Problem.

In particular, in the case of reading a color image, there is a problem that an error occurs in white balance correction for adjusting a color tone and an image of a color different from that of a document is formed.

The present invention has been made in view of the above-described problems, and provides an image reading apparatus capable of equalizing a reference level of quantization of photoelectric conversion signals output from a plurality of solid-state imaging chips and improving fidelity of image reproduction. It is intended to be.

[Means for solving the problem]

In order to solve the above-mentioned problems, the invention according to claim 1 divides an original image into pixels and reads each pixel with a plurality of colors separated by an image sensor in which a plurality of imaging chips are arranged, and reads each pixel with a plurality of colors. In an image reading device that outputs a corresponding image signal, an image in which an original image is subdivided and read by an image sensor in which a plurality of imaging chips are arranged, and an image that outputs a plurality of color-separated image signals corresponding to each pixel is output. In the reading device, a clamp unit that sets a reference level of a photoelectric conversion signal from each imaging chip, an A / D conversion unit that quantizes an output signal from the clamp unit to generate image data, and reads a reference color image, A / D conversion reference given to the A / D conversion means in accordance with reference image data based on a photoelectric conversion signal of a color in a wavelength region having the largest relative luminosity of the plurality of colors. Constructed and a reference potential setting means for performing position adjustment.

According to a second aspect of the present invention, an original image is subdivided into pixels by an image sensor having a plurality of imaging chips arranged, and each pixel is separated into three colors of R, G, and B, which are three primary colors, and read. In an image reading apparatus that outputs an image signal corresponding to each pixel, an A / D conversion unit that quantizes a photoelectric conversion signal from each imaging chip to generate image data, reads a reference color image, and reads a G color A reference potential setting unit configured to adjust a reference potential of A / D conversion given to the A / D conversion unit in accordance with reference image data based on the photoelectric conversion signal.

(Operation)

The clamp means sets a reference level of the amplitude of the photoelectric conversion signal output from the imaging chip of the image sensor.

The A / D conversion unit quantizes the output signal from the clamp unit to generate image data corresponding to pixels of the original image.

The reference potential setting means adjusts the reference potential of A / D conversion to be applied to the A / D conversion means according to the reference image data obtained by reading the reference color image. At that time, the reference potential is adjusted according to the reference image data based on the photoelectric conversion signal of the color in the wavelength region where the relative luminosity factor is the largest. When each pixel is read after being color-divided into R, G, and B, which are the three primary colors of the additive system,
The reference potential is adjusted in accordance with the reference image data based on the G color photoelectric conversion signal.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a front sectional view showing a schematic configuration of the digital copying machine A.

The digital copying machine A performs various signal processings on an image signal obtained by reading an image of a document, and outputs an image signal as an image reader unit IR, and an electrophotographic method based on the image signal sent from the image reader unit IR. It comprises a laser printer section LP for forming a color image.

In the image reader section IR, the original placed on the original glass 18 is exposed to an R (red), G (green), and B (blue) color by an exposure lamp 17, a rod lens array 15, and an image sensor 11. These are read as color signals of three primary colors. The R, G, and B color signals are converted into four color signals obtained by adding Bk (black) to three subtractive colors of Y (yellow), M (magenta), and C (cyan) by a color correction circuit 105 described later. After being converted and subjected to various kinds of signal processing, it is sent as an image signal to a laser printer unit LP having a laser optical system 13.

The digital copying machine A of this embodiment does not have an image memory for three colors, and the slider 14 scans an original for each color image copy, and based on this scans the C, M, Y, and Bk The signal is sent to the laser printer unit LP.

The laser optical system 13 of the laser printer unit LP includes a scanning polygon mirror 13a, an Fθ lens 13b, a reflection mirror 51, and the like, and transmits an image forming laser beam controlled by C, M, Y, and Bk signals to the photosensitive drum 1. And exposure is performed.

The photosensitive drum 1 is driven to rotate counterclockwise. The surface of the photosensitive drum 1 is provided with an organic photosensitive member in which a charge generating layer and a charge transporting layer are laminated on a conductive substrate, and has a high sensitivity particularly around a laser emission wavelength of 780 nm.

Around the photosensitive drum 1, a drum cleaner 4, a toner collecting roll 5, an eraser lamp 3, and a charging charger 2 are provided, and four types of developing devices are provided.
The first developing device 6 uses Y (yellow) toner, the second developing device 7 uses M (magenta) toner, the third developing device 8 uses C (cyan) toner, and the fourth developing device Numeral 9 supplies black toner, and these toners are negatively charged. To supply toner, the toner of each color stored in the toner hopper 10 is piped (not shown) to each of the developing devices 6, 7, 8, and 9 as appropriate based on a supply signal.
This is done by transport through

Transfer sheet (copy paper) such as plain paper and OHP film
Are loaded on the paper feed cassettes 19a and 19b, and are fed one by one by the paper feed rollers 52a and 52b. Then, when the leading end comes into contact with the registration roller 20, the transfer sheet is temporarily stopped to take the following timing, and at the same time, skew correction is performed. Reference numeral 21 denotes a paper sensor used for this purpose. A transfer drum 36 is driven to rotate clockwise. The transfer drum 36 has a plurality of tip chucking claws 38. This tip chucking claw is 38
Chucks the leading end of the copy paper sent in a timely manner by the registration roller 20.

The frame 22 that supports the transfer drum 36 is rotatably supported about a pivot 41 and is urged counterclockwise by a spring 40. As a result, the transfer drum 36 comes into pressure contact with the positioning roller 39 disposed on the photosensitive drum 1 side, and the distance between the transfer drum 36 and the photosensitive drum 1 is kept constant.

On the inner peripheral side of the transfer drum 36, a suction charger 24, a transfer charger 25, and a first charge removing charger 26 are provided. On the outer peripheral side of the transfer drum 36, a ground electrode 23 is disposed opposite to the adsorption charger 24, and a second discharger 27 is disposed opposite to the first discharger 26. Further, a jam detecting means 90 for detecting the occurrence of separation jam of the transfer sheet is provided. It is preferable to use a reflection type photo sensor as the jam detecting means 90.

The suction charger 24 performs a corona discharge of a negative charge to negatively charge the dielectric screen 55 of the transfer drum 36, and is sent in a state where the front end is chucked to the transfer drum 36 by the front end chucking claw 38. The copy paper is electrostatically attracted to the dielectric screen 55. At this time, the ground electrode 23 comes into contact with the copy paper, and the electrostatic attraction of the copy paper onto the transfer drum 36 is ensured except for the influence of the suction charger 24 on the copy paper.

The transfer charger 25 is disposed in the transfer section S where the photosensitive drum 1 and the transfer drum 36 are closest to each other, and transfers the toner image on the photosensitive drum 1 to the transfer drum 36 by corona discharge of positive charge.
The electrostatic transfer is performed on the upper transfer sheet.

An AC voltage is applied to the first charge-eliminating charger 26 and the second charge-eliminating charger 27, and a set of these forms a charge-eliminating charger 68. The first charge removal charger 26 mainly removes electricity from the dielectric screen 55 to reduce the electrostatic attraction force of the transfer sheet,
The second charge removing charger 27 mainly removes the charge on the surface of the transfer sheet at the time of separation, and prevents discharge due to separation and scattering of an image.

The copy paper separated from the transfer drum 36 by the separation claw 28 is sent to the fixing device 30 by sheet discharging means T such as a conveyor 29, where it is thermally fixed, and then discharged to the discharge tray 32. 44 is a position detection sensor for the transfer drum.
It detects 36 rotation reference positions.

FIG. 3 is a perspective view showing an optical system of the image reader section IR,
FIG. 4 is a plan view of the image sensor 11, FIG. 5 is an enlarged view schematically showing the light receiving portions of the CCD sensor chips 11a and 11b in FIG. 4, and FIG. 6 is a block diagram showing a driving circuit of the CCD sensor chip 11a. FIG. 7 is a time chart showing the driving operation of the CCD sensor chips 11a to 11e, and FIG. 8 is a time chart showing the output of each of the CCD sensor chips 11a to 11e.

The original D placed on the original platen glass 18 is line-scanned in the sub-scanning direction by a slider 14 having an image sensor 11, and is a 1 × optical system having an exposure lamp 17, a rod lens array 15, and the image sensor 11. By R
(Red), G (Green), B (Blue) Additive System 3
It is separated into primary colors and read. Rod lens array 15
Has an interference film filter that blocks infrared light (not shown)
Is provided.

As shown in FIG. 4, the image sensor 11 includes five contact-type CCD sensor chips 11a to 11e so as to be continuous in the horizontal direction (main scanning direction) and in the vertical direction (sub scanning direction). They are arranged in a zigzag pattern alternately at a constant pitch. Since there is a constant pitch in the sub-scanning direction, output signals from the CCD sensor chips 11a, 11c, and 11e behind in the sub-scanning direction are delayed, but this is caused by the line shift gates of the CCD sensor chips 11a to 11e. By setting the timings of the pulse signals φV1 to φV7 to be applied to G1 to G7 as shown in FIG. 7, the output signals OSb and OSd from the front CCD sensor chips 11b and 11d are corrected by delaying by four lines.

Each CCD sensor chip 11a to 11e has its end
As shown enlarged in the figure, one size is 62.5 μm (d
.. Are arranged in one row.

Each element 12 is divided into three, and one divided area has three primary colors RGB.
A spectral filter is provided so as to receive one color of light.

Such one element 12 corresponds to one pixel obtained by subdividing the original image, and the photoelectric conversion output of one element 12 represents the reflected light intensity of one color of one pixel.

FIG. 9 is a block diagram of the image processing apparatus B incorporated in the image reader section IR.

In the image sensor 11, in order to increase the reading speed in the main scanning direction, five CCD sensor chips 11a to 11e are simultaneously driven, and each of the CCD sensor chips 11a to 11e has a total of 2 RGB as shown in FIG.
Effective read pixel signals for 928 pixels are serially output in order.

Simultaneous (parallel) from five CCD sensor chips 11a to 11e
Each of the five systems of photoelectric conversion outputs serially output to a line memory 111, a CPU (central processing unit) 112, and a ROM 11
Each of the following image processing circuits 101 to 110 constituting the image processing apparatus B together with 3 receives signal processing.

First, the data is quantized by a digitization processing circuit 101 having a sample hold circuit and an A / D converter, converted into 8-bit (256 gradation) digital data, and separated into image data of each color by a latch circuit. The signal is input to the channel synthesis circuit 102.

The five-channel synthesizing circuit 102 temporarily stores image data for each of two lines in a total of 15 (3 × 5) first-in first-out memories for each chip and each color, and sequentially selects image data from each chip in a one-line cycle. Then, a serial image signal corresponding to the pixel arrangement (reading scan order) is generated.

The image data of each color simultaneously transmitted as these serial image signals is converted into a white balance correction circuit 10 so that a correct color image can be formed in the laser printer section.
In step 3, the relative ratio between the colors is adjusted and standardized.

Next, the shading correction circuit 104 controls the exposure lamp 17
A correction corresponding to the orientation distribution (light quantity unevenness) in the main scanning direction and the sensitivity difference between the respective elements 12 is performed, and the data signal proportional to the reflected light intensity is taken into consideration in the reading range of the document D. The data is logarithmically converted in accordance with the visual characteristics, and is converted into a density data signal proportional to the density of the document D.

In the color correction circuit 105, as described above, masking processing Bk (black) for generating density data corresponding to the three primary colors Y, M, and C of the printing toner from the density data for each of the RGB colors as described above.
BP processing (black plate generation) that generates density data corresponding to
UCR processing (under color removal) and mono-color conversion processing are performed, and the gamma correction circuit 106 designates a background removal processing for forming a clear image with enhanced overall contrast, and is designated by an operation key (not shown). A density adjustment process for forming a density image is performed.

The color editing circuit 107 performs three types of color image editing processing: negative / bodied inversion, color change (color change), and paint (filling).

In addition, the scaling / editing processing circuit 108 controls the output timing and output of the density data signal to form an enlarged or reduced scaled image and an edited image such as movement or mirror inversion by a thinning method or an interpolation method. A process for changing the order or the scanning speed in the sub-scanning direction is performed. The MTF correction circuit 109 performs an edge emphasis process that eliminates smoothing edge loss that prevents the occurrence of moire fringes.

As described above, the density data D97 to 9
“0” is subjected to binarization processing by an area gradation method in a gradation reproduction circuit 110, and sent to a laser printer unit LP as image signals VIDEO4-0.

The CPU 112 controls each image processing and the operation of the slider 14, and receives various keys on an operation panel provided on the upper surface of the digital copying machine A, an editor (not shown) for specifying an area for color editing, or a sensor from each unit. Serial communication is performed with a host CPU (not shown) that controls signal input and operation of the laser printer unit LP. The line memory 111 is used for temporarily storing image data at a specific processing stage.
, A program and various data are read.

Hereinafter, each image processing will be described in detail in the order of signal transmission. In the following description, a, b, c, d, and e used as symbols indicate the correspondence with the CCD sensor chips 11a, 11b, 11c, 11d, and 11e, respectively, and include R, G, B, Y, M, and C. , Bk indicate the correspondence with the above-mentioned respective colors. In addition, those corresponding to a plurality of chips or colors may be collectively described in parentheses.

1 (a) to 1 (c) are block diagrams of the digitization processing circuit 101, FIG. 10 is a signal waveform diagram showing a sample and hold operation for an effective pixel signal, and FIG. 11 is a diagram showing an A / D conversion operation. It is a signal waveform diagram. In these figures, since the circuit configuration of the parts corresponding to the respective CCD sensor chips 11a to 11e is the same, only the part corresponding to the CCD sensor chip 11a is shown.

As shown in FIG. 10, in synchronization with the read clock signal RS
Photoelectric conversion signal OSa output from CCD sensor chip 11a
Is an analog signal that includes reset noise and is displaced in the negative direction according to the intensity of light reflected from the document D with reference to an offset potential of 5 to 6 volts.

To remove the reset noise and extract pixel information,
The first sample-hold circuit 121 in FIG. 1A starts sampling the photoelectric conversion signal OSa at the rising timing of the sample-hold signal SCLK1, and holds the potential at the falling timing.

The second sample-and-hold circuit 122 samples a light-shielded pixel signal (see FIG. 8) output from the light-shielded element 12 according to the signal SMPK for each line, and sets the potential VBa to a black level. Hold.

The output OHa of the first sample and hold circuit 121 is
3 is differentially amplified with reference to the black level given by the second sample-and-hold circuit 122, and pixel information of each color corresponding to one pixel in the order of G, B, R
Output as a.

The pixel signal ASa is sent to the clamp unit 126 via the low-pass filter unit 124 and the gain amplifying unit 125 as shown in FIG. The low-pass filter unit 124
The clock noise superimposed by the hold operation is
The gain is removed from the ASa, and the gain amplifying section 125 compensates for the signal loss caused by the low-pass filter section 124. Upon input to the gain amplifier 125, a DC component is removed from the pixel signal ASa by the coupling capacitor 125a.

The clamp unit 126 includes a transistor 130 and a resistor 131 that constitute a buffer stage, a capacitor 135 for clamping, a resistor 133 and a Zener diode 134 for setting a clamp potential, and an analog switch 132 that performs an opening / closing operation according to a signal SMPK. .

As described above, the signal SMPK is “H” during the black level sampling period performed at the initial stage of one-line scanning,
At this time, the analog switch 132 is closed, and the potential of the output terminal 135a of the clamp capacitor 135 becomes the clamp potential V1 determined by the breakdown voltage of the Zener diode 134.
(≒ 1 volt). Therefore, the signal SMPK is “L”
Is a signal that changes with the clamp potential V1 as the lowest potential (see FIG. 11). The pixel signal ACa thus clamped passes through a buffer section 127 composed of an emitter follower circuit, and the pixel signal ACa shown in FIG.
It is applied to the analog input terminal AIN of the / D converter 140.

The A / D converter 140 receives the clock signal SCLK2 as shown in FIG.
, The pixel signal ACa is quantized by comparing the pixel signal ACa between the voltages applied to the lower reference terminal −REF and the upper reference terminal + REF, respectively, and the minimum value “0” to the maximum value “255” is obtained. 8-bit (256 gradation) image data DSa7 ~
The converted image data DSa7-0 are converted to image data RaD17-10, GaD17-10, and BaD1 corresponding to the respective colors of R, G, and B by a color separation circuit 144 that performs a two-stage latch operation.
The signal is separated into 7 to 10 and sent to the subsequent 5-channel synthesis circuit 102.

The lower reference terminal −REF of the A / D converter 140 is connected to the D / A converter 14.
The lower reference potential LVref generated based on the lower reference data LREF7 to LREF0 at 1 is given, and D / D
The upper reference potential HVref generated by the A converter 142 based on the upper reference data HREF7 to HREF0 is given, and both the D / A converters 141 and 142 receive the negative reference voltage from the reference voltage generator 143. The voltage Vref is applied.

The D / A converters 141 and 142 generate the lower reference potential LVref or the upper reference potential HVref by the calculation represented by the following color (1).

Vo = (x / 255) × | Vref | (1) where Vo is LVref or HVref, and x is LREF7-0 or HREF7.
０0.

FIG. 12 is a flowchart for setting a reference potential for A / D conversion controlled by the CPU 112. This subroutine is executed immediately after the power of the digital copying machine A is turned on.

First, in step # 91, initial setting of the upper reference data HRBF7-0 is performed. As the setting value, a value around "251" close to the maximum value is selected.

Subsequently, in step # 92, initialization is performed on the lower reference data LREF7-0 so that the lower reference potential LVref is slightly lower than the clamp potential V1.

Next, in step # 93, the reference white plate 16 (see FIG. 3) with the exposure lamp 17 turned off at the standby position of the slider 14 (see FIG. 3)
Is read, and in step # 94, G image data GaD17 which is image information of a wavelength region having the highest relative luminous efficiency among the three colors.
Are stored in the line memory 111.

In step # 95, it is determined whether or not the image data GaD17 to GaD17 is the minimum value "0". If NO, the lower reference data L is raised in step # 96 to raise the lower reference potential LVref.
REF7 to REF0 are reset and the process returns to step # 93. If YES in step # 95, it means that the setting of the lower reference potential LVref for the CCD sensor chip 11a has been completed, so that these processes are performed on the other CCD sensor chips 11b to 11e.
To the lower reference data L for each A / D conversion.
Set REF7-0. When the setting of all the chips 11a to 11e is completed (step # 97), the process proceeds to step # 98, and the setting process of the upper reference potential HVref is started.

In step # 98, the exposure lamp 17 is turned on to read the reference white plate 16, and in step # 99, the image data GaDs 17 to 10 are read.
Is stored in the line memory 111.

Next, in step # 100, each CCD sensor chip 11
The image data G (a, b, c, d,
e) It is determined whether or not the average values of D17 to D17 for one line are equal.

If NO in step # 100, the setting of the upper reference data HREF7-0 is changed in step # 101, and the process returns to step # 98.

If YES in step # 100, it means that the uniformization of the reference level of the A / D conversion performed for each of the CCD sensor chips 11a to 11e has been completed. Return to the main routine for controlling the operation.

FIG. 13 is a block diagram of the 5-channel synthesis circuit 102, and FIG.
FIG. 4 is a time chart showing the operation of the 5-channel combining circuit 102.

The five-channel synthesizing circuit 102 includes a CCD sensor chip 11 in the digitizing processing circuit 101 to facilitate the subsequent processing.
The image data (R, G,
B) aD17-10 (R, G, B) eD17-10 are synthesized and image data RD27-20, GD27-20, BD27 that are serially output in accordance with the pixel arrangement for one line for each color. Generate ~ 20. Since the circuit configuration for each color is the same,
FIG. 13 shows only a portion corresponding to R in the three colors.

Image data R output from the digitization processing circuit 101
(A, b, c, d, e) D17 to D17 are temporarily stored in first-in first-out memories 150a to 150e which perform a write operation in accordance with a write enable signal ▼. The write enable signal ▼ is a pulse of one line cycle, which is the same as the horizontal synchronization signal TG as a reference of one line cycle, but the write reset enable signal ▼ for resetting the write address to 0 has a two line cycle. Therefore, each first-in first-out memory 150a-150e has two
Line image data R (a, b, c, d, e) D17-1
0 is stored.

The first-in first-out memories 150a to 150e can perform the write operation and the read operation independently and simultaneously. The read operation depends on each read enable signal ▲ ▼ ~ ▲
Is performed during the active (active low) period, and the first-in first-out memories 150a to 150e are sequentially controlled to be in a read operation state. The read reset enable signal 信号 for resetting the read address to 0 becomes active with a delay of one line cycle from the signal ▼. As a result, the write operation of the second line and the read operation of the first line are performed in parallel, and the latch circuit including the D flip-flop
The image data RD27 to RD20 are output as a serial signal without intermittent one line at a time via 151a.

The signals ▲ ▼ and ▲ ▼ are respectively counters 153 and 154 which increment according to the signal WCK1 or RCK1 serving as an access reference outputted from the clock generator 152, and the addresses of the outputs of the counters 153 and 154 are Generated by the specified ROMs 155 and 156.

Note that the clock generator 152 is configured to output various clock signals, S
CLK1, SCLK2, φ1A, φ2A, φ2B, and RS are also generated.

FIG. 24 (a) is a diagram showing the spectral sensitivity characteristics of the image sensor 11, and FIG. 24 (b) is a diagram showing the spectral distribution characteristics of the exposure lamp 17 and the interference film filter of the rod lens array 15.

As is clear from FIGS. 24 (a) and (b), even when the reference white plate 16 of uniform density is read (see FIG. 13),
Image data RD27 of each color from the 5-channel synthesis circuit 102
Differences occur between the values of 〜20, GD27-20, and BD27-20 due to the spectral characteristics of the optical system. Therefore, white balance correction for forming an image having a correct color tone is required.

FIG. 15 is a block diagram of the white balance correction circuit 103.

In FIG. 15, the white balance correction circuit 103
Is the image data R of each color from the 5-channel synthesis circuit 102
C for D27-20, GD27-20, BD27-20 (8 bits each)
Correction coefficient data Wr, Wg, Wb7-0 given from PU 112
(8 bits each), and the ratio between RGB is 1:
Image data RD37-30, GD3 standardized to be 1: 1
The white balance correction circuit 103 outputs 7 to 30 and BD 37 to 30 (each 8 bits). The white balance correction circuit 103 includes multipliers 251 to 253 to which image data (R, G, B) D27 to D20 are input as multiplicands, respectively. Coefficient data Wr, Wg, Wb7-0
And the auxiliary data ND from the two's complement circuit 258 which are given in common to each color and add the arithmetic sum to the multiplier data MD
Adder 261 given to each multiplier 251-253 as r, MDg, MDb
263, the respective image data (R, G, B) D27 to 20 and the output data of the name multipliers 261 to 263 are added to obtain corrected image data (R, G, B).
G, B) having adders 271 to 273 for generating D37 to D30.

Each of the correction coefficient data Wr, Wg, Wb7-0 and the auxiliary data ND is 8-digit decimal data with a decimal point placed between the most significant bit and the next bit. That is, 2 ⁰ , 2 ⁻¹ , 2 ⁻² ... 2 ^-7 are allocated in order from the most significant bit, and 1/128 (2
^-7 ) Treated as a decimal value.

The 2's complement circuit 258 is always supplied with a 80H (1000 0000B) bit signal (integer 1) as the data to be converted CD from the CPU 112, and the most significant bit (sign bit) of the correction coefficient data Wr, Wg, Wb7-0. Is "0", the converted data CD is output as it is as positive auxiliary data ND, and when the sign bit is "1", the two's complement of the converted data CD, that is, "-".
"1" is output as negative auxiliary data ND. Therefore,
The multiplier data MD (r, g, b) is a value obtained by adding “1” to the correction coefficient data Wr, Wg, Wb7-0, or a value obtained by subtracting “1”.

FIG. 16 is a flowchart of a white balance correction process controlled by the CPU 112. This subroutine process
Although it can be executed at any time in consideration of the aging of the optical system, it is usually performed before the scanning of the document D is started every time the main power of the digital copying machine A is turned on.

First, in step # 102, the correction coefficient data Wr, Wg, Wb7
80H (integer 1) is set as ０0. As a result, the multiplier data MD (r, g, b) becomes 0, and the multipliers 251 to 253
Therefore, the image data (R, G, B) D27 to D20 are output as they are from the adders 271 to 273 as image data (R, G, B) D37 to D30. .

Next, in step # 103, the exposure lamp 17 is turned on at the standby position of the slider 14 to read the uniform density reference white plate 16 provided at the end of the platen glass. Ideally, when the reference white image is read, the respective image data of the three primary colors become equal, but actually, there is a difference between RGB as described above.

Therefore, in this embodiment, in order to perform the normalization so that the ratio between RGB is 1: 1: 1, the following steps # 104 to # 108
, A calculation process of the correction coefficient data Wr, Wg, Wb7-0 is executed.

In step # 104, the corrected image data (R, G, B) D37 to D3 output without being substantially corrected as described above.
0 is stored in the line memory 111 for each line, and an average value in one line is obtained for each color in step # 105.

Next, in step # 106, the relative data of each color is calculated by setting the largest one among the three average values as 1.
At 107, it is determined whether the ratio between the relative data is 1: 1: 1. If yes in step # 107, it means that the standardization has been completed, so the process returns to the main routine for controlling other image processing and the operation of each section of the digital copying machine. move on.

In step # 108, the correction coefficient data Wr, Wg, Wb7-0
, The reciprocal of the relative data corresponding to each color is set, and at the same time, the value of the sign bit is transmitted to the correction circuit 258 of 2 as the control signal 2SC, and the process returns to step # 103.

For example, if the relative data values of R, G, and B are “1”, “0.
95 "and" 0.65 "," 1/1 "is used as the correction coefficient data Wr7-0, and" 1 / 0.95 "=" 1 "as the data Wg7-0.
+5/95 ”as data Wb7-0,“ 1 / 0.65 ”=“ 1 + 3 ”
Set 5/65 ”respectively. Therefore, in this case, the multiplier data MDr, MDg, MD added to each of the multipliers 251-253.
As for b, 1 is subtracted from the correction coefficient data W (r, g, b) 7 to 0, so that “b” is “0”, “5/95”, and “35/65”.

Here, when the reference white plate 16 is read again in step # 103, when the same image data as the previous time, that is, relative data is obtained, the white balance circuit 103 obtains “1”, “95/100”. , “65/100” image data (R, G, B) D27 to D20 are input.

The multiplier 252 corresponding to G performs multiplication of “5/95” times,
As a result, the adder 272 outputs "5/100" which is the output of the multiplier 252 and "95/10" which is the value of the image data GD27 to GD20.
The image data GD37 to GD30 of “100/100” to which “0” is added are output.

Similarly, multiplication and addition operations are performed for B, and the adder 273 outputs image data BD37 to BD30 equal to the image data RD37 to RD30 corresponding to R.

Therefore, the ratio of the corrected image data (R, G, B) D37 to D30 of each color corresponding to the image data (R, G, B) D27 to D20 read from the reference white plate is 1: 1: 1. This means that the white balance correction has been completed.

Thereafter, when the document D is read, the white balance correction circuit 103 outputs the set correction coefficient data W (r,
g, b) By performing an operation based on 7 to 0, the image data input from the previous stage is corrected and transmitted to the subsequent image processing circuit.

FIG. 17 is a block diagram of the shading correction circuit 104.

The shading correction circuit 104 receives the image data RD37 to RD3 of each of the three primary colors from the white balance correction circuit 103.
0, GD37-30, and BD37-30 (8 bits each) provided with a shading correction unit SH and density conversion RO
Although the circuit is constituted by M280, the circuit configuration of each color is the same, and FIG. 17 shows only a portion corresponding to the image data RD37 to RD30.

The shading correction unit SH is configured to read one line of reference image data obtained by reading the reference white plate 16 as a reference color image.
RAM 281 for storing SRD, reciprocal conversion ROM 28 for outputting reciprocal data ID of reference image data SRD read from RAM 281
2. It has a multiplier 283 for multiplying the image data RD37 to RD30 obtained by reading the original image with the reciprocal data ID.

The RAM 281 has a capacity of 8 Kbytes and can store the reference image data SRD for one line (for 8000 pixels) in the main scanning direction, but is written and read out through a common input / output port. Therefore, gate circuits 284 and 285 are provided to avoid collision of input / output data, and RAM 281 is provided.
The address counter 28 performs an increment according to the image clock signal SYNCK and performs an initial setting according to the horizontal synchronization signal TG defining one line cycle.
Done by 6. The image clock signal SYNCN is a signal serving as a reference for the transmission timing of image data between the above-described image processing circuits.

As soon as the image reader IR is turned on, the exposure lamp 17 is turned on at the standby position of the slider 14, and the uniform density reference white plate 16 provided at the end of the platen glass.
Is read. At the same time, the write control enable signal ▲ ▼ given from the CPU 112 becomes active (active low), and the read reference image data SRD for one line is stored in the order of the pixels one pixel at a time starting from the top address of the RAM 281. , That is, the preparation for the pseudo-correction is completed.

When the reading of the document D is started, the enable signal ▲
▼ becomes inactive and the shading correction enable signal ▼ becomes active, and the reference image data SRD is read in order from the head address of the RAM 281 in synchronization with the input of the image data RD37 to RD30 from the preceding stage according to the signal SYNCK.

In the above-mentioned A / D conversion in the digitization processing circuit 101,
The maximum value of the photoelectric conversion signal from the element 12 is “255” (11111111
B), the reference image data SRD obtained by reading the reference white image is ideally all “255”. However, the light distribution of the exposure lamp 17 and the spectral sensitivity of the element 12 are actually ideal. For example, there is a value of “254” or less, and a difference occurs between pixels.

Therefore, in this embodiment, in order to compensate for the difference between pixels and to make one line uniform, reciprocal data IDs are prepared in advance in the reciprocal conversion ROM 282 for all possible values of the reference image data SRD. . The reciprocal conversion ROM 282 has a capacity of 256 bytes and stores the reference image data SD read from the RAM 281.
An address is designated by r, and the reciprocal data ID of the designated address is read.

In the 8-bit reciprocal data ID, “1 of the decimal numbers from“ 0 ”to“ 255/128 ”in increments of“ 1/128 (2 ⁻⁷ ) ”that can be displayed by the sum of the numerical values assigned to each bit ”(1000 00
00B) to “255/128” (1111 1111B).

That is, if the reference image data SRD is “255”, “255/25
"5" = "1", "200" is "255/200", "128" is "255/128", and so on for the reference image data SRD of "128" to "255". "255" which is the maximum data
Corresponds to the reciprocal value converted as “1”. For the reference image data SRD of “127” or less, the same “255 /
128 ”are associated with each other.

In the multiplier 283, since the image data RD37 to 30 read by the same element 12 is multiplied by the reciprocal data ID corresponding to the reference image data SRD, the reference image data SRD is read when the reference white plate 16 is read. Is 12 or more
Are read from the shading correction unit SH as corrected image data SHD7-0, which is multiplied by the reciprocal data ID and subjected to correct shading correction. For example, when the image data RD37 to 30 by the element 12 whose reference image data SRD is “200” is “150”, a multiplication of “150” × “255/200” is performed, and as a result,
It is corrected to “204”.

Reference image data SRD when read on reference white plate 16
Are approximately doubled and output.

The corrected image data SHD7-0 output in this manner
Becomes the address of the density conversion ROM 280 and is added to the density conversion ROM 280 as a density conversion table index address. From the density conversion ROM 280, logarithmic conversion data corresponding to the values of the corrected image data SHD7 to SHD0 is read out, and the next-stage color correction circuit 105 is provided as image data RD47 to RD40 proportional to the density of the document D.
Sent to

FIG. 18 is a block diagram of the color correction circuit 105. The color correction circuit 105 includes a minimum value detection unit 801 that selects the minimum (minimum image data DMIN) among the additive color image data (R, G, B) D47 to 40 input from the previous stage, and a UCR. Coefficient data U7-0 or BP coefficient data K7-0 and minimum image data DMIN
802, which performs multiplication with the above, a UCR operation unit 810 including three adders 811 to 813 provided for each color of the additive color system, and outputs of the adders 811 to 813 are directly input. A color correction masking section 820 including three multipliers 821 to 823 and two adders 824 and 825 connected so as to obtain an arithmetic sum of outputs of the multipliers 821 to 823, and an output of the adder 825 , Multiplier
An output selector 830 for selecting one of the output of 802 or the image data GD47 to GD40 of G is provided, and the additive system is BP-processed to the image data (R, G, B) D47 to D40, UCR Image data D5 for controlling the amount of toner of each color used for image formation by performing the process and the color correction masking process
Outputs 7 to 50.

When performing the BP process, the multiplier 802 is provided with the BP coefficient data K7 to K0 of the value “k” optimized in advance by the CPU 112 as a multiplier, and converts the value into the minimum image data DMIN (the value is “min”). The data of “k × min” multiplied by “k” is input as an option input of the output selector 830 as black plate image data BkD7-0 corresponding to the toner of Bk.

When the UCR process is performed, the UCR coefficient data U7 to U0 having the optimized value “−u” are used as multipliers as multipliers.
The undercolor image data UD7 to UD0 of “−u × min” obtained and supplied to the adder 811 are commonly applied to the adders 811 to 813 of the UCR calculation unit 810. In each of the adders 811 to 813, the additive color image data (R, G, B) D47 to 40 and the lower color image data UD7 to 0 are added, and the image data (R, G,
B) Under color-removed image data GUD47 to 40, BUD47 to 40, and RUD47 to 40 are generated by subtracting the optimum UCR amount “uxmin” from D47 to D40.

The color correction masking section 820 performs a matrix operation represented by the following equation (2).

Here, C, M, and Y are image data (C,
M, Y) D7 to D0, and Gu, Bu, and Ru are the undercolor-removed image data (G, B, R) UD47 to UD40 for each of the additive colors. Also,
gj, bj, and rj (j = 1, 2, 3) are optimal primary masking coefficient data obtained by a trial experiment, and are given as multipliers to the multipliers 821 to 823 in accordance with the operation of the laser printer unit LP. Things.

For example, CD7 for C (cyan) toner attaching operation
When generating 0 to 0, the undercolor-removed image data Gu, Bu, and Ru of the subtractive color system are distributed and synthesized as shown in the following equation (3).

_{CD7~0 = g 1 Gu + b 1} Bu + r 1 Ru ... (3) digital copier A of the present embodiment as described above is not provided with an image memory capacity capable of storing data of all the pixels of the document D, 1 single A maximum of four reading scans are performed on the document D, and the respective toners are superimposed and adhered in the order of C, M, Y, and Bk to form a color image.

Therefore, the output selector 830 determines the image data (C, M, Y) D7-0 of each color of the subtractive color system, the blackboard image data BkD7-
0, image data as mono-color image data MOD7-0
One of GDs 47 to 40 is selected and output as image data D57 to D50 in the subsequent stage. That is, when the mono-color selection signal ▲ ▼ for specifying the mono-color image forming area is active (active low), the mono-color image data MOD7-0
When the signal ▲ ▼ is inactive and the black board signal ▲ ▼ is "L", the black plate image data
When BkD7-0 is "H", image data (C, M, Y) D7-0 of each color of the subtractive color system is selected.

In the present embodiment, the circuit is simplified by performing the multiplication using the minimum image data DMIN in the UCR processing and the BP processing as a multiplicand in one multiplier 802 as described above. Switching between the processing and the BP processing is performed in conjunction with the switching of the output selector 830.

Further, by using G (green) image data GD47 to GD40 having a large relative luminosity factor as the monocolor image data MOD7 to MOD0, a natural monocolor image suitable for the relative luminosity factor can be formed.

FIG. 19 is a block diagram of the gamma correction circuit 106, and FIGS. 20 (a) to (c) are diagrams showing the relationship between the input and output of the gamma correction circuit 106.

The gamma correction circuit 106 includes a density adjustment unit 50 that increases or decreases individual values of the image data based on the density coefficient data T7 to T0 to form a hard copy image having a desired density or an optimized density.
2. It has a background removal unit 501 that reduces individual values of image data based on background data UND7 to UND0 to increase the overall contrast of the formed image.

When the copying operation of the digital copying machine A is in the manual mode, the density coefficient data T7 to 0 and the background data UND7 to 0 are set by operating a density designation key on an operation panel (not shown). In the case of the auto mode selected in, the setting is automatically made according to the document density detected in the preliminary scanning. The eight most significant bits and the least significant seven bits of the density coefficient data T7 to T0 are treated as positive decimal numbers assigned to the first integer and the first to seventh decimal places, respectively.

The image data D57 to D50 input from the color correction circuit 105 are
First, the background removal unit 501 receives a background removal process. For example,
When an original D composed of a color image printed on yellow paper is copied on white copy paper, a laser printer unit LP is used to form a clear image in which the color image is raised.
Data D57 input at the time of Y toner adhesion operation in
A process is performed to reduce 5050 according to the base color (yellow) density.

The background data UND7 to UND0 set by the CPU 112 are converted into negative data by the two's complement circuit 511 of the background removal unit 501 and added to the adder 512, and the adder 512 outputs the positive image data D57 to An addition operation with the background data UND7 to UND0 is performed.

As a result, the input image data D5 as shown in FIG.
Output image data D67 to D60 obtained by reducing base data UND7 to UND0 from 7 to 50 are obtained. In the figure, "A", "B", and "C" are the background data UD7-0, respectively.
Indicate "0", "20", and "50", and in any case, the density adjustment unit 502 does not increase or decrease the data. That is, there is no adjustment.

Similar to the white balance correction circuit 103 in FIG. 15 described above, the density adjusting unit 502 performs multiplication and multiplication in order to realize a wide range of multi-stage adjustments by processing with a limited number of bits (the same 8 bits as image data). The data is increased / decreased by the arithmetic processing combining the addition.

That is, the density adjusting unit 502 multiplies the image data D57 to D50 input via the background removal unit 501 by the density coefficient data T7 to T0, and converts the output of the multiplier 521 to negative data. Two's complement circuit 522, control signal Shader selector 523 for selecting the output of the multiplier 521 or the output of the two's complement circuit 522 in accordance with
Adder 524 for adding 50 and the selected output of shading selector 523
And adjusts the input image data D57 to 50 in a range of 0 to 3 times.

When forming a dark image, the enable signal Becomes “H”, and at this time, the shade selector 523 is set to the multiplier 531
Select the output of When forming a faint image, the enable signal Becomes “L”, and at this time, the density selector 523 selects the output of the two's complement circuit 522.

Accordingly, in the adder 524, the input image data D57 to D50,
The density coefficient data T7-0 (γ) is changed by adding the density coefficient data GDC7-0 and the output image data D67-60 as Di, γ, and Do, respectively, and performing an addition operation expressed as Do = Di ± γDi. Thus, within the range indicated by the arrow in FIG. 20 (b), the density gradient (the gradient of the straight line in the figure) can be set as "256" when increasing the density and "128" when decreasing the density. It is possible to adjust the density steplessly. In the figure, "d" is not adjusted, that is, the density coefficient data T7 to
When 0 is set to 0, both e and e are set to 0.
5 "(0100 0000B).

FIG. 20C shows image data D57 to D5 input from the preceding stage.
0 shows input / output characteristics when both background removal processing and density adjustment processing are performed. The broken line indicates no processing, the solid line indicates that the background data UND7-0 is "75" (0100 1011B), and the density coefficient data T7 The case where the adjustment is made thicker by setting “-0” to “0.5” is illustrated.

 FIG. 21 is a block diagram of the color editing circuit 107.

The color editing circuit 107 is an inverter circuit 601 that logically inverts the image data D67 to 60 input from the gamma correction circuit 106 to generate inverted image data IND67 to IND60 for forming a negative / positive inverted image. A designated color image data generating unit 602 for outputting designated color image data HD7 to HD7 for reproducing colors, image data D67 to 60 or inverted image data IN
Negative / positive selector 603 for selecting D67 to D60, color change selector 604 for selecting the output of negative / positive selector 603 or specifying color image data HD7 to HD0, color change selector 6
An area paint selector 605 for selecting the selected output of 04 or the designated color image data HD7-0 as the image data D77-70 is provided. When outputting the image data D77-70, the area paint selector 605 is used to form a color-edited image. (Fill)
The selectors 603 to 605 are connected so that an image, a color-changed image, and a negative / positive inverted image are given priority in this order.

Each of the selectors 603 to 605 is activated when an image of an area specified by an editor (not shown) having a sheet-shaped area scale and a point specifying stylus pen for specifying a forming area of each color edited image on the document D is provided. ▲, ▲
The selection operation is performed according to ▼ and ▲ ▼.

That is, each signal When active, the negative / positive selector 603 selects the inverted image data IND 67 to 60, and the color change selector 604 and the area pen point selector 605 select the specified color image data HD7 to HD0. , A color edited image is formed. However, the signal ▲
▼ is applied to the color change selector 604 via a gate circuit 632 controlled by a color determination signal CJ described later.

In addition, each signal Are inactive, the color editing circuit 107 enters a through state. That is, the input image data D67
60 are transmitted to the subsequent stage as image data D77 to D70 without being processed.

The designated color image data generating unit 602 is a color data signal 1D for up to four colors for reproducing the color designated by the operator.
A color generator 621 for generating 7-0, 2D7-0, 3D7-0, and 4D7-0, and a color data signal (1-4) D7 according to signals EDIT2 and EDIT3 corresponding to the designated color of the color change image or the area paint image. And a selector 622 for selecting one of the data D0 through D0 and outputting it as designated color image data HD7-0, and designates the color generator 621 from the ROM 113 via the CPU 112 before the scanning of the document D is started. Calculation information corresponding to the color is provided.

When a color-changed image is formed, for example, when a brown portion is changed to blue, the color generator 621 is provided with calculation information corresponding to the designated color (changed color) blue, and is simultaneously stored in the ROM 113 in the color determination RAM 631 in advance. The stored brown (changed color) RGB three-color separation data is stored.

The address specification at the time of reading of the color discrimination RAM 631 is performed by the additive three-color image data (G, B, R) D47 to D40 output from the shading correction circuit 104, and the respective image data (G, B, R) The 1-bit data (color discrimination signal CJ) to be read becomes "0"("L") only when the mutual ratio of D47 to D40 is a value corresponding to the brown color of the color to be changed.

Therefore, when the color of the pixel under processing is brown designated as the color to be changed, if the signal 信号 is “L”, the output of the gate circuit 632 is also “L” (active), and the color change selector 604 is blue. Specified color image data HD7-0
Select

In the present embodiment, the gamma correction circuit 106 and the color editing circuit 107 are independent from each other, and the gamma correction circuit 106 and the color editing circuit 107 are provided in this order along with the transmission of image data. A process for forming a color change image or an area paint image can be performed without receiving the image.

FIG. 22 is a block diagram of the scaling / editing processing circuit 108.

The magnification / editing processing circuit 108 is a color editing circuit 107 in the preceding stage.
The image data signals D7 to 70 input from are subjected to scaling processing and editing processing relating to the image formation position and form, and output as image data signals D87 to D80 to the subsequent MTF correction circuit 109. Is an image clock signal serving as a reference for transmission timing of image data between the above-described image processing circuits.
This is performed via latch circuits 412 and 413 that perform a latch operation according to SYNCK.

The scaling / editing processing circuit 108 generates a scaling clock signal by thinning out the signal SYNCK, and outputs a write clock signal WCK and a read clock signal RCK in parallel. A predetermined amount is alternately written in each line cycle, and when one performs a write operation, the other performs a read of the written image data.
Write address counter 403 that specifies the address at the time of writing 01, 402, RAM 4 according to read clock signal RCK
A read address counter 404 for specifying an address at the time of reading of 01 and 402, and an address selector 405 and 40 for selecting a write address WA from the write address counter 403 and a read address RA from the read address counter 404.
6. It has a line parity counter 407 for selecting a write operation or a read operation of the RAM 401, 402.

Each of the RAMs 401 and 402 has a capacity of 8 Kbytes and can store image data for one line (for 8000 pixels) in the main scanning direction.

The write address counter 403 increments the count by “1” in accordance with the signal WCK from a fixed count initial value for each line, that is, counts up. The read address counter 404 performs various counting operations as described later. It can be controlled by an edit processing signal.

The line parity counter 407 is an odd line signal in which “L” and “H” are alternately switched every time the horizontal synchronization signal TG defining one line cycle is counted once. Odd line signal Even line signal corresponding to inverted signal of Is output, and the write operation or the read operation of the RAM 401 or 402 is selected.

The clock generation circuit 400 outputs a scaling control enable signal ▲
When a reduced image is formed, a scaled clock signal is output as a write clock signal WCK and a standard clock signal SYNCK is output as a read clock signal RCK. When forming an enlarged image, the signal SYNCK is output as the write clock signal WCK, and the scaled clock signal is output as the read clock signal RCK.

These signals WCK with different number of pulses per unit time,
If the image formation is performed based on the image data signals D87 to D80 generated by making the access timings at the time of the writing operation and the reading operation of each of the pair of RAMs 401 and 402 different with the signal RCK, in the main scanning direction, A scaled image can be formed. The magnification in the sub-scanning direction is changed by changing the moving speed of the slider 14.

The initial count value of the read address counter 404 is set according to the load signal LOAD applied from the repetition circuit 470 based on the load data LOAD · DATA from the adder circuit 461 to which the movement data MOV · DATA is given from the CPU 112.

By appropriately changing the initial count value, it is possible to form a moving image in which the image forming position is shifted.

That is, as described above, the capacity of the RAMs 401 and 402 is 8 Kbytes (8
192 × 8 bits), and addresses (13 bits) from “0H” to “1FFFH” can be assigned. On the other hand, the read address counter 404 is a 15-bit counter,
Addresses from "H" to "7FFFH" can be generated. Therefore, the address area of the RAM 401, 402 is changed from "4000H" to "5FFF
H, and by setting the initial count value of the read address counter 404 to be increased or decreased around "4000H" by the load data LOAD / DATA, the read position from the RAM 401, 402 is shifted left and right in the main scanning direction. be able to.

The repetition circuit 470 is for forming a repetition image, and includes an output of the read address counter 404 and the repetition data REP.
・ Comparator 471 to compare with DATA, Comparator 471
Output and iterative control enable signal , And a gate circuit 473 to which the output of the gate circuit 472 and the horizontal synchronization enable signal ▼ are input.

signal When is active, the count value is repeated data REP
When the data reaches DATA, the output of the comparator 471 becomes "L" (active). Along with this, the signal ▲ ▼ becomes active, the initial setting for loading the load data LOAD / DATA into the read address counter 404 is performed, and the read address counter 404 keeps reading even if one line of the RAM 401 or RAM 402 is being read. The increment is performed again from the initial count value. As a result, the image data stored in the specific address areas of the RAMs 401 and 402 are repeatedly read, and a repeated image data signal is generated. Repeated images are useful, for example, when creating multiple labels.

The variable initial setting circuit 460 is for forming an oblique image, and includes the adder 461 and the line counter 462 described above. When forming an italic image, the variable initial setting circuit 460 changes the initial count value of the read address counter 404 at predetermined intervals.

Line counter 462 is an italic enable signal Is active, the signal is incremented by the signal ▲ ▼, and the adder 461 adds the line counter to the movement data MOV / DATA.
The load data LOAD / DATA to which the output DOUT of 462 is added is output. Therefore, the count initial value of the read address counter 404 increases for each line. As a result, the formed image is an italic image shifted left by one pixel per line.

Further, the read address counter 404 can switch between an up-count operation and a down-count operation by a mirror enable signal ▼.

When the signal ▲ ▼ is inactive, the read address counter 404 reads the load data LOA as described above.
Signal R from the initial count value set based on DDATA
The up-count operation is performed according to CK, but the signal ▲
When ▼ is active, it is switched to the down-count operation.

When the read address counter 404 is switched to the down-counting operation, the image data written in the RAM 401 or RAM 402 is sequentially read from the one written later. For example, when "5000H" is set as the initial count value by the load data LOAD / DATA, the read address counter 404 decrements from the logical address "5000H", and the logical address "500" in the RAMs 401 and 402.
The image data stored in the address range M from the physical address corresponding to “H” to the physical address “0” is read.

The image formed based on the image data signals D87 to D80 generated by the down-counting operation of the read address counter 404 is a so-called mirror image (mirror image) obtained by inverting the original image symmetrically. This mirror image is used, for example, for creating a composition.

 FIG. 24 is a block diagram of the tone reproduction circuit 110 of FIG. 23.

The gradation reproduction circuit 110 is configured to store 256 gradation image data D97 to 90 and R
The threshold data SD (8 bits) read from the OM113 is compared with the threshold data SD (8 bits) to output binary data for determining the arrangement configuration of the display dots and the non-display dots of the formed image. Generation of gradation pattern to be stored in
RAMs (hereinafter abbreviated as "RAM") 201 to 205, latch circuits 211 to 215 for latching threshold data SD read from the RAMs 201 to 205 for synchronization with image data D97 to D90, and a latch circuit
Comparing the threshold data SD from 211 to 215 with the image data D97 to D90, the five comparators 221 to 225 for outputting image signals obtained by binarizing the image data D97 to D90, and reading the threshold data SD from the RAM 201 to 205 Address counters 232 and 234 for generating the address at the time, an address selector 23 for selecting the read address buses XA and YA from the address counters 232 and 234 and the write address bus MA from the CPU 112.
Has 6.

RAMs 201 to 205 store threshold data SD groups for two types of gradation matrices patterns corresponding to image formation of 8 gradations suitable for copying a character image and 29 gradations suitable for a photographic image. SD is ROM1 before scanning of document D starts.
Transferred from 13.

When reading the threshold data SD from the RAM 201 to 205,
The address selector 236 selects the read address buses XA and YA from the address counters 232 and 234, assigns them to the upper bits and the lower bits, and outputs them to the address terminals of the RAMs 201 to 205.

On the other hand, the address counter 232 stores image data D for one pixel.
Image clock signal SYNC that determines transfer timing of 97 to 90
The count is incremented by the input of K, and the other address counter 234 performs a count-up operation by a horizontal synchronization signal TG which is a reference of an image forming cycle of one line in the main scanning direction.

The threshold data SD stored in the RAMs 201 to 205 is read one by one in synchronization with the signal SYNCK, and the read five threshold data SDs are read after the transfer timing is adjusted by the latch circuits 211 to 215, respectively. , Respectively, image data D97-90
It is simultaneously compared with image data D97 to D90 of one pixel which is commonly provided to the comparators 211 to 215 via the bus.

As a result, the image data D97 to D90 are binarized based on the threshold data SD, and five binary data for one pixel are simultaneously output from the comparators 211 to 215. These two
The digitized signal is inverted by the inverters 230, 230,..., And then sent to the laser printer unit LP as image signals VIDEO4 to 0 reproduced with gradation.

In the laser printer section LP, the image signal VIDE
O4-0 are converted to serial signals, and the lighting control of the laser light source is performed in accordance with the image signals VIDEO4-0, thereby forming a color hard copy image in which five pixels are assigned to one pixel of the document D.

〔The invention's effect〕

According to the present invention, the reference levels for quantization of the photoelectric conversion signals output from the plurality of solid-state imaging chips of the image sensor are uniformed, and the fidelity of image reproduction can be increased.

[Brief description of the drawings]

1 (a) to 1 (c) are block diagrams of a digitizing circuit, FIG. 2 is a front sectional view showing a schematic configuration of a digital copying machine, and FIG. FIG. 4 is a perspective view showing an optical system of the image reader unit, FIG. 4 is a plan view of the image sensor, FIG. 5 is an enlarged view schematically showing a CCD sensor chip light receiving unit in FIG. 4, and FIG. FIG. 7 is a block diagram showing a driving circuit, FIG. 7 is a time chart showing a driving operation of the CCD sensor chip, FIG. 8 is a time chart showing an output of the CCD sensor chip, and FIG. 9 is an image processing device incorporated in the image reader section. FIG. 10 is a signal waveform diagram showing a sample-and-hold operation, FIG. 11 is a signal waveform diagram showing an A / D conversion operation, and FIG.
FIG. 13 is a flowchart of setting a reference potential of A / D conversion controlled by the PU, FIG. 13 is a block diagram of a 5-channel synthesis circuit, and FIG.
FIG. 15 is a time chart showing the operation of the 5-channel synthesizing circuit, FIG. 15 is a block diagram of the white balance correction circuit, FIG. 16 is a flowchart of the white balance correction processing controlled by the CPU, and FIG. FIG. 18 is a block diagram of a color correction circuit, and FIG.
The figure is a block diagram of the gamma correction circuit, and FIG.
(C) is a diagram showing the relationship between the input and output of the gamma correction circuit,
FIG. 21 is a block diagram of the color editing circuit, and FIG.
FIG. 23 is a block diagram of a tone reproduction circuit, FIG. 24 (a) is a diagram showing spectral sensitivity characteristics of an image sensor, and FIG. 24 (b) is interference between an exposure lamp and a rod lens array. FIG. 3 is a diagram illustrating spectral distribution characteristics of a membrane filter. 11 image sensor, 11a to 11e CCD sensor chip (imaging chip), 112 CPU, 126 clamp part (clamp means), 140 A / D converter (A / D conversion means), IR: Image reader (image reading device),
VIDEO4 to 0 ... Image signals.

Continuation of front page (56) References JP-A-63-287161 (JP, A) JP-A-1-233880 (JP, A) JP-A-63-314958 (JP, A) JP-A-2-67873 (JP) , A) JP-A-1-865 (JP, A) JP-A-63-208367 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 G06T 9/00

Claims (2)

(57) [Claims] 1. An image reading apparatus which divides an original image into pixels, reads each pixel with a plurality of separated colors, and outputs an image signal corresponding to each pixel by an image sensor having a plurality of imaging chips arranged therein. A clamp means for setting a reference level of a photoelectric conversion signal from each imaging chip; an A / D conversion means for generating image data by quantizing an output signal from the clamp means; reading a reference color image; Reference potential setting means for adjusting the reference potential of A / D conversion given to the A / D conversion means in accordance with the reference image data based on the photoelectric conversion signal of the color in the wavelength region having the largest relative luminosity of the colors. An image reading device, comprising: 2. An image sensor in which a plurality of image pickup chips are arranged, an original image is subdivided into pixels, and each pixel is read out by color separation into R, G, and B, which are three primary colors of an additive system.
In an image reading device that outputs an image signal corresponding to each pixel, an A / D conversion unit that quantizes a photoelectric conversion signal from each imaging chip to generate image data, reads a reference color image, and reads a G color photoelectric signal. A / D provided to the A / D conversion means according to the reference image data based on the conversion signal.
An image reading apparatus, comprising: reference potential setting means for adjusting a reference potential for conversion.