JP2861951B2 - Drive circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning drive circuit for an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art As a matrix type liquid crystal display device, a thin film transistor for addressing (hereinafter referred to as T) is provided in a liquid crystal panel.
A TFT active matrix type liquid crystal display device that obtains a display by incorporating an FT into a matrix is known.

The TFT active matrix type liquid crystal display device is driven by a horizontal driver for transmitting a pixel signal and a vertical driver for transmitting a scanning signal for performing line-sequential scanning (FIGS. 5 and 6).

As shown in FIGS. 5 and 6, an image signal is
The signal conversion circuit 17 and the γ correction circuit 18 control the liquid crystal voltage.
The signal is converted into an AC drive signal corresponding to the transmittance characteristic, and the horizontal driver 19 applies a voltage corresponding to the converted signal to the liquid crystal display device 21. The timing signal for row electrode scanning generated from the image signal through the signal conversion circuit 17 is:
It is sent to the vertical driver 20. Vertical screwdriver 20
Is mainly composed of a shift register unit in which D flip-flops are connected in series and a drive circuit unit (buffer). When a start signal is sent from the signal conversion circuit 17, a "1" pulse is generated according to the clock signal and the number of row electrodes (FIGS. 7 and 8). The scanning period H is H = T / T, where T is the total scanning period of the row electrodes and N is the number of row electrodes.
N.

That is, the vertical driver 20 operates during the scanning period H
Is output, and a voltage is applied so that the TFTs are turned on one row at a time. However, the total scanning period T must be a time that can not recognize human line-sequential scanning, the scanning period H, from the time that the voltage across the capacitance C _LC of the liquid crystal layer becomes the voltage applied by the horizontal driver 19 It needs to be longer.

The color is created by generating light having three primary colors of light, red, blue and green, and the brightness of the light is changed according to the voltage from the output signal of the horizontal driver 19 applied to the liquid crystal layer. To determine. At present, liquid crystal panels are being multi-colored (multi-gradation) and high-definition.

In the multi-color display, the voltage-transmittance characteristics of the liquid crystal currently used are largely changed by a slight change in voltage in a halftone, so that the accuracy of reproducing the voltage-transmittance characteristics is high. This is achieved by allowing a high voltage to be applied to the liquid crystal layer. Higher definition is realized by increasing the number of pixels, and is made possible by shortening the scanning period H. Therefore, in order to realize multicolor and high definition, the horizontal driver 19 must be able to apply a highly accurate voltage to the liquid crystal layer in a short time.

On the other hand, as described above, the vertical driver 20 needs to send a scanning pulse having a scanning period H during which the voltage applied to the liquid crystal layer is applied to the horizontal driver 19, that is, a period during which the TFT is turned on. . At this time, the time constant T _ON = R _ON · C _LC (R _ON
If the width of the scan pulse to the gate electrode of the TFT is not sufficiently long with respect to the on-resistance of the TFT, the liquid crystal layer cannot be charged sufficiently. This can be solved by extending the scanning period H forward without increasing the total scanning period T (Japanese Patent Application Laid-Open No. 62-136624). However, in an actual driving circuit of a liquid crystal display device, the time constant is 4 times. Since the scanning is performed with a scan pulse width of about 5 times, there is a sufficient charging time, and there is no problem.

Next, a problem that occurs when the scanning drive pulse is shifted will be described with reference to FIGS. FIG. 8 shows a conventional vertical driver which shifts at the rising edge of a clock. As for the output of the vertical driver, the output of the (i-1) th row is "1" at a certain clock. At the rising edge of the next clock, the output of the (i-1) th row is changed from "1" to "0" and i
The output “0” → “1” on the line is switched at the same timing. This is because the TFT in the (i-1) th row is turned off and the TF in the i-th row is
This means that T is turned on at the same timing.

On the liquid crystal display device, the rising and falling of the scan electrode waveform becomes slow due to the load of the TFT and the wiring (FIG. 9). Therefore, the rise of the output of the (i-1) -th row and i
The output rises in the rows overlap, and the TFTs in the (i-1) th row and the TFTs in the i-th row are simultaneously turned on. i-
If the TFTs in the first row and the TFT in the i-th row are turned on at the same time, conduction occurs between the liquid crystal layer in the i-1th row and the liquid crystal layer in the i-th row, and the movement of charges occurs. The charge to be stored fluctuates.

On the other hand, when the scanning panel on the i-th row becomes "1", the scanning side wiring in the liquid crystal display device connected to the output of the vertical driver and the liquid crystal display connected to the output of the horizontal driver for sending pixel signals. The voltage applied to the data-side wiring fluctuates due to parasitic capacitance generated at a point where the data-side wiring approaches in the device. At this time, T
When the FT and the TFT in the i-th row are simultaneously turned on, the fluctuated voltage is applied to the liquid crystal layer in the (i-1) -th row, and i
The electric charge accumulated in the -1st row varies.

Therefore, a voltage different from the voltage applied by the horizontal driver is applied to the liquid crystal layer, which causes image quality deterioration different from the expected one in which the brightness of light appearing in the liquid crystal display device, which is called a crosstalk display defect, differs from that expected. When multi-coloring is promoted, the above-described variation in charge stored in the liquid crystal layer causes a difference between an expected color and an output color, which is a problem in quality.

In order not to cause the simultaneous ON state of the TFTs, the vertical driver applies a voltage higher than the switching voltage of the TFT. By applying a large voltage, only the rise and fall of the scan electrode waveform affect the switching of the TFT.

The rising and falling of the scanning electrode waveform can be made sharp by increasing the dimension of the transistor of the driving circuit (buffer) of the vertical driver and increasing the driving capability. It is conceivable not to cause the ON state.

However, when the dimension of the transistor is increased, not only the chip size of the vertical driver integrated circuit is increased, but also the through current of the buffer is increased, so that the power consumption of the vertical driver integrated circuit is increased. .

In the case of driving and displaying a liquid crystal driving device arranged in a dot matrix, the bias power supply is cut off when the level of the AC signal changes, and the timing of the AC signal is delayed according to the cutoff time. There has been proposed a bias circuit that reduces crosstalk display by delaying the image and improves image quality degradation (Japanese Patent Laid-Open No. 4-31091).
No. 9).

[0017]

SUMMARY OF THE INVENTION In driving a TFT active matrix type liquid crystal display device, it is possible to suppress deterioration of image quality due to crosstalk display failure caused by simultaneous ON state of TFTs caused by overlapping of scan electrode waveforms. The above method is not suitable as a means for solving the problem. This is because, unlike the case where a liquid crystal driving device arranged in a dot matrix is driven and displayed, the driving of the TFT active matrix type liquid crystal display device is performed by the vertical driver and the horizontal driver as described above.

An object of the present invention is to provide a TFT active matrix which is problematic in realizing multi-color and high-definition without increasing the dimension of the transistor, without increasing the total scanning time, and without decreasing the operation speed. It is an object of the present invention to provide a liquid crystal display drive circuit which suppresses image quality deterioration due to crosstalk display caused by simultaneous ON state of TFTs caused by overlapping of scanning electrode waveforms of a liquid crystal display device.

[0019]

In order to achieve the above object, a liquid crystal display driving circuit according to the present invention has a delay circuit and drives an active matrix type liquid crystal display device. , The delay circuit includes a scanning drive.
Provided in a shift register section for shifting the dynamic pulse,
For the input to the scan drive pulses, standing delaying the rising timing of only the scan driving pulse delay time set
By increasing the frequency, the overlap of scan electrode waveforms that causes crosstalk is suppressed. In addition, the present invention
The liquid crystal display drive circuit according to
For liquid crystal display driving a passive matrix liquid crystal display
A drive circuit, wherein the delay circuit includes a shift register unit.
To the output side of the output buffer that outputs an output signal to each line
Connected, sends its output to the next line's output buffer,
By detecting the fall of the output buffer with a delay
Circuit configuration that delays the rise of the next row output buffer
It is what it was.

[0020]

The delay until the vertical driver output rises is delayed by using a delay circuit provided in a vertical driver or a shift register, so that the falling of the output of the previous row and the scan electrode waveform do not overlap. As a result, T
Avoid the simultaneous ON state of FT. For this reason, image quality degradation for crosstalk display can be suppressed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

( Reference Example ) FIG. 1 is a circuit diagram showing a liquid crystal display driving circuit according to a reference example of the present invention.

In FIG. 1, reference numerals 1 to 3 denote i + 1 to i +
D-flip-flops 4 to 6 used as the shift register unit 7 up to one row are buffers for each output. As described above, the conventional vertical driver includes a shift register and an output buffer.
Delay circuits 8 to 10 for delaying the output stage and AND circuits 11 to 13 for calculating a logical product of a D-flip-flop output of the previous output stage and the output stage. The D flip-flop outputs at the rising edge of the clock.

It is assumed that the output Qi-1 of the D-flip-flops 1 to 3 in the (i-1) -th row is "1" at a certain clock. At the rise of the next clock, the signal of Qi-1 changes from “1” to “0”, and the D-flip-flop 1
The outputs Qi of # 3 to # 3 change from "0" to "1".

At this time, in the reference example, a signal "0" obtained by delaying the signal of Qi-1 by the delay circuits 8 to 9, and
Since the logical product of the signal Qi and the signal “1” is obtained, the waveform Xi output to the scan electrode is delayed by the delay circuits 8 to 8 as shown in FIG.
9, the rise is delayed by the time Dφ set by “9”, and “1” → “0” of the scan electrode waveform Xi−1 in the (i−1) th row.
And “0” of the scanning electrode waveform Xi of the i-th row →
The timing of "1" does not have to be the same.

At this time, even when the scan electrode waveform becomes dull due to the load of the TFT and the circuit in the liquid crystal display device, the rise of the output of the i-1 row does not overlap with the rise of the output of the i row. And the TFT in the i-th row are not simultaneously turned on. Therefore, it is possible to improve image quality deterioration due to crosstalk display failure caused by the simultaneous ON state of the TFTs.

(Embodiment 1 ) FIG. 2 shows an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a liquid crystal display drive circuit according to No. 1 .

The first embodiment is a case where the output is delayed in the shift register section. The delay circuit 9 is connected to the input Di of the D flip-flop 16 of the shift register section. D
-The output Qi of the flip-flop 16 is the output of the NOR circuit 14 which takes the logical sum of the signal from the delay circuit 9 and the signal obtained by shifting the signal from the delay circuit 9 in synchronization with the clock.

With the above configuration, the rising timing of the output Qi of the D flip-flop 16 can be delayed. Also, instead of the NOR circuit 14, NAN
It can also be realized by using a D circuit. Further, the first embodiment has an advantage that the number of transistors can be reduced compared to the reference example . This is advantageous in that the chip size of the integrated circuit can be reduced in a vertical driver having many outputs.

When the waveform is largely dull due to the load of the TFT and the circuit in the liquid crystal display device, the scan electrode waveform may slightly overlap, but the scan pulse width, output drive capability and power consumption of the vertical driver, chip size In consideration of the above, the delay time can be optimized so that the accuracy of the voltage applied to the liquid crystal layer is sufficiently high. In a vertical driver for a TFT active matrix display,
By setting a delay time of about several hundred ns, a liquid crystal display device in which the accuracy of the voltage applied to the liquid crystal layer is sufficiently high can be configured.

(Embodiment 2 ) FIG. 3 shows an embodiment of the present invention.
It is a circuit diagram showing a liquid crystal display disturbance circuit according to 2.

In the second embodiment, delay circuits 8 to 10 are connected before output buffers 4 to 6, and outputs of the delay circuits 8 to 10 are sent to the next line. This circuit delays the rise of the i-th row by delaying and detecting the fall of the (i-1) -th row ahead of the output buffers 4 to 6.

In the second embodiment, since the falling of the scanning electrode waveform at the end of the output buffer where the effect due to the dull output due to the TFT and the wiring appears is detected, even if the dulling of the scanning electrode waveform is large. By optimizing the delay time, the simultaneous ON state of the TFTs can be avoided regardless of the load.

As described above, the vertical driver of the present invention
By delaying the fall of the scan electrode waveform and taking the logical product or OR of the delayed signal and the rise of the scan drive pulse of the next row, the rise timing of the scan drive pulse of the next row is delayed, It is possible to suppress image quality deterioration due to crosstalk display failure caused by simultaneous ON states of TFTs caused by overlapping waveforms.

[0035]

As described above, according to the present invention, T
The vertical driver for driving the FT active matrix type liquid crystal display device has a delay circuit inside, and thus delays the time until the start of the rise of the driving output pulse. Thereby, the TF caused by the overlap of the scan electrode waveforms generated during the falling period of the pulse of the preceding row
The period of the simultaneous ON state of T can be suppressed, and there is an effect of improving image quality degradation due to crosstalk display failure.

In the present invention, the timing of the clock is not changed, so that the total scan time is not increased and the operation speed is not reduced. Further, there is an advantage that another input signal for delay is not required, and it is not necessary to increase the buffer size of the drive circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a liquid crystal display drive circuit according to a reference example of the present invention.

FIG. 2 is a circuit diagram illustrating a disturbance circuit for a liquid crystal display according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a disturbance circuit for a liquid crystal display according to a second embodiment of the present invention.

FIG. 4 is a timing chart of the present invention.

FIG. 5 is a block diagram showing a TFT active matrix display device.

FIG. 6 is a diagram showing a configuration of a TFT and a liquid crystal layer in a liquid crystal panel.

FIG. 7 is a block diagram showing a conventional vertical driver.

FIG. 8 is a timing chart of a conventional vertical driver.

FIG. 9 is a timing chart of a conventional vertical driver.

[Explanation of symbols]

1-3 D-flip-flop used as shift register 4-6 Output buffer 7 Shift register section 8-10 Delay circuit for delaying shift register output 11-13 AND circuit in which one of inputs is inverted 14 D-flip-flop NOR circuit 15 to 18 D-flip-flop provided with delay circuit inside 17 Signal conversion circuit 18 γ correction circuit 19 Horizontal driver 20 Vertical driver 21 Liquid crystal display device

Claims (2)

(57) [Claims] 1. A liquid crystal display drive circuit having a delay circuit for driving an active matrix liquid crystal display device, wherein the delay circuit shifts a scan drive pulse.
It is provided in the transistor section and responds to the input scanning drive pulse.
Te, by rise delaying the rising timing of only the scan driving pulse delay time set, a liquid crystal display drive circuit, characterized in that to suppress the overlap of scan electrodes waveform which causes crosstalk. 2. An active matrix having a delay circuit.
Drive circuit for driving a liquid crystal display device.
The delay circuit outputs an output signal from the shift register unit to each row.
Is connected to the output side of the output buffer that outputs
To the output buffer of the next line, and
By detecting the fall with a delay, the next line output buffer
Circuit configuration that delays the rise of
And a liquid crystal display driving circuit.