JP2858511B2 - Arithmetic operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic operation circuit, and more particularly to a test circuit for a carry look-ahead circuit.

[0002]

2. Description of the Related Art Recently, as a performance required of a data processing device such as a microprocessor, a large amount of data can be processed at a high speed in a short instruction cycle.
In the case of an arithmetic circuit, for example, an arithmetic logic unit, processing a large amount of data at a high speed causes an increase in the data bit width. Recently, it is necessary to operate an arithmetic circuit of 32 bits or more with one clock of 33 MHz or more. Naturally, as the number of bits increases, the capacity of the carry propagation line increases, making high-speed operation difficult.

[0003] A carry-look-ahead circuit is often used to solve the problem. This carry look-ahead circuit speeds up the arithmetic circuit.
Generally, since these circuits are used as internal circuits, it is very difficult to check whether the operation is performed properly because the carry look-ahead circuit is redundant with respect to the normal carry propagation circuit. Difficult and undesirable from a fault detection standpoint. In other words, when the carry look-ahead circuit is not operating, logically operates normally because there is a path through which the carry propagates from the lowest to the highest even without passing through the carry look-ahead circuit depending on the failure mode. This is a normal carry look-ahead circuit.

For this reason, various test circuits for carry look-ahead circuits have been studied.
As in the case of 0, there is an example in which a pulse is generated by using a normal carry propagation path and a signal delay of a carry look-ahead circuit, and a flip-flop is set. There is a concern that the chip area may increase. In addition, in order to perform a stable operation, it is necessary to increase the pulse width to some extent, and there is a possibility that the number of delay elements for that purpose also increases.

[0005]

Since the above-mentioned carry look-ahead circuit of the conventional arithmetic circuit is usually used as an internal circuit, it is very difficult to confirm whether or not the circuit is operating normally. This is because, when viewed from the outside of the device, whether or not the carry-ahead look-ahead circuit is operating normally is observed as a variation in the operation speed, but the variation in the operation speed involves various factors. In many cases, it cannot be determined that the carry look-ahead circuit is defective. Therefore, it is desirable to add some test circuit to the carry look-ahead circuit and perform an operation test. Further, the test circuit of the carry look-ahead circuit needs to be configured to operate stably with as few elements as possible in order to suppress the chip area.

An object of the present invention is to provide an arithmetic operation circuit which solves the above-mentioned problems and does not increase the number of elements and the number of delay elements.

[0007]

According to the present invention, a test circuit of a carry look-ahead circuit includes a signal indicating that a prefetch condition of a carry look-ahead circuit is satisfied in an arithmetic circuit having a carry look-ahead circuit. It is characterized by comprising a NAND or NOR logic gate having a carry output signal as an input and a dynamic inverter having an output signal of the logic gate as an input.

[0008]

FIG. 1 is a block diagram showing a test circuit of a carry look-ahead circuit of an arithmetic operation circuit according to a first embodiment of the present invention. In FIG. 1, this embodiment uses a dynamic arithmetic and logic unit (hereinafter abbreviated as ALU) as an arithmetic circuit.

In the present embodiment, ALU1 to ALU4, a transfer gate 5 connected to GND for generating a carry signal of the least significant bit, an AND gate 37, and a dynamic carry line when a carry look-ahead condition is satisfied are established. G
A transfer gate 6 for dropping to the ND level, a signal 7 indicating that the carry look-ahead condition has been satisfied, a signal 8 for delaying the carry output, a delay 9 for delaying the carry signal, and a carry output 10 for ALUs 1-4. A dynamic inverter 11 for performing precharge at the same timing as the arithmetic unit, an output 12 of the dynamic inverter, and a logic circuit 13 constituting a carry look-ahead circuit
And an AND gate 14 and an inverter 31. Here (NOR for negative logic) 15 is a signal for enabling the carry input to the least significant bit. The dynamic inverter 11 has P and N channel field effect transistors 40 and 41. The logic circuit 13 has inverters 32, 33, 34, 35 and a NOR gate 36.

Here, for simplicity of explanation, 4-bit ALUs 1 to 4 will be described as an example. ALU 1-4
Is a method in which precharge is performed during a period when the clock φ is at a low level, and calculation / carry is propagated during a period when the clock φ is at a high level. When the operation result of the data input to the 4-bit ALUs 1 to 4 generates a carry in the most significant bit, that is, when the carry-ahead read condition is satisfied, the signal 7 becomes high level, and the carry line 10
To GND level. The condition that the carry-ahead look-ahead is satisfied means that if the addition result S of each bit to which a carry is not added is “1111”, if the least significant bit has a carry input, the result propagates to the highest carry output. This is the case.

Although the signal obtained by delaying the carry signal 10 is 8, when the operation is normal, a pulse having a width of at least 9 delay is observed at the output of the NAND gate 14. In general, it should be a pulse having a delay difference of 9 delay line segments + an ordinary carry propagation path and the output of the carry look-ahead circuit. By inputting the output of the NAND gate 14 to the dynamic inverter 11, the output of the inverter 11 changes from high to low. Although it is conceivable to use a flip-flop as a substitute for the dynamic inverter 11, the dynamic inverter is superior in the point that the number of elements is small and the responsiveness of a short pulse is used. A change from high to low of the dynamic inverter 11 at the sampling timing indicates a normal operation of the carry look-ahead circuit. However, the output of 11 must be latched before the start of the precharge of the next cycle.

Here, although the carry look-ahead circuit has failed and the carry look-ahead condition is satisfied, the signal 7
Is not active (in this case, high). In this case, since the signal 7 is always at the low level, the output 14
No pulse is generated. Therefore, the output 12 always remains at the high level. If only the calculation result is considered, the carry output 10 outputs a carry propagating inside the arithmetic unit, so that a normal result can be obtained. However, since the carry is not pre-read, the maximum operating frequency is reduced. If the carry-ahead condition is always active and a failure occurs, a correct carry output cannot be obtained at the output 10, so that the failure can be easily determined.

FIG. 3 is a block diagram showing a test circuit of a carry look-ahead circuit of an arithmetic operation circuit according to a second embodiment of the present invention. FIG. 4 is a timing chart showing the operation of each unit in FIG.

3 and 4, in this embodiment, the AND of the signal 22 indicating the test mode and the clock φ is ANDed without using the clock φ for precharging the dynamic inverter 11 of the embodiment. The gate 21 takes precharge with the output signal. Others are the same as FIG.

Originally, the failure detection of the carry look-ahead circuit may be performed in the test mode. Therefore, in the normal use mode, the dynamic inverter for detecting a fault need not be operating. Therefore, in the present embodiment, reduction of current consumption can be expected by precharging the dynamic inverter 11 only when necessary. Further, holding of the output 12 becomes easy. Other operations are first
This is the same as the embodiment.

[0016]

As described above, the carry look-ahead circuit of the present invention has an effect that the operation test of the carry look-ahead circuit of the arithmetic circuit can be easily performed by adding a small amount of hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an arithmetic operation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment of FIG.

FIG. 3 is a block diagram showing an arithmetic operation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart of the embodiment of FIG. 3;

[Explanation of symbols]

 1-4 ALU (bits 0-3) 5, 6 Transfer gate 7 Carry look-ahead circuit signal 8 Carry output signal after delay 9 Delay circuit (delay) 10 Most significant bit carry output 11 Dynamic inverter 12 Dynamic inverter output DESCRIPTION OF SYMBOLS 13 Carry look-ahead logic circuit 14, 21 AND gate 15 Carry input enable signal 22 Test mode signal 30 Data bus 31-36 Inverter 36 NOR gate

Claims (1)

(57) [Claims] 1. An arithmetic operation circuit comprising a test circuit for testing a carry look-ahead circuit, comprising: a NAND circuit having a signal indicating that a prefetch condition of the carry look-ahead circuit is satisfied and a carry output signal of the arithmetic circuit as inputs; An arithmetic operation circuit, wherein a test circuit of the carry look-ahead circuit is constituted by a NOR logic gate and a dynamic inverter which receives an output signal of the logic gate as an input.