JP2007220148A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor capable of reducing power consumption and of increasing speed. <P>SOLUTION: The microprocessor has a detection means for detecting an instruction for operating each calculation circuit, and means for activating one or more of the calculation circuits corresponding to the instruction detected by the detection means before calculation execution and for inactivating the activated calculation circuits after calculation termination. The microprocessor reads instructions of a quantity of (n) (n≥2) at the same time to decode them and executes calculation by using (n) pieces of the calculation circuits at the same time. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit such as a microprocessor having a functional circuit block for which low power consumption is desired, such as a built-in cache memory requiring high-speed access and multi-bit output.

  The prior art will be described below taking a microprocessor as an example.

  In recent years, high-speed microprocessors (hereinafter referred to as MPUs) have been developed in order to solve the problem caused by the mismatch between the internal instruction execution speed and the transfer speed of instructions and operands from the external main memory. In order to improve the processing performance by increasing the degree of parallelism, it has become common to incorporate multiple arithmetic units, and as a result, the increase in power consumption has become a serious problem .

  The main purpose of incorporating the cache memory is to fetch instructions and data at a high speed that matches the execution speed of the MPU.

  Today, the clock cycle of the fastest CISC type MPU is 25 to 40 MHz, but it is expected that an MPU exceeding 100 MHz in the RISC type will appear in the near future.

  Such an ultra-high speed MPU requires ultra-high speed access of several ns or less as a built-in cache memory.

  The built-in cache memory has a characteristic that the number of words is relatively small but the number of read bits per word is extremely large (up to 8 bits in a general-purpose SRAM). For example, even today's 32-bit MPUs generally implement parallel reading of several hundred bits, etc., and it seems that the number of parallel readings will further increase if the MPU becomes 64-bit in the future.

  Here, in general, a differential high-sensitivity sense amplifier using a bipolar transistor is suitable as a sense amplifier for an ultrahigh-speed memory. However, this circuit constantly consumes relatively large power. Further, if there is no special power saving means in other parts of the memory, power is consumed even if no memory access occurs.

That is, in a single-chip MPU incorporating a cache memory with ultra-high-speed access and multi-bit parallel output, the power consumption of the memory circuit becomes extremely large. However, it is expected to become impossible over time.

  As a first conventional technique known as a low power consumption technique, the memory circuit is effectively switched between standby mode power consumption and normal operation mode power consumption by a chip select signal CS equivalent to the memory address signal. There are some that reduce the power consumption.

  As a second prior art, for example, an ATD (Addres Transition Detector) circuit detects a change in an address signal, generates a clock pulse necessary for internal operation based on the signal, and requires a memory sense amplifier or the like. A device that operates only for a period to reduce power consumption is known.

Further, as described in Patent Document 1, etc., in a logic LSI such as an MPU, a) a power control instruction is provided corresponding to a plurality of functional blocks, and the corresponding functional block is switched to an active or inactive state by a program. B) A method of realizing low power consumption by providing a clock control circuit for each functional block and controlling the presence or absence of clock supply, c) A method of providing a power control circuit for each functional block A method for realizing low power consumption by shutting off power supply to functional blocks that are not used at the time of instruction execution is known. However, the above prior art lacks consideration for noise induced in the power supply line and the ground line due to a sudden change in the power supply current when switching between the normal power consumption state and the low power consumption state. There is a problem.
1) Since the circuit current greatly changes in a short time between the low power consumption state and the normal operation state, a large noise voltage is generated due to the inductance and resistance of the power supply line and the GND line.
2) The functional circuit itself or other internal circuit malfunctions due to the noise voltage. Even if no malfunction occurs, a certain time is required until the noise voltage disappears, which causes an effective decrease in memory access speed.

  FIG. 24A is a diagram for explaining generation of noise voltage in the power supply system. In the figure, 1300 is a power source, 1310 is a functional circuit block 1321, 1322 such as a memory circuit, for example, and GND-type inductances 1331 and 1332 are a power source system and a GND-type resistor, respectively.

FIG. 24B shows the change of the power supply current i and the changes of the power supply potential v ₁ and the GND potential v ₂ when the SW is turned on at time t ₁ and turned off at time t ₂ .

As shown in the figure, when the switch SW is turned on at time t ₁ , the circuit current i changes from 0 to a steady current during Δt ₁ time. At this time, as shown in the figure, the power supply potential v ₁ of the circuit changes greatly so as to have a peak in the negative direction, and the GND potential v ₂ changes greatly so as to have a peak in the positive direction. Conversely, when the switch SW is turned off at time t ₂ , the circuit current i changes from a steady current to 0 during Δt ₂ time. At this time, the power supply potential v _{1 of the} circuit changes greatly so as to have a peak in the positive direction, and the GND potential v ₂ changes greatly so as to have a peak in the negative direction.

For example, now, the circuit 1310 of FIG. 24 is 500 sense amplifiers, 2 per circuit.
It is assumed that a current of mA is consumed, and this current is switched from 0 to a steady current at Δt = 1 ns. At this time, the resistors 1331 and 1332 are ignored, and the inductance 1321,
1322 The L = 5 nH assuming the power supply noise v _n are as follows.

  In other words, such a large power supply noise is unacceptable in today's semiconductor integrated circuits that operate with a power supply voltage of 5 V or less.

Even if the noise can be reduced to an appropriate level, as shown in FIG. 24 (B), Δt ₁ hours and Δt ₂ hours are required until the power supply and GND noise disappear. This time depends on the current switching time, but usually 1 to 3 ns is required. This time is unacceptable in an ultrahigh-speed memory or the like that requires an access time of several ns or less, and becomes a major obstacle to high-speed operation.

  As described above, the problem of noise due to a change in power supply current is the same for a plurality of arithmetic units and other functional circuit blocks in a semiconductor chip.

  Incidentally, various technologies have begun to be introduced in recent high-performance MPUs in order to increase the processing capacity. The processing performance of the computer is evaluated by the following equation.

  CPI is the number of cycles required for one instruction.

The PISC processor has attracted attention in recent years. The main purpose of RISC is to improve the performance by bringing the above-mentioned CPI close to 1.

Recently, Super Scalar, VLIW, etc. have begun to attract attention as the next technology of RISC. This technique reads up to n instructions at the same time, interprets n instructions at the same time, and executes n instructions at the same time. By increasing the degree of hardware parallelism, the above-mentioned CPI can be reduced to 1 / n. To improve the performance of the computer. High-speed operation circuits such as Super Scalar and VLIW include differential logic circuits such as bipolar transistors,
BiCMOS low-amplitude circuits have come to be used, but circuits that pass DC current regularly consume relatively large power.

  MPUs such as Super Scalar and VLIW require n high-speed operation circuits having the same function, and there is a problem that the power consumption of the operation circuits increases n times.

For example, Non-Patent Document 1 discusses the related technology.
JP 61-45354 A Nikkei Electronics No. 487, November 27, 1989, P191-200

  As is apparent from the above description, the conventional technology for reducing power consumption in semiconductor integrated circuits and electronic circuits such as microprocessors does not take into account the problem of noise generated in power supply lines and ground lines during power switching. There has been a problem that a rapid start-up cannot be performed because it takes a certain time until the circuit malfunctions or the noise disappears.

  In particular, in the MPU having a conventional on-chip memory, there is a trade-off relationship between the reduction in noise at the time of power switching and the increase in memory access speed.

  Although the microprocessor having a cache memory has been described above, a similar problem occurs in a semiconductor integrated circuit or an electronic circuit having a functional block that requires high speed.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the power consumption and speed of a functional circuit block, in particular, a microprocessor having an on-chip memory such as a cache memory.

  Here, activation means supplying a predetermined power necessary for the operation of the circuit, and inactivation means supplying a power smaller than the predetermined power.

According to the semiconductor integrated circuit device of the present invention, the power supply system inductance L, the allowable power supply noise V _n.
, A functional circuit block having a circuit current switching width ΔI, and means for generating an operation start notice signal for activating the functional circuit block in advance of time T before the operation start, and
The T, L, V _n and ΔI are

Satisfy the relationship.

  Further, according to the memory of the present invention, a warning signal for notifying the start of operation is received, and the circuit current is increased to a predetermined value over a predetermined time from the reception of the warning signal. A function circuit block having a function of shifting to a power consumption mode and reducing a circuit current to a low power consumption mode current over a predetermined time after the execution of an operation is completed, and shifting to a low power consumption mode. And is activated by an access notice signal for giving a notice of access, and executes a predetermined memory operation based on an address signal, a read / write control signal, and a data input / output signal.

  The microprocessor of the present invention is a microprocessor that reads and decodes n (n ≧ 2) instructions at the same time, and executes operations simultaneously using n arithmetic circuits, and operates each arithmetic circuit. Detection means for detecting an instruction in advance, and means for activating one or more operation circuits corresponding to the instruction detected by the detection means prior to execution of the operation, and inactivating the activated operation circuit after completion of the operation And have.

  Further, the microprocessor of the present invention has means for detecting that various race conditions occur between instructions executed at the same time, and when a race condition occurs, among the arithmetic circuits corresponding to the conflicting instructions, One of them is activated prior to execution of the operation, and a signal for inactivating the other operation circuits is sent to the preceding detection means.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of reducing the power consumption and speed of a functional circuit block, in particular, a microprocessor having an on-chip memory such as a cache memory.

Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention will be described by taking a microprocessor as an example.

  FIG. 1 shows a configuration of a microprocessor (MPU) according to a first embodiment of the present invention.

  In the figure, 100 is a single-chip MPU, but for convenience of explanation, only the components necessary for understanding the present embodiment will be described below, and the other parts will be omitted.

  In the figure, reference numeral 101 denotes a program counter which generates an instruction data read address in synchronization with a clock signal CLK. A memory address register 102 holds a read address of the instruction cache memory 103. An instruction data register 104 holds instruction data read from the instruction cache memory 103.

  Reference numeral 111 denotes another memory address register that holds a read or write address of the data cache memory 112. A memory data register 113 holds read data from the data cache memory 112 or write data to the data cache 112.

  The instruction data register 104 and the data register 113 are coupled to the internal data bus 172, and exchange data with the external data bus 161 via the input / output control circuit 160.

A first instruction decoder 120 decodes the output 105 of the instruction register 104 and outputs predetermined instruction control signals 121 and 122. An arithmetic unit 140 receives data necessary for the operation from the register file 150 via the internal bus 173, executes arithmetic operation, logical operation, shift operation, etc., and outputs the result via the internal bus 174 to the register file 150. Write to. In other cases, the calculation result is written to the memory address register 111 via the internal bus 175.

  The output 121 of the instruction decoder 120 specifies the content of the operation to the arithmetic unit 140. Further, the output 122 of the instruction decoder 120 designates a read / write operation for the register file 150.

  A second instruction decoder 130 interprets the output 105 of the instruction register 104, predicts, for example, memory access to the data cache 112, performs predetermined processing, and then performs a predetermined processing, and then issues a memory access notice signal 131 to the data cache 112. Is output.

The data cache 112 executes a predetermined memory access from this signal, an address signal from the memory address register 111, and a read / write control signal (not shown in the figure).

Note that the second instruction decoder 130 can also have a function of generating the operation start notice signals 132 and 133 as necessary, in addition to the arithmetic unit 140 and the register file 150.

  FIG. 2 shows a typical instruction execution stage of the MPU according to the present embodiment.

  In the figure, instruction 1 and instruction 2 indicate the execution stage of the RR operation (register-register operation).

  In the drawing, instruction data is fetched from the instruction cache 103 at the IF stage, decoded by the instruction decoder 120 at the D stage, and a predetermined operation is executed by the arithmetic unit 140 at the EX stage. Finally, the operation result is written to the register file 150 at the W stage.

  Next, it is shown in the middle of the figure. In the LOAD instruction and STORE instruction in which access to the data cache 112 occurs, the IF stage and D stage are the same as the above-described RR operation, but in the next AC stage, effective address calculation for accessing the data cache 112 is performed. And the data cache 112 is accessed at the next CA stage. Finally, in the W stage, the read data is written into the register file 150.

  As described above, in the LOAD / STORE instruction, the effective address calculation stage AC is always interposed between the decode stage D and the memory access stage CA. In this embodiment, memory access occurs at the D stage two stages before the CA stage. And an access notice signal is output to the cache memory 112.

  Next, FIG. 3 shows in more detail the operation timing from the fetching of this instruction to the generation of the access notice signal and the execution of the memory access.

In the figure, 3a is a system clock CLK, and this cycle is the same length as one stage of the instruction execution stage of FIG. 3, for example, 5 ns. 3b is IF stage, indicating that LOAD of M ₁ ~M ₅ in the figure, STORE instruction is fetched.

Reference numeral 3c denotes a D stage, which indicates that the LOAD or STORE instructions of M _{1 to} M ₅ are decoded in the stage subsequent to the IF stage.

3d is an AC stage, and execution addresses A _{1 to} A ₅ are calculated for the LOAD / STORE instructions M _{1 to} M ₅ decoded in the D stage 3c.

3e is a memory address A ₁ to A ₅ address calculation result, actual memory access CA stage 3f using this address is executed.

3g is a memory access prediction signal M ₁ ~M ₄ obtained by the second instruction decoder 130 shown in FIG. 1, is obtained as a result of decoding the M ₁ ~M ₅ of 3c in the D stage. 3h
Is a memory access notice signal 131 obtained by subjecting the 3g memory access prediction signals M _{1 to} M ₅ to predetermined processing, and is output to the data cache 112.

Here, the access warning signal 3h is generated prior to one stage prior to the actual memory access 3f E ₁ stage to be performed, similarly occurs prior to the previous one stage relative to Ea stage To do.

Here, FIG. 4A shows the internal configuration of the second instruction decoder 130 (see FIG. 1) that generates the memory access notice signal 131, and FIG. 4B shows its operation timing.

In the figure, reference numeral 410 denotes a memory access prediction circuit, which detects whether or not the instruction data output from the instruction register 104 is an instruction that accompanies memory access. Specifically, a LOAD instruction and a STORE instruction are detected, and a detection signal DET as indicated by 3g in FIG. 4B is generated.
Reference numeral 420 denotes a flip-flop that latches the detection signal DET3g with the clock signal CLK3a, and its output / Q4a becomes a signal as shown in FIG. 4B (where / Q represents an inverted output of Q). Reference numeral 430 denotes an inverter which inverts the output / Q4a of the flip-flop 420 to generate an access notice signal PR3h as shown in FIG.

  Although the polarity of the PR signal 131 is not essential, in the present embodiment, it is a positive active signal.

  Next, FIG. 5 shows an internal configuration of the data cache memory 112 (see FIG. 1).

  In the figure, reference numeral 510 denotes an address buffer which receives an address signal Ai and outputs it as positive and negative address signals necessary for the address decoder / driver 520. The output of the address decoder / driver 520 is output to the memory array 530 to select a memory array to be read or written.

A sense amplifier 540 amplifies a minute signal read from the memory array 530 to a predetermined signal level and outputs the amplified signal. An output driver 550 is provided to drive an output _Do having a relatively heavy load.

  A write control circuit 560 writes the write data Di to a predetermined address in the memory array 530 using the write control signal WE.

Reference numeral 570 denotes a current control signal generation circuit, which receives the access notice signal PR and generates at least one current control signal 575. In the present example, and if the data cache memory 112 is shared, in order also provides an example of such a case where there is access to factors other than the execution of the instructions, receiving a plurality of warning signal PR ₁ ... PR _n, at least A case where one or more current control signals 575 are generated is shown.

  The control of the circuit current by the current control signal 575 can be applied to all circuit elements except the current control signal generation circuit 570 in the cache memory 112. Which circuit is selected as a control target depends on the actual hardware configuration and application.

  FIG. 6A shows a configuration example of the current control signal generation circuit 570 (see FIG. 5), and FIG. 6B shows the operation timing thereof.

In the figure, reference numeral 610 denotes an OR gate, which takes the OR of the access notice signals PR _{1 to} PR _n and supplies the output to the inverter 620 and the flip-flop 660. Reference numeral 630 denotes a NOR gate which takes the NOR of the output of the inverter 620 and the / Q output of the flip-flop 630.
The signal PUP as shown in 6B of (B) is output.

Reference numeral 640 denotes an AND gate which takes an AND of the Q output 6b of the flip-flop 660 and the clock signal CLK3a and outputs an MCLK signal indicated by 6d in FIG. 6B. Also,
Reference numerals 650 and 670 respectively denote an OR gate and a delay circuit. The OR gate 650 takes an OR of the MCLK signal 6d and a signal obtained by delaying the MCLK signal by the delay circuit 670 for a predetermined time, and outputs a ΦSA signal indicated by 6f in FIG. 6B. Is output.

  Note that MA6e in FIG. 6B indicates the memory address of the memory access execution cycle.

As shown in FIG. 6B, memory access to the memory addresses A ₁ and A ₂ is performed at the stage 6g at t ₂ and t ₃ . 6c PUP signal contrast becomes rising, the falling down signal at the end of t ₃ stage 1 stage preceding t ₁ stage than t ₂ stages.

The circuit current is controlled based on the PUP signal 6c. This is shown in FIG. As shown by 7a in FIG. 7, based on the PUP signal 6c, the current of the target circuit is raised from i ₁ to a predetermined current value i ₂ during the t ₁ stage, and the memory access at t ₂ and t ₃ is performed. The current value is maintained in the stage, and the current value is lowered to a predetermined low current value i ₂ from the beginning of the t ₄ stage when the memory access is completed.

Next, the MCLK signal 6d (FIG. 6B) is a pulse signal generated corresponding to each of the memory access stages t ₂ and t ₃ , and is useful as a memory clock when realized by a clock synchronous memory. Refer to Documents 1) to 3) for the clock synchronous memory.
Reference 1) Kevin j. O'connor: Modular Embeded Cache Memory for a 32b Piplined RISC
Microprocessor.1987 IS SCC p.256, 257
2) Masanori Odaka et al: A 512 kb / 5ns BiCMOS RAM with 1KG / 150ps Logic Gate
Array.1989 IS SCC p.28, 29
3) Masayoshi Kimoto et al: A 1.4ns / 64kb RAM with 85ps / 3688 Logic Gate Array.1
989 CI CC p.15.8.1〜15.8.4
Further, the ΦSA signal 6f is a pulse signal generated corresponding to each of the memory access stages t ₂ and t ₃ , and is useful, for example, as a signal for causing the sense amplifier to pulse for a predetermined period.

  In other words, by independently controlling activation of only the sense amplifier, the power supply noise caused by current switching can be kept within an allowable range, and used as a signal that shortens the activation time of the sense amplifier that is a high power consumption source as much as possible. Can do.

  An example in which the circuit current is actually controlled using the above PUP signal and ΦSA signal is shown below.

  First, FIG. 8A shows a first example of a circuit for controlling the circuit current using the PUP signal, and FIG. 8B shows its operation waveform.

In the figure, reference numerals 811 and 812 denote PMOSs, each source being connected to the power source V ₁ , and each gate being commonly connected and also connected to the drain of the PMOS 811. 821
, 822 and 823 are NMOSs, the drain of 821 is connected to the drain of the PMOS 811, the gate is connected to the PUP signal, and the source is connected to the reference potential.

  The drain of the NMOS 822 is connected to the drain of the PMOS 812, the gate is connected to the output of the inverter 830, the source is connected to the reference potential, and the input of the inverter 830 is connected to the PUP signal.

  Reference numeral 840 denotes an active circuit such as a differential amplifier, which is provided in a functional circuit block such as the data cache memory 112, the arithmetic unit 140, and the register file 150 (see FIG. 1). A predetermined operating current determined by the constant current source 850 is supplied. Further, an integrating capacitor C is connected between the gate of the NMOS 823 and GND.

The PMOS 811 and 812 and the NMOS 821 and 823 constitute a current mirror circuit. As shown in FIG. 4B, when the PUP signal rises from the “0” level to the “1” level, the PMOS 812 supplies the capacitor C with a predetermined value. The gate voltage Vg of the NMOS 823 and the current i of the circuit 840 rise gently at a predetermined slew rate as shown in the middle and lower stages of FIG. The rise time t ₁ is a time corresponding to the stage t ₁ shown in FIG.

Similarly, when the PUP changes from the “1” level to the “0” level, the voltage Vg and the current i fall gently at a predetermined slew rate, and this fall time t ₄ similarly corresponds to t ₄ shown in FIG. It will be time.

Note that the rise time t ₁ and the fall time t ₄ of the current i are not necessarily the same, and after the operation of the circuit is completed, when it is lowered, t ₄ is shortened within a range in which no special inconvenience occurs. You can also

  FIG. 9A shows a second example of a circuit for controlling the circuit current using the PUP signal, and FIG. 9B shows its operation waveform.

In the figure, 911 to 914 are inverters, 921 to 923 are NMOSs, 931 to 933 are constant current sources, 940 is an active circuit such as a differential amplifier, for example, the data cache memory 112, the arithmetic unit 140, the register file 150 ( This is provided in a functional circuit block such as FIG.

Here, when the delay times of the inverters 912 to 914 are designed to increase in the order of 914, 913 and 912, when the PUP signal changes from “0” to “1” level as shown in FIG. Currents i _{1 to} i ₃ flowing through 923 also rise with a predetermined time difference, and active circuit 940
The operating current rises stepwise up to a steady current of i ₁ + i ₂ + i ₃ after time t ₁ .

Similarly, when the PUP signal changes from “1” to “0” level, the circuit current of the active circuit 940 falls in a stepped manner within the time t ₄ , which is effectively gentle as in the embodiment of FIG. Current change can be obtained.

The rise time t ₁ and fall time t ₂ correspond to the times of the stage t ₁ and the stage t ₄ in FIG. 7 as in the first example.

The example in which the circuit current is actually controlled using the PUP signal and the ΦSA signal has been described above. However, the present embodiment is not limited to this, and other general methods for controlling the circuit current are used. This embodiment can also be realized.

  Hereinafter, an example of the circuit current control in each part of the data cache memory 112 (see FIG. 1) will be described taking the case of using the first circuit current control circuit as an example.

  FIG. 10 shows an embodiment of current control of the address buffer indicated by 510 in FIG.

  In the figure, 1011 to 1014 are NPN transistors, 1021 and 1022 are resistors, 1031 to 1033 are NMOSs, and 1041 to 1043 are constant current sources.

The emitters of NPN 1011 and 1012 are connected in common and connected to the constant current source 1041 via the NMOS 1031. The bases of NPNs 1011 and 1012 are connected to an address signal Ai and a reference power source V _R , respectively, and their collectors are connected to a power source V ₁ via resistors 1021 and 1022. The collectors of NPN1013 and 1014 are connected to the power supply V ₁ and their bases are
It is connected to the collector of NPN1011 and the collector of NPN1012. The emitters of NPNs 1013 and 1014 are connected to constant current sources 1042 and 1043 via NMOSs 1032 and 1033, respectively.

  The output / ai is taken out from the emitter of the NPN 1014 as a non-inverted output of the input Ai, and the output / ai is taken out from the emitter of the NPN 1013 as an inverted output of the input Ai. The gates of the NMOSs 1031 to 1033 are commonly connected to the control signal Vg. The control signal Vg corresponds to the signal Vg shown in FIG.

Here, the NPN 1011, 1012, the resistors 1021, 1022 and the constant current source 1041 constitute a differential amplifier. When the current control signal Vg is “1” level and the address signal Ai is higher than Vg, the NPN 1011 is ON, NPN1012 is OFF, NPN1011 collector is at “0” level, N
The collector of PN1012 becomes “1” level.

  The collector of the NPN 1011 is connected to the base of the emitter follower transistor 1013, and an “0” level output / ai can be obtained from the emitter. Similarly, the collector of the NPN 1012 is connected to the base of the emitter follower transistor 1014, and a "1" level output / ai can be obtained from the emitter.

When the address signal Ai is lower than V _R , the NPN 1011 and the NPN 1012 operate in reverse, the / ai output becomes “1” level and the ai output becomes “0” level.

Next, when the current control signal Vg is at the “0” level, the NMOSs 1031 to 1033 are all turned off. At this time, there is no current path from the power source V ₁ to the GND, so this circuit does not consume power.

  Here, since the current control signal Vg is set so that the rise and fall times become a predetermined time as shown in FIG. 8B, the current change is also as shown by 7a in FIG. It can be gentle.

  Therefore, the power supply and the GND noise (see FIG. 24B) at the time of current switching as shown in FIG. 24B can be suppressed to a desired magnitude.

  Next, FIG. 11 shows an example of circuit current control of the decoder / driver 520, memory array 530, and sense amplifier 540 (see FIG. 5) in the data cache memory.

  In the figure, reference numerals 1161 and 1162 denote NOR gates, which correspond to the final stage of the address decoder.

Reference numerals 1171 and 1172 denote word drivers composed of AND gates. The outputs of the address decoders 1161 and 1162 are connected to one input, the control signal Vg is connected to the other input, and the output causes the word lines WL ₁ and WL ₂ to be connected respectively. To drive.

  Although 1100 is not particularly limited, it is a 4MOS type memory cell, and only one cell is shown for convenience of explanation.

Reference numerals 1111 and 1112 denote load MOSs for bit line pull-up. 1113-
Reference numeral 1116 denotes a MOS switch for bit line selection. A desired bit line is coupled to the common data line 1120 by column selection signals C ₁ and C ₂ .

1121 and 1122 are emitter follower circuits using NPN transistors, and the level of the signal on the common data line 1120 is shifted by VBE (base-emitter voltage).
Tell NPN 1123 and 1124 bases. The emitters of NPNs 1123 and 1124 are connected in common and connected to a current source 1151 through an NMOS 1141. The collectors of NPNs 1123 and 1124 are connected to the power source V ₁ through resistors 1131 and 1132.

NPNs 1123 and 1124, resistors 1131 and 1132, and current source 1151 constitute a differential amplifier, which amplifies a minute signal read from memory cell 100 to a predetermined amplitude. Similarly, reference numeral 1150 constitutes a differential amplifier composed of two resistors and two NPNs, and is connected to a constant current source 1152 via an NMOS 1142.

  The two inputs 1150 are connected to the collectors of NPNs 1123 and 1124, and these signals are further amplified to obtain an output signal having a predetermined amplitude at a terminal 1151.

Here, since the above-described current control signal Vg (see FIG. 8) is connected to one input of the AND gates 1171 and 1172, the AND gate 1171 when the Vg is at the “1” level.
, 1172 are selectively driven to selectively drive the word lines WL ₁ , WL ₂ . On the other hand, when Vg is at "0" level, all word drivers including AND gates 1171 and 1172 are turned off. Accordingly, at this time, the current flowing into all the memory cells including the memory cell 1100 is cut off. Therefore, useless power consumption in a state where no memory is accessed is cut.

Similarly, a current control signal Vg is connected to the gates of the NMOSs 1141 and 1142. The NMOSs 1141 and 1142 are turned on when Vg is “1” level, and are turned off when Vg is “0” level.

  Accordingly, since the sense amplifier current does not flow in a state where no memory is accessed, useless power consumption is cut.

  Here, since the change in the circuit current due to the current control signal Vg is as shown in 7a of FIG. 7, not only the noise of the power supply and GND due to the current switching can be suppressed to an allowable value, but also at the start time of the memory access. Since the noise has disappeared, high speed operation is possible.

In FIG. 11, when the switch SW1180 is switched to the signal ΦSA side, the NMOSs 1141 and 1142 are operated in a pulse manner. As described above (see FIG. 6B), the ΦSA signal is a pulse signal that becomes “1” level for a predetermined time in the memory access stages t ₂ and t _{3. In} this example, the ΦSA signal is only for a certain time during memory access. Since power is supplied to the sense amplifier, power can be reduced.

  Next, FIG. 12 shows an example of circuit current control of the output driver 550 (see FIG. 5) of the data cache memory 112.

In the figure, the drain, gate and source of the PMOS 1211 are connected to the base, input V _IN and power source V ₁ of the NPN 1241, respectively. The drain, gate, and source of the NMOS 1221 are connected to the base of the NPN 1241, the input V _IN , and one end of the resistor 1251, respectively. The drain, gate, and source of the PMOS 1222 are connected to the drain of the NMOS 1221, the bases of the current control signals Vg and NPN1241, respectively. A capacitor 1261 is connected to both ends of the resistor 1251. The anode and cathode of the diode 1231 are connected to the collector and base of the NPN 1241, respectively, and the power source V ₁ is connected to the collector of the NPN 1241. The emitter of NPN1241 is an output terminal, between the output terminal and the power supply V ₂ terminating resistor 1252 is connected.

Now, when the current control signal Vg is at “1” level, the PMOS1222 is OFF. At this time, if the input V _IN is “0” level, the PMOS 1211 is turned on and the NMOS 1221 is turned off.

Accordingly, at this time, the base voltage of the NPN 1241 is raised via the PMOS 1211 and the output V _OUT becomes the “1” level. Conversely, when V _IN is at the “1” level, the PMOS 1211 is turned off and the NMOS 1221 is turned on, the base voltage of the NPN 1241 is lowered, and the output V _OUT becomes the “0” level.

  The diode 1231 is a clamper for suppressing a decrease in the base potential of the NPN 1241 to a predetermined value.

  The resistor 1251 is for current limiting, and the capacitor 1261 is for speeding up.

Next, when Vg is at the “0” level, the PMOS 1222 is turned on. At this time, the base potential of the NPN 1241 is pulled down regardless of the level of the input V _IN , and the output V _OUT becomes the “0” level. Therefore, the collector voltage V _{OUT of the} NPN 1241 becomes smaller than that at the “1” level, and power consumption can be reduced.

  Therefore, the same effect as the circuit current control of the address buffer 510, the decoder / driver 520, the memory array 530, and the sense amplifier 540 described above can be obtained.

As described above, the example of the circuit current control in each part of the data cache memory 112 (see FIG. 1) has been shown taking the case of using the first circuit current control circuit as an example. The circuit current control circuit (see FIG. 9) or other circuit current control circuit may be used.

  As described above, in this embodiment, the description has been made mainly on the example of reducing the power consumption by the memory access method using the access notice signal. However, as described above, for example, an instruction such as an arithmetic unit or a register file in a single chip MPU. The same applies to all functional circuits whose operation is controlled by word interpretation. In this embodiment, the example in which the circuit current is started up in synchronization with the previous stage of the operation execution stage has been described. However, this is not necessarily required to be synchronized. The start-up may be started prior to the start of the execution stage for a time during which the noise can be suppressed to a predetermined value. In this case, the PUP signal may be made a significant signal at a desired timing, not in synchronization with the previous stage of the execution stage.

  As described above, according to the present embodiment, the memory circuit and other functional circuits included in the single-chip microprocessor are started up at a predetermined rate before the operation is started by the access notice signal prior to the actual operation. A predetermined operation is executed. For this reason, these functional circuits consume power necessary for circuit performance only when they are actually operated, which is effective in reducing the power consumption of a single-chip microprocessor.

  In addition, new functions can be added as much as power is reduced, which is effective for higher functionality and higher integration.

  Also, since each functional circuit can change the circuit current at a predetermined rate, the noise of the power supply and the ground line due to the current change can be suppressed to a predetermined value. For this reason, there is an effect that a highly reliable circuit operation can be realized.

  Furthermore, in each functional circuit to which this embodiment is applied, since the noise of the power supply line and the ground line disappears at the time of starting actual operation, it can operate in the best power supply state, and the high speed of the circuit It is also effective for operation.

  Next, the case where the present invention is applied to a Super Scalar type RISC processor will be described.

  The Super Scalar type RISC processor is mainly equipped with multiple arithmetic units that share register files, simplifying instructions to reduce the number of pipeline stages, and reading multiple instructions in one machine cycle. Is to control. That is, since a plurality of instructions are simultaneously read and executed in one machine cycle, a plurality of arithmetic units can operate at the same time, thereby increasing the processing capability.

FIG. 13 is an instruction list of the processor described in the second embodiment. These instructions are roughly classified into basic instructions, branch instructions, load / store instructions, and system control instructions. For convenience of explanation, the number of instructions is limited as described above for the sake of simplicity. However, this does not limit the present invention, and more instructions may be added.

FIG. 14 shows the configuration of the second embodiment. 1400 is a memory interface, 1401 is a data cache, 1402 is a sequencer, 1403 is an instruction cache, 1404 is a 32-bit first instruction register, 1405 is a 32-bit second instruction register, 1406 is a first decoder for the first instruction, 1408 is a second decoder for a first instruction, 1409 is a second decoder for a second instruction, 1407 is a first decoder for a second instruction, 1413 is a conflict detection circuit between the first and second instructions, Reference numeral 1410 denotes a first arithmetic unit, 1412 denotes a second arithmetic unit, and 1411 denotes a register file. In this embodiment, a maximum of two instructions are read and executed in parallel during one machine cycle. FIG. 15 shows the most basic operation of the pipeline processing in this embodiment. Pipeline is IF (Instruction Fetch), D (Decode)
, EX (Execution), T (Test), and W (Write).

  Next, the operation will be described with reference to FIG. In the IF stage, two instructions pointed to by the program counter in the sequencer 1402 are read from the instruction cache 1403 and set in the first instruction register 1404 and the second instruction register 105 through the buses 1415 and 1417, respectively.

In the D stage, the contents of the first instruction register 1404 are decoded by the first decoder 1406, and the contents of the second instruction register 1405 are decoded by the second decoder 1407. As a result, the contents of the register pointed to by the first source register field of the first instruction register 1404 are sent to the first arithmetic unit 1410 via the bus 1425 and the contents of the register pointed to by the second source register field are sent to the first arithmetic unit 1410 via the bus 1426. Is done. The contents of the register pointed to by the first source register of the second instruction register are sent to the second arithmetic unit 1412 via the bus 1427 and the contents of the register pointed to by the second source register field are sent to the second arithmetic unit 1412 via the bus 1428.

Next, the operation of the EX stage will be described. In the EX stage, in accordance with the contents of the operation code of the first instruction register, the first arithmetic unit 1410 performs an operation between the data sent via the buses 1425 and 1426. In parallel, according to the contents of the operation code of the second instruction register 1405, the second arithmetic unit 1412 performs an arithmetic operation between the data sent via the buses 1427 and 1428. The load / store instruction performs address calculation here.

  Next, the operation of the T stage will be described. In the T stage, the basic instruction continues to hold data. In this stage, the load / store instruction executes memory access to the data cache 1401 based on the address calculated in the previous EX stage based on the address output through the bus 1429 or the bus 1431. In the case of a store instruction, data to be stored simultaneously is output through the path 1437.

  Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 1410 is stored through the bus 1429 in the register pointed to by the destination field of the first instruction register. Also, the operation result of the second operation unit 1412 is stored through the bus 1431 in the register pointed to by the destination field of the second instruction register. Further, in the case of a load instruction, it is stored through the bus 1430 into a register pointed to by the destination field in the load instruction.

  FIG. 15 shows a flow of processing basic instructions continuously. Two instructions are processed per machine cycle. In this example, the case where the first arithmetic unit and the second arithmetic unit are always operating in parallel is illustrated.

  However, depending on the combination of the first instruction and the second instruction, both instructions may not be executed simultaneously. This is called competition.

  For example, a register pointed to by the destination register field of the first instruction, a register pointed to by the first source register field of the second instruction, or a register pointed to by the second source register field S2 of the second instruction It is time to match.

When such a conflict occurs, the hardware is controlled to execute the instruction in the first instruction register over one machine cycle, followed by the second instruction register in the next one machine cycle. . That is, both the first instruction and the second instruction are executed over one machine cycle. FIG. 16 shows a pipeline when there is a conflict. In this example, both the first instruction and the second instruction are addition instructions. Considering the two instructions at address 2, the first instruction adds the contents of the registers R (1) and R (2), and the register R (1 3), and the second instruction adds the contents of the register R (4) and the register R (3) and stores the result in the register R (5). Here, there is a conflict with the destination register R (3) of the first instruction and the source register R (3) of the second instruction. In such a case, as shown in FIG. 16, each instruction is executed every machine cycle.

  In other words, by executing the first instruction on the PC 2 and invalidating the second instruction executed in parallel, then invalidating the first instruction in the next cycle and executing the second instruction executed in parallel. realizable. It should be noted that a short path, which has been well known in the past, may be used for the collision between the destination and the source when shifted by one cycle.

  As shown in FIG. 14, the Super Scalar type RISC processor has two arithmetic units, and only one of the arithmetic units is always used in the case of the above-mentioned competition. The remaining arithmetic units are processing meaningless.

  In the Super Scalar type RISC processor, when various types of competition are found, it is important to detect and activate the used arithmetic unit prior to the start of operation. This will be described in detail with reference to FIG. After the first instruction and the second instruction are read in the IF stage, various conflict checks between the first instruction and the second instruction are performed in the conflict detection circuit 1413 in the D stage.

  If it is recognized that a conflict has occurred after various conflict checks, the operation unit is executed only by one of the operation units. Therefore, the operation unit to be used may be activated through the signals 1432 and 1433.

  If there is no contention, both arithmetic units are activated. The activated arithmetic unit is continuously activated if the control signal for the next machine cycle conveys activation in the second half of one machine cycle. If the activation is not transmitted, the arithmetic unit is deactivated after the machine cycle is completed.

Describe in detail the case of conflict. When the conflict detection circuit for the first and second instructions detects a conflict, the first instruction unit first executes the first instruction. Therefore, the first arithmetic unit is informed of the activation by the control signal 1435 via 1433 and activated. Is done. At the same time, the second arithmetic unit is informed by the control signal 1436 that it is not activated via the control signal 1432. For this reason, the second arithmetic unit remains inactive, that is, low power consumption.

  At this time, the signal 1434 notifies the sequencer 1402 that a conflict has been detected.

In order to execute the second instruction in the next cycle, the first arithmetic unit is informed by the control signal 1435 via 1433 that it is not activated. For this reason, the first arithmetic unit becomes inactive. At the same time, the second arithmetic unit is informed by the control signal 1436 via the control signal 1432 that it is activated.

  As described above, as in this embodiment, when various conflicts are found in the simultaneous processing of two instructions, an arithmetic unit that is not activated by detecting and activating the arithmetic unit to be used prior to the start of operation. Can reduce power consumption, and has the effect of reducing overall power consumption.

  17 to 19 show the first arithmetic unit 1410, the second arithmetic unit 1412, and the register file 1411 extracted from FIG. 14, and the connection relationship is omitted.

FIG. 17 shows a circuit using at least one or more differential inputs for the first and second arithmetic units, for example, an ECL circuit. Super composed of such arithmetic units
In the Scalar type microprocessor, when a conflict is detected, each machine cycle is executed. Therefore, the first or second arithmetic unit to be actually used is activated by a signal line 1435 or 1436 in advance. However, the remaining non-activated computing units are kept in a state where the current flowing through the current source is reduced or not flowing, so that the power is not supplied. Do not consume.

  18, FIG. 19, and FIG. 20 show a circuit that takes logic between the base and emitter of at least one or more bipolar transistors in the first and second arithmetic units, for example, an ECL circuit or a BiCMOS circuit. . This circuit configuration itself is described in detail in Japanese Patent Application Laid-Open No. 60-175167. This circuit has the disadvantage that when the bipolar transistor is ON, a direct current flows and power increases. For this reason, it is effective not to consume the power of the arithmetic units that are not used when competition or the like occurs. The control method is the same as that described in FIG.

  The difference between FIG. 18 and FIG. 19 is that the method for reducing power is different. In FIG. 18, a P-channel MOS transistor is inserted between the collector side of the bipolar transistor and Vcc. When this P-channel MOS transistor is turned on, it is in an operating state, and when it is turned off, it is in an inactive state. .

  In FIG. 19, although the circuit is in an operating state, when the signal 1435 or 1436 is turned ON, the bipolar transistor is forcibly turned OFF, and the collector-emitter current of the bipolar transistor is not allowed to flow. This means that the direct current is forcibly cut, thereby reducing the power consumption.

  FIG. 20 shows the first arithmetic unit 1410, the second arithmetic unit 1412, the register file 1411 of FIG. 14, and the clock distribution system that takes their timing. A notable point in the distribution system of FIG. 20 is the clock driver A in the distribution system.

  The clock driver A supplies clocks independently only to the first arithmetic unit 1410, the register file 1411, and the second arithmetic unit 1412, respectively. In a Super Scalar type microprocessor composed of arithmetic units including such a distribution system, when a conflict is detected, it is executed every machine cycle, but the first or second arithmetic unit that is not actually used is The signal line 1435 or 1436 is controlled to stop the clock to a specific area of the clock distribution system. As a result, the logic below the clock distribution system supplied to each block is fixed. That is, either one of the two arithmetic units is supplied with a clock and is operating, but the other one arithmetic unit is not supplied with a clock.

  A CMOS circuit or a BiCMOS basic circuit has complementary characteristics and normally consumes very little power, but consumes power during a transition period when input data changes. Stopping the supply of the clock means that the logic is fixed and does not change. For this reason, there is an effect that power consumption can be reduced, and the control method of FIG. 20 is effective for a configuration including an arithmetic unit including a CMOS circuit and a BiCMOS basic circuit.

  As described above with reference to FIG. 17 to FIG. 20, it is possible to reduce the power consumption in the inactive state corresponding to the circuit format constituting the arithmetic unit. It is obvious that the power consumption can be reduced corresponding to each of the configurations of the arithmetic units by combining the circuit formats shown in FIGS.

In the present embodiment, there are those that cannot be processed simultaneously by a combination of conflicts between registers (for example, a combination of a load instruction and a load instruction). As an example, FIG. 21 shows the combination. However, the combination is determined by hardware implementation and is not directly related to the present invention. That is, when one or more combinations are restricted in the combination shown in FIG. 21, a conflict due to the combination of instructions is established.

Further, returning to FIG. 14, the contention detection circuit 1413 and the decoders 1406, 1408,
Other operations 1409 and 1407 will be described as a third embodiment.

In the example described above, when various types of conflicts are found, detection and activation are performed prior to the start of the operation of the arithmetic unit to be used. However, in the third example, various types of conflicts are found. At this time, the computing unit which is not used is detected and inactivated prior to the start of the operation. This situation will be described in detail with reference to FIG. After the first instruction and the second instruction are read out in the IF stage, various conflict checks between the first instruction and the second instruction are performed in the conflict detection circuit 1413 between the first instruction and the second instruction in the D stage. Done. After various conflict checks, it is recognized that a conflict has occurred, but since it is executed by only one arithmetic unit, the remaining arithmetic units may be deactivated through signals 1432 and 1433. In other words, when the conflict detection circuit between the first and second instructions detects a conflict, the first instruction is executed first. However, the second instruction invalidates the first decoder for the second instruction by the signal 1432 and performs the second operation. The unit is deactivated through control signal 1436. At this time, the signal 1434 notifies the sequencer 1402 that a conflict has been detected. In the next cycle, the first decoder for the first instruction is invalidated by the output 1433 of the conflict detection circuit, and the first arithmetic unit is inactivated through the control signal 1435. In parallel with this, the second instruction is executed. The deactivated arithmetic unit is controlled so as to be activated again in the second half of one machine cycle, so that subsequent instructions can be executed.

  As described above, in the simultaneous processing of two instructions as in the present embodiment, it is detected whether or not there is a conflict between two instructions that may be executed at the same time. This has the effect of reducing the overall power consumption.

  17 to 19 show the first arithmetic unit 1410, the second arithmetic unit 1412, and the register file 1411 extracted from FIG. 14, and the connection relationship is omitted. The manner of low power consumption for each arithmetic unit is the same as in the second execution example.

  In a Super Scalar type microprocessor configured with such an arithmetic unit, when a conflict is detected, each machine cycle is executed, but the first or second arithmetic unit that is not actually used is a signal line 1435 or 1436. To reduce the power consumption of the unused one. At this time, the first or second arithmetic unit that is actually used continues to flow a current of a value provided for the intended operation from the current source. That is, either one is controlled so that a predetermined current continues to flow and the remaining one reduces power consumption.

  As in the case of the second embodiment, it is obvious that the power consumption can be reduced correspondingly in the configuration of the arithmetic unit by the combination of the circuit formats of FIGS.

In this embodiment, the conflict between the registers has been described. As other conflicts, as described in the previous second embodiment, those that cannot be processed simultaneously by a combination of instructions (for example, a load instruction and a load instruction) For example). FIG. 21 shows an example of the combination. However, the combination is determined by hardware implementation and is not directly related to the present invention as described in the second embodiment. One or more combinations are shown in FIG. When there is a restriction on the combination of instructions, a conflict due to the combination of instructions is established.

Furthermore, in the present embodiment, the combination of basic instructions has been described. However, when using data loaded by an instruction immediately following a branch, instruction, or load instruction (this is called a load use), there is no arithmetic unit. There is a case to do meaningful processing. Also in this case, the present invention is effective. FIG. 22 shows a branch instruction, and FIG. 23 shows a load use. These operations are omitted because they can be easily analogized.

  Furthermore, when an instruction that does not actually operate the arithmetic unit, such as a NOP instruction or a system control instruction, is detected, the detected arithmetic unit can be deactivated.

  In FIG. 14, a first instruction second decoder 1408 and a second instruction second decoder 1409 are circuits that detect by decoding an instruction as to whether or not each instruction actually operates the arithmetic unit.

  When detected by the second decoder for first instruction 1408, the first arithmetic unit 1410 is deactivated through the signal line 1435, and when detected by the second decoder for second instruction 1409, the second arithmetic unit 1412 is deactivated through the signal line 1436. Activate. As a result, the power consumption of the arithmetic unit can be reduced.

Furthermore, this embodiment is also effective in another Super Scalar type control method described for a two-instruction Super Scalar type microprocessor, and is not limited to two instructions, and has a simultaneous processing function for a plurality of instructions. Valid for the processor. Needless to say, the present invention is not limited to a RISC processor, and can be applied to a CISC processor.

  In the present embodiment, the single-chip microprocessor has been described as an example. However, in other semiconductor integrated circuit devices such as a one-chip LSI, the functional circuit predicts the start of the operation of each functional circuit block. A similar effect can be obtained by controlling the circuit current of the block. In this case, the operation start prediction method and the circuit current control timing are in accordance with the configuration and application of the device to be applied, but the operation start is predicted prior to the operation start, so that no malfunction caused by current switching or the like occurs. This is not different from the essence of the present embodiment in that the functional circuit block is activated for a certain period of time before the start of the operation, thereby ensuring low power consumption and normal operation, and thus increasing the speed of the apparatus.

  Furthermore, this embodiment can be similarly realized not only in a semiconductor integrated circuit but also in a general electronic circuit.

1 is a block diagram showing a configuration of a microprocessor according to a first embodiment of the present invention. FIG. 3 is an explanatory diagram showing an instruction execution stage of a microprocessor. The figure which shows the timing chart which shows the operation timing of a microprocessor. The figure which shows the timing chart which shows the block which shows the structure of an access warning signal generation circuit, and its operation | movement. The block diagram which shows the structure of a cache memory. The figure which shows the timing chart which shows the circuit which shows a current control signal generation circuit, and its operation | movement. The figure which shows the time chart which shows the relationship between an access warning signal and power supply current. The figure which shows the block which shows the structure of a current control signal generation circuit, and the timing chart which shows the operation | movement. The figure which shows the timing chart which shows the block which shows a current control signal generation circuit, and its operation | movement. A circuit showing the configuration of the address buffer. The block diagram which shows a memory cell peripheral circuit. The circuit diagram which shows an output drive circuit. The figure which shows a command list. The block diagram which shows the structure of the microprocessor which concerns on a 2nd Example. Explanatory drawing which shows the instruction execution stage of the microprocessor shown by 2nd Example. Explanatory drawing which shows the instruction execution stage of the microprocessor at the time of various competition. The figure which shows the circuit example in an arithmetic unit. The figure which shows the other circuit example in an arithmetic unit. The figure which shows the other circuit example in an arithmetic unit. The figure which shows the circuit of the distribution system of the clock signal supplied to an arithmetic unit. Explanatory drawing which shows the combination rule of the instructions in 2 instructions simultaneous processing. Explanatory drawing which shows the instruction execution stage of a branch instruction. Explanatory drawing which shows the instruction execution stage at the time of load use. Explanatory drawing which shows the relationship between the change of a circuit current, and a noise voltage.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Program counter, 102 ... Memory address register, 103 ... Instruction cache memory, 104 ... Instruction data register, 111 ... Memory address register, 112 ... Data cache memory, 113 ... Memory data register, 120 ... First instruction decoder, 130 ... second instruction decoder, 140 ... arithmetic unit, 150 ... register file, 160 ... input / output control circuit, 410 ... memory access prediction circuit, 570 ... current control signal generation circuit,
940 ... Active circuit, 1100 ... Memory cell, 1150 ... Sense amplifier.

Claims (4)

A function circuit block having a power supply system inductance L, an allowable power supply noise V _n , and a circuit current switching width ΔI, and means for generating an operation start notification signal for activating the function circuit block in advance by time T And T, L, V _n and ΔI are

A semiconductor integrated circuit device satisfying the following relationship:   Receiving a warning signal that predicts the start of operation, increasing the circuit current to a predetermined value over a predetermined time from the time of receiving the warning signal, shifting the operation mode from the low power consumption mode and executing the operation A functional circuit block characterized by having a function of reducing the circuit current to the low power consumption mode over a predetermined time and shifting to the low power consumption mode after completion of.   A memory which is activated by an access notice signal for giving a notice of access and executes a predetermined memory operation based on an address signal, a read / write control signal and a data input / output signal.   An information processing apparatus comprising at least one of the semiconductor integrated circuit device according to claim 1, the functional circuit block according to claim 2, and the memory according to claim 3.

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