JP2858137B2 - Computer output device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly, to a logic circuit used in a computer device to perform switching between output display frames very quickly. It is about.

[Conventional technology]

As computer devices, such as workstations, have become increasingly sophisticated, it has become apparent that computer devices can be conveniently used to obtain animation features that can be combined with movies and televisions. Computers that can provide animated outputs provide different advantages over television and cinema because they can construct and modify animated displays differently than other computers. The performance of computers capable of providing three-dimensional displays has increased and accelerated the demand for devices capable of handling objects to be animated.

[Problems to be solved by the invention]

A major problem in using a computer to obtain an animated output is that it requires the display of frames that change in small increments and that are mutually adjacent in a rapid sequence. In order to display one frame of graphic material on a cathode ray tube (CRT), it is necessary to store an instruction for each position (pixel) to appear on the cathode ray tube or other information display device. On large, sharp displays, the number of pixels on the cathode ray tube averages about 10 pixels horizontally.
Since there are 00 pixels and the same number in the vertical direction, the total number of pixels for information to be stored is about 1 million. In a preferred device capable of displaying several colors and shades on a cathode ray tube, each of those pixels contains 24-bit digital information specifying a particular color output. Therefore, it is necessary to store about 24 million bits of information for each frame to be output.

However, it takes not only long enough to write about 24 million bits into each storage location of a frame that is supplied as an output to the cathode ray tube, but also to write those bits to supply the next frame. It takes more time to clear. Delays between frames are avoided by using a double buffered device provided with two full screen bit mapped memories and alternately switched to the output of a cathode ray tube. The device greatly reduces the time between the presentation of two information frames, but does not eliminate the need to quickly clear each display memory so that it can be written to the next frame. . Thus, even such a double buffered device is too slow to provide optimal output for animation.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the speed at which an image is switched frame by frame or at the output terminal of a computer output device.

It is another object of the present invention to eliminate most of the delay associated with clearing display memory between frames in a computer device.

It is another object of the present invention to eliminate the need to clear display and depth memory between frames in a computer device.

Still another object of the present invention is to improve the operation speed of a computer device.

[Means for solving the problem]

The present invention substantially eliminates the time normally required to clear a display device in a computer device,
An object of the present invention is to improve the speed at which individual frames can be switched to the output terminal of a computer device. The apparatus does so by providing a double-buffered frame identification memory for storing stored frame instructions corresponding to information in an associated display memory. Each pixel in the display memory has an associated corresponding pixel in the frame identification memory.

When reading out the frame written in the display memory, the output frame register supplies an indication of the frame to be read out as a frame number, and as the frame identification memory and the display memory are scanned for refreshment of the cathode ray tube, the frame number is displayed. The frame number is compared with the value of each pixel in the frame identification memory. Only the pixels in the selected frame are supplied as output from the display memory to the cathode ray tube.
For those pixels where the number in the output frame identification register is not compared to the number in the frame identification memory, the background color generator is activated to provide information to the cathode ray tube. Thus, by erasing only a small portion of the frame identification memory without erasing the display memory, writing from frame to frame in the display memory can be continued.

To be able to accurately represent a three-dimensional graphic on a two-dimensional output display, additional logic is provided to determine the depth at which pixels of a particular frame are written along the Z-axis. The present invention allows the use of Z-buffers from frame to frame without erasing the Z-buffers. In addition, another similar logic device is provided to determine the window in which to write the pixels of a particular frame so that the same device can handle the window.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

Frame Identification First, reference is made to FIG. 1, which illustrates a display output device 10 for rapidly processing information in accordance with the present invention. For purposes of this description, a particular graphic or data structure that one wishes to display as a full screen representation on a cathode ray tube (CRT) or other computer output device may be included.
The output device 10 operates under the control of a central processing unit (CPU) (not shown in FIG. 1).

When it is desired to write a particular graphic frame to an output device such as CRT 12, the actual information to be displayed is written to the display memory. The output device 10 has a first display memory A (13) and a second display memory B (14). By using two display memories in parallel, it is possible to quickly switch between the frames of the display required for performing the animation. The output of those memories is multiplexer 15
Can be selected with. In the actual case, a certain frame is written into the display memory A, during which the frame in the display memory B is supplied as an output to the cathode ray tube. Next, display memory A
Is supplied as an output to the cathode ray tube, during which a new frame is written into the display memory B.

In the conventional device, new information is stored in the display memories A and B.
Before writing, their display memories must be cleared so that they can be written to. When the display has a large number of pixels, and in this embodiment, each pixel stores 24-bit information, it takes a long time to clear it,
The operation of the device may be delayed to the point where its use in animation becomes impractical.

To reduce this time and provide the switching speed required for animation, the output device 10 of the present invention comprises an input frame identification (FID) register 16 and a pair of frame identification (FID) memories A (17). And B (18), an output frame identification (FID) register 19, a background color register 20,
And a control register 21. Each FID memory A, B is associated with one display memory A, B of similar name. Apparatus 10 also includes a multiplexer 22, a comparator circuit 23, a write enable logic circuit 24, and a logic circuit 25.

The operation of the device 10 is as follows. CPU is FID memory A
The value is written to the control register 21 using the host data bus in order to select which of (17) or B and the display memory A (13) or B (14) associated therewith is to be written.

Then the CPU supplies the frame identification number. The frame identification number is stored in the input FID register 16 used for all information to be written for the frame. In the preferred device, 16 frame numbers 0
~ 15 is used. After the input frame identification register is initialized, the actual information displayed on the output device is
The data is sent from the CPU to the selected display memory A or B.
Each of the display memories A and B is a memory in which full-screen pixels are mapped. Frame identification memories A and B are also memories in which full-screen pixels are mapped. Each frame identification memory receives an input from the input FID register 16 and supplies an output to the multiplexer 22. This allows the frame identification memory to be quickly switched to display the animated graphic image.

Each input information portion on the host data bus from the CPU carries a pixel address and color information (eg, RGB color values). Assuming that display memory A and FID memory A are selected, R
The GB color value is written to the appropriate pixel address in display memory A, and the frame identification number is written to the same pixel address in frame identification memory A. In a preferred device, the frame identification number requires 4 bits of storage for each pixel and RG
The B color value requires a 24-bit storage amount for each pixel.

Thus, when any particular complete frame is written to display memory A, display memory A contains the representation to be displayed in RGB color values at the addressed location selected for that particular frame. Write a triangle (as shown at the top left of CRT 12) to display memory A
Assuming to write to (FIG. 1), the color value for that triangle is placed in the appropriate pixel in display memory A and the triangle designation is placed in the same pixel in frame identification memory A as the identification number.

For example, if the triangle indication was stored as frame zero, the color indication would be provided to the display memory as a triangle and the number zero would be stored at the same triangle location in the associated FID memory. When it is time to display frame zero on the CRT, the CPU stores the frame identification number, in this case zero, in the output frame identification register 19 (again, a four bit register in the preferred embodiment) using the host data bus. The CPU is set so that multiplexers 22 and 15, which control the output of the frame identification memory and the output of the display memory, respectively, select the output of memory A. Next, as each pixel in display memory A is scanned to its output via its associated multiplexer, the frame identification value is also scanned from frame identification memory A for that particular pixel. Only at the position where the triangle is stored, the value from the frame identification memory is zero. Accordingly, the comparison circuit 23 for comparing the output from the selected frame identification memory with the output from the output frame identification register 19 supplies a signal indicating the pixel of the frame identification memory A in which the frame zero is written. . (Ie, a triangle with a frame identification number of zero). Thus, at the location where the frame identification memory A stores a zero frame number, the comparison circuit provides an equal output indicating a pixel that is part of the current frame. The RGB color signals stored in the pixels in the display memory A are supplied to the cathode ray tube via the logic circuit 25. On the other hand, for all pixels except those having a frame identification number of zero in frame identification memory A, comparison circuit 23 provides an unequal output indicating that the pixel is not part of the current frame. Then, the background color is supplied from the background color register 20 and sent to the cathode ray tube 12.

This device for processing signals has several significant advantages. For example, in this device, the color value may be stored only at the position in the display memory indicating the foreground data. The background color does not need to be stored in the display memory. Thus, the storage of information can be continued faster than in a conventional device in which each pixel needs to store 24-bit information. More importantly, to write the next frame to the display memory, it is not necessary to erase the display memory after the information for the frame has been read.

For example, after frame zero has been processed as described above, the next frame processed by a particular FID memory will have the next frame number (here frame number 1). Thus, the information written to the FID memory and the corresponding display memory need only be written over the information in those memories. The reason is that the display device
The RGB color information that is ultimately supplied to 12 is stored in the output FID register.
This is because only the information (in the display memory B) corresponding to the frame number 1 selected by 19 is used.

This device, which eliminates the need to clear the display memories A, B (13, 14), greatly increases the operating speed of the device and allows the quick switching required for animation.

The use of the FID memory F and the ID register allows the computer output device to function without having to clear the display memories A and B (13, 14) each time the frame changes, but the FID memories A and B ( 17,18) must undergo some form of clearing. In other words, the CPU only needs to send RGB color information to each display memory,
The clear information as well as the frame identification (FID) number information must be sent to the memory.

The total number of writable frames in a state where the FID memories A and B (17, 18) are not cleared with clear information is determined by the number of bits (4 bits in this embodiment) used for the frame identification number. If a 4-bit digital memory is used to record the frame number, a total of 16 frames can be used.
The memory needs to be cleared at least once. In addition,
The frame identification number is not limited to a 4-bit number,
The number of frames may be larger or smaller than 16. For example, if 3 bits are used, 8 frames can be used and 5 frames can be used.
In other words, 32 frames can be used by using the number of bits, and 64 frames can be used by using the number of 6 bits.

As the display memory A (13) and the display memory B (14) operate alternately, the FID memory A (17) and the FID memory B
(18) also operates alternately.

In the preferred embodiment, 16 frames are used (therefore, the frame numbers are 0, 1, 2,..., 15), and the CPU stores RGB color information for each frame in the display memory A.
(13) and are alternately written to the display memory B (14). For example, assuming that the RGB color information of frame zero is written in the display memory A (13) as described above,
The RGB color information is written to the display memory B (14), the RGB color information of frame 3 is written to the display memory A (13),
In this way, the display memory A (13) and the FID memory A (1
7) processes a total of 8 frames (here, called even-numbered frames) of 0,2,4,6,8,10,12,14, and displays memory B (14) and FID memory The pair with B (18) is 1,3,5,7,9,1
A total of eight frames of 1, 13, and 15 (here, referred to as odd-numbered frames) are processed. Both FID memories must be cleared at least once every 16 uses
Each FID memory must be cleared at least once for every eight uses.

As described above, if the number of pixels of the display device is, for example, 1000 in each of the vertical and horizontal directions, the FID memory A (1
Since each of 7) and FID memory B (18) is a memory corresponding to a full-screen pixel of the display device, 10
Corresponding to the number of pixels of 00 × 1000 = 1,000,000, each pixel is composed of 4 bits. Concentrated writing of the clear value in such a memory takes a considerable amount of time, which slows down the operation of the device. (The clear value will be described later.) An advantageous way of clearing without slowing down the device is that at least one-eighth or more of one FID memory after each frame has been written to the output device. Is to clear For example, FIG. 8 shows an example in which the FID memory A (17) is divided into eight horizontal stripes and is cleared. In the above example of 1,000,000 pixels, each horizontal stripe is
1,000,000 / 8 = equivalent to 125,000 pixels. FID memory B (1
8) is divided in the same way, and the horizontal strip becomes 16 in total. Then, a clear operation is performed for each horizontal line for each display of the frame. Then, after the display of the 16 frames is completed, clearing of all 16 horizontal stripes is completed.

The clear operation will be described with respect to the FID memory A (17) as follows. Processing for frame zero (RGB
Write the color value to the appropriate pixel address in display memory A (13) and write the frame identification number (here "zero") to the corresponding pixel address in FID memory A (17)
Before the first operation, a frame identification number as a clear value is written at each pixel position of each horizontal line of the FID memory A (17). FID memory A (17) is 0,2,4,
It handles 6,8,10,12,14 frames, so FID
As the clear value in the memory A (17), an odd frame number (1, 3, 5, 7, 9, 11, 13, 15) can be used. For example, as shown in FIG. 8, "15" can be used as the clear value.

Frame zero is processed in FID memory A (17) and CRT
And before the processing for frame 2 is started, the clear value is written to the uppermost horizontal stripe (all of 125,000 pixels) of the FID memory A (17). After the display operation for frame 2, the clear value is written to the second horizontal line of the FID memory A (17). After the frames are displayed one after the other, the clear values are likewise written to each horizontal line. Therefore, the next frame zero is stored in FID memory A
When writing to (17), the clear value has been written for all eight horizontal stripes, so the FID memory A
From (17), all zero values, which are identification numbers of frame zero, are excluded. As described above, since the identification number indicating the old frame zero does not exist in the FID memory A (17), even if the identification number of the next frame zero is simply written in the FID memory A (17), the information about the next frame zero is obtained. Is not distorted by the old frame zero identification number. Similar results occur when the next frame identification number is written. Therefore, in the FID memory, by the time immediately before a new frame is written, all writing of an old frame identification number with the same identification number as that of the new frame has already been cleared. Clearing the write for the old frame identification number is done by writing a clear value and is done in a known manner by means specific to the particular storage element.

Clearing one-eighth of FID memory A (17) or FID memory B (18) (clearing 125,000 pixels in the example above) after each output of a frame to the CRT
It will be apparent to those skilled in the art that this is significantly faster than conventional devices that require clearing the entire display memory for each output to RT. In the display memory, it is necessary to clear all the 24-bit pixels, but in the FID memory, it is sufficient to clear 4 bits per pixel, and the FID memory is completely cleared after each writing to the output device. Even so, the device of this embodiment is 16 times faster. In the preferred embodiment, which clears one-eighth of FID memory A (17) or FID memory B (18), the time required is
One-eighth of the time to clear the entire memory.
Thus, the total time used to clear in the device of the present invention is 1 / 48th of the time required to clear in a conventional device having equal display memory. This advantage is further exacerbated with FID memories having a larger number of bits. For example, when a 5-bit number is used for the frame identification number, a method of clearing one-fifteenth of the FID memory A (17) or the FID memory B (18) can be used. The required clearing time is 90 times smaller than that of the conventional device. When a 6-bit number is used for the frame identification number, the FID memory A
(17) Alternatively, a method of clearing one-third of the FID memory B (18) can be used, and the clear time required by the present invention can be reduced to one-186th of the conventional device.

Window Identification The output device described with reference to FIG. 1 can be conveniently used in computer devices that fully utilize multiple windows. For example, FIG. 2 shows a window identification output device 30 that can be used in the frame identification device described above, or alternatively. This device 30 can be used to provide an output signal to the CRT 12. Their output signals appear in various windows on the CRT.

The device 30 comprises a pair of double-buffered display memories A (1
3) and B (14). Each display memory is a full screen bit mapped memory. In the preferred embodiment, each display memory can include a 24-bit storage for each pixel for storing color information. The device 30 also includes a window identification (WID) register 34 and a WID memory 35. In the preferred embodiment, the WID register 34 contains 4
The WID memory 35 is a full screen bit mapped memory that contains four bits of information for each pixel. The window identification (WID) comparator 36 is a WID register
An output signal is received from the WID memory and the WID memory. The device 30 comprises a multiplexer 37, an enabling logic 38, and each display memory A.
A and B also include a control register 39 for selectively enabling states.

Next, the operation will be described. The window is initially selected by a value supplied by the CPU. These values include the pixel address and the window identification number for each pixel in the window. Window identification number is window identification memory
Written to each corresponding pixel of a particular window in 35. When the first window is written to the window identification memory, each pixel in the window carries the window identification number for that window. When the next window in front of the first window is written into the window identification memory, the upper portion of the first window of the second window is placed on top of the superimposed pixels of the first window. As it is written, the first window is automatically covered and clipped. After all the desired windows have been written, the window identification memory 35 has stored the instructions, as shown on the display of CRT 12 in FIG.

If you want to write information to the display memory for a particular window (a windowing device can be used for one display memory and a double buffered device), the information is
It is written from U to the display memory via the data bus. This information includes the pixel address, the above RGB value, and the window identification number. The window identification number is stored in the window identification register 34, and is compared with the window identification number stored in that pixel of the window identification memory 35. If the window identification number stored in the window identification memory 35 is the same as that number in the window identification register 34, the comparison circuit 36
B information can be written to the addressed pixel of the selected display memory. If the window identification number is not the same as the number stored for that pixel in the window identification memory, no RGB information is stored in the display memory. Thus, only the address of the selected display memory within each particular window is the signal to write to that window. The signal written to the display memory is transmitted from the specific display memory via the multiplexer 37 to the cathode ray tube 31.
(FIG. 2).

Several further advantages are realized by the window identification device described herein. For example, without many, the window identification device would write information in a particular window to the correct area of the display and properly clip portions of any particular window behind other windows. Is done. Further, since the window identification memory is a full screen bit mapped memory, the window can be of any shape. The shape can describe a shape other than a mere rectangular window as in the normal case.

Depth Information The device shown in FIG. 1 for quickly switching between frames of a display memory without clearing the display memory provides an output indicating the depth of each pixel provided to a particular display on the CRT. Including equipment. Various devices for supplying depth information are conventionally known, but the usual way is to specify an instruction at the pixel to be written on the display of the position of each pixel along the Z axis (third dimension axis). Is to give.

FIG. 3 shows a device 40 containing this information. This device 40 is different from the device shown in FIG. 1 in that a Z buffer memory 41 for storing Z information value, that is, a depth information value, and a comparing circuit 42 for comparing the stored Z buffer value with a new pixel value for each specific pixel. , A multiplexer 43 at the output terminal of the FID memory, and a comparator 44. The write enable logic circuit 24 is similarly used to control writing to the FID memory, the Z buffer memory, and the display memory.

As in the case of a display memory, in order to increase the operation speed of the apparatus, it is desirable to use a Z buffer memory 41 which does not require a clear during operation. A normal Z-buffer memory is a full screen video mapped memory, as well as FID memory, FID memory and display memory.
At each pixel address, an indication of a particular position at which the pixel is taken along the Z axis is stored. In a preferred embodiment of the present invention,
Since the Z buffer memory stores 24 bits in each pixel,
This process of clearing memory significantly slows down the operation of the device.

In conventional devices, the Z buffer memory is first cleared to the background Z value after each frame. This is done because the Z-buffer memory for each frame stores only the earliest value for each pixel. Since the background is the deepest of those that can be displayed, the Z-buffer memory is usually cleared before any frame is written. If not cleared, after the device has been activated at any time, the Z-buffer memory contains information from several previous buffers and needs to know which pixels to use and which pixels to ignore. is there.

To know whether a new pixel should be written to the display memory, it is necessary to know whether that pixel in the frame identification memory contains information in the frame in which it is being written. This determination is made, as described above, by the input frame identification register 16 and the specific FI selected by the control register 21.
This is performed by the device 40 using the D memory 17 or 18. The incoming EID number is compared to the FID number stored at the indicated pixel in the FID memory. If they are equal, FID
Comparator 44 provides an equal output to write enable logic 24. It indicates that the frame is the one in which the number stored in that pixel has been written, and therefore that the pixel has been written at least once for this frame.
If the FID numbers are not equal, the pixel has not been written prior to this frame, and thus comparison circuit 44 provides an unequal signal to the write enable logic. The signal is
Incoming information is written to various memories. In this case,
The selected display memory receives the color display signal at the pixel position,
The selected FID memory receives the new frame number and
The value is written to the Z buffer memory.

Assuming that the signal from FID comparator 44 is equal, indicating that the pixel was previously written to this frame, a Z-buffer comparison is required to determine whether to write. Z buffer comparator 42 looks up the Z value at that pixel location in the Z buffer memory and compares it to the new Z value. As a result of the comparison, if the Z value is less than or equal to that stored in memory, then the new pixel value is in the same plane, or at a location in front of the previously written pixel. Thus, the write enable logic is enabled to write the pixel to the appropriate display memory, FID memory, and Z buffer memory.

To operate the write enable logic so that pixels can be written to display memory and other memories,
FIG. 4 shows a truth table showing comparison values used for the FID comparator 44 and the Z buffer comparator 42. In this truth table, for the comparator output, 1 indicates that the = or <= state is true, and 0 indicates that the state is not true. Further, x indicates that the comparison state is not used. For a write output, 0 means no write occurs and 1 means write occurs. As shown in this table, assuming that the FID numbers are different as a result of the FID comparison, a new frame is written and the write enable circuit is activated no matter what the Z buffer comparison is. . On the other hand, if the FID comparison indicates that the FID numbers are the same, the result of the Z-buffer comparison controls the operation of the write enable circuit.

FIG. 5 shows an apparatus including the elements of the invention described above for providing very fast switching between frames displayed by a pair of double-buffered display memories on an output CRT.
Shows 50. This device includes a control register 21. This register receives the input signal from the CPU via the data bus,
The input signals are sent to enable the window identification circuit, the Z buffer circuit, and the frame identification circuit. The control register is a double-buffered display memory 13,1 for any particular operation, such as input or output.
4 and which of the frame identification memories 17 and 18 should be selected.

Device 50 also includes write enable logic 24. It operates as a central controller that writes information to the frame identification memory, the Z buffer memory, and the display memory.

Next, the operation will be described. The control register 21 receives a value indicating which element of the circuit is enabled. For example, a specific program may or may not be operated by a window comparison circuit, a frame identification register, or a Z buffer memory circuit. This is true. I mean,
This is because a specific program may not operate the window, operate in the three-dimensional area, or may not be used to perform the animation at a specific moment. In the following description, it is assumed that all three subsystems are enabled by signals provided to the control registers. The basic operation of this device 50 is
First, to determine whether the data signal is within a particular window, then, to determine if the data signal is in a particular frame in which it is being written, and finally, It is to determine whether to write a data signal for that frame before the already stored data signal.

The first step in any operation is to store the window to be used in the window identification memory. This is performed by writing a value from the CPU indicating each window to be used into the window identification memory 35.

Thereafter, when it is desired to write a particular pixel to the display memory 13 or 14, the values are stored in the control register 21 to select the appropriate A or B display memory and the appropriate associated frame identification memory 17 or 18. Is stored in The CPU writes the current window value to the WID register and the current frame value to the input FID register 16. In the window identification circuit, the window number in the WID register 34 is compared with the window identification number stored in the window identification memory 35, and if both are equal (that is, the information in the pixel is in the window), the window identification is enabled. A signal is sent to write enable logic 24.

The input FID comparator 44 compares the frame number in the input FID register with the frame number stored in the frame identification memory selected by the control register. If they are not equal, the next pixel has not yet been written to this frame and the signal is
Added directly to Thereby, the write enable logic (if it has received the enable signal from the window identification and comparison circuit) is enabled to write to each memory. That is,
The write enable logic writes to the particular FID memory selected, the Z buffer memory, and the display memory selected by the control register.

If no enable signal was received from the window identification comparison, the enable signal from the FID comparator will not enable the write enable logic to be written to any memory.

An enable signal is provided as a result of the window comparison,
Assuming that the comparison of the signal in the FID register and the selected FID memory indicates that the pixel identification is the same, it indicates that this pixel has already been written to this address for this frame. Then, a Z-buffer comparison needs to be performed to determine if the current pixel is ahead of the already stored pixel. Z
The buffer comparison compares the value supplied by the CPU with the Z value stored in the Z buffer memory for that pixel. If the Z value provided by the CPU is less than or equal to that stored in the Z buffer memory,
The new or current pixel is in front of the stored pixel. And FID memory in the write enablement theory,
Signals are provided for writing to the Z buffer memory and the selected display memory.

FIG. 6 shows the result of comparison between the window comparator circuit, the frame discrimination comparator, and the Z-buffer comparator.
4 is a truth table showing how to control the write enable circuit of FIG.

The other parts of the circuit shown in FIG. 5 of the device 50 are substantially the same as previously described and need not be described. For example, CRT
The background color register 20 is used to supply a background color to a position where the pixel to be displayed is not a foreground pixel in the selected frame. The output frame identification number is determined by comparing the frame identification number stored in the selected FID memory, and output is performed as described above to enable output from the appropriate display memory or background color register. The FID register 19 is used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the apparatus of the present invention for selecting individual frames to be displayed on a computer output device. FIG. 2 is a block diagram of the present invention for selecting individual windows to be displayed on the computer output device. Showing a block diagram,
FIG. 3 is a block diagram showing an apparatus of the present invention for selecting a specific frame including a three-dimensional figure to be displayed on a computer output device, and FIG. 4 explains the operation of the apparatus shown in FIG. FIG. 5 is a block diagram of a device including a device for selecting a window, a device for selecting a frame, and a device for selecting a depth dimension of a signal to be supplied to a computer output device. FIG. 6 is a truth table useful for explaining the operation of the apparatus shown in FIG. 5,
FIG. 7 is a block diagram showing registers and memories addressable on a host address bus from a central processing unit in accordance with the present invention, and FIG. 8 illustrates the operation for clearing a frame identification memory in accordance with the present invention. FIG. 10 …… Display output device, 13,14 …… Display memory, 15,22,37,
43 Multiplexer 16 Input frame identification register 17, 18 Frame identification memory 19 Output frame identification register 20, Background color register 21, 39 Control register 23 Comparison circuit , 24, 38 ... write enable logic circuit, 25 ... logic circuit, 30 ... window identification output device, 34 ... window identification register, 35 ... window identification memory, 36 ... window identification comparator, 41 ... ... Z
Buffer memory, 42... Z buffer comparison circuit, 44... Frame identification comparator.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Suzu-Chien San United States 94042 Mountain View, California Mountain View Pi Ou Botsukusu 585 (No address) (56) References (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 3/153 G09G 5/00

Claims (6)

(57) [Claims] 1. A computer output device for sequentially displaying a plurality of individual frame information on a display screen of a display means, the first output device having a plurality of pixel positions and storing the frame information in the pixel positions. A second memory means including a second memory having a plurality of pixel positions corresponding to the pixel positions in the first memory, the second memory means comprising: One of a plurality of n-bit frame indicators is stored at each of the pixel positions in the pixel information, and each of the plurality of n-bit frame indicators is stored in the first memory among the plurality of frame information. The first memory means and the second memory means can be used as input means coupled to the first memory means and the second memory means, and the first memory stores the frame information in the first memory means. The second memory is provided with input means for inputting the corresponding frame indicators so as to occupy the same pixel position in the first and second memories, respectively, and a first memory coupled to the second memory means. A first comparing means for comparing the frame mark stored at the pixel position in the second memory means with a mark indicating a specific frame to be displayed on the display screen. When the two signs compared by the first comparing means are equal, the frame information stored at the corresponding pixel position in the first memory is displayed on the display screen. Wherein said clear means is configured to be coupled to said second memory means,
A computer output device, comprising: clear means for clearing the continuous part of the second memory means each time the frame information is displayed on the display screen. 2. The computer output device according to claim 1, further comprising a third memory having a plurality of pixel locations corresponding to said pixel locations in said first memory, coupled to said input means. One of a plurality of markers indicating a window to be displayed on the display screen is stored at each of the pixel positions in the third memory; A second comparison means coupled to the means, wherein the sign indicating a window stored at the pixel location in the third memory means, and a sign indicating a particular window to be displayed on the screen. A second comparing means for comparing the frame information to be displayed on the display screen only when the two signs compared by the second comparing means are equal to each other. Me Computer output and wherein the input to re unit. 3. A computer output device for sequentially displaying a plurality of individual frame information so as to perform a three-dimensional display of information on a display screen of a display means, comprising: a plurality of pixel positions; A first memory unit including a first memory for storing a pixel position in a pixel position, and a second memory unit including a second memory having a plurality of pixel positions corresponding to the pixel position in the first memory. One of a plurality of n-bit frame indicators is stored at each of the pixel positions in the second memory, and each of the plurality of n-bit frame indicators includes A frame information stored in the first memory can be specified, and a third memory having a plurality of pixel positions corresponding to the pixel positions in the first memory is included. A third memory unit for storing depth information at each of the pixel positions in a third memory; the first memory unit, the second memory unit, and the third memory unit; Input means coupled to the first, second, and third memory so that the frame information, the n-bit frame indicator, and the depth information occupy the same pixel position in the first, second, and third memories, respectively. The memory conditionally inputs the frame information, the second memory conditionally inputs the n-bit frame indicator,
The third memory includes input means for conditionally inputting the depth information; and a first comparing means coupled to the second memory means, wherein the pixel position in the second memory means is provided. And a first comparing means for comparing the frame mark stored in the first frame with a mark indicating a specific frame to be displayed on the display screen, and both the marks compared by the first comparing means are compared with each other. If not equal, by the input means
The frame information is stored at the corresponding pixel location in the first memory, the frame indicator is stored at the pixel location in the second memory, and the depth information is stored in the third memory. A second comparing means coupled to the third memory means and the input means, wherein the two signs compared by the first comparing means are equal to each other. Compares the depth information stored in the third memory with the depth information input by the input means, and compares the stored depth information with the depth information input by the input means. If greater than or equal, the input means stores the frame information at the corresponding pixel location in the first memory and sets the frame indicator to the Computer output device stored at the pixel location in the second memory and the depth information stored in the pixel location in the third memory. . 4. The computer output device according to claim 3, further comprising: a marker for a specific frame to be displayed on the display screen, the marker being coupled to the second memory means and the input means; And a third comparing means for comparing the frame mark stored in the pixel position in the second memory with the frame mark. If both the marks compared by the third comparing means are equal, the first mark is compared with the first mark. And the frame information and the depth information respectively stored at the corresponding pixel positions in the second memory means are displayed on the display screen. 5. A computer output device for sequentially displaying a plurality of individual pieces of frame information so as to perform three-dimensional display of information in an arbitrary window on a display screen on a display means, comprising a plurality of pixel positions. And a first memory means including a first memory for storing the frame information at a pixel position, wherein a second memory having a plurality of pixel positions corresponding to the pixel position in the first memory is provided. A second memory means including one of a plurality of n-bit frame indicators stored at each of the pixel locations in the second memory, wherein each of the plurality of n-bit frame indicators comprises: One frame information stored in the first memory can be specified from among the plurality of frame information, and has a plurality of pixel positions corresponding to the pixel positions in the first memory. A third memory means including a third memory, wherein at each of the pixel positions in the third memory, one of a plurality of n-bit window indicators indicating a window to be displayed on the display screen is provided. A fourth memory having a plurality of pixel positions corresponding to the pixel positions in the first memory, wherein depth information is stored in each of the pixel positions in the fourth memory. 4
The first memory means, the second memory means, the third memory means, and the fourth memory means as input means coupled to the frame information, The n-bit frame indicator, the window indicator, and the depth information occupy the same pixel position in the first, second, third, and fourth memories, respectively, and the frame information is stored in the first memory. Is conditionally input, the n-bit frame indicator is conditionally input to the second memory, the window indicator is input to the third memory, and the depth information is conditionally input to the fourth memory. And input means for inputting the window mark stored in the pixel position in the third memory means as first comparison means coupled to the third memory means; Picture A second comparing means coupled to the second memory means, comprising first comparing means for comparing with a sign indicating a particular window to be displayed above, wherein the second comparing means coupled to the second memory means; A second comparing means for comparing the frame mark stored at the pixel position with a mark indicating a specific frame to be displayed on the display screen; If the signs are not equal and the two signs compared by the first comparing means are equal, the frame information is not equal to the first sign.
At the corresponding pixel location in the memory, the frame indicator is stored at the pixel location in the second memory, and the depth information is stored at the pixel location in the fourth memory. A third comparing means coupled to the fourth memory means and the input means, wherein both indices compared by the first comparing means are equal and compared by the second comparing means. If both signs are equal, the fourth
Comparing the depth information stored in the memory means with the depth information input by the input means, and determining whether the stored depth information is greater than the depth information input by the input means. Or when equal, the input means stores the frame information at the corresponding pixel location in the first memory, stores the frame marker at the pixel location in the second memory, Computer output device, characterized in that it comprises a third comparing means for storing at the pixel position in the fourth memory. 6. The computer output device according to claim 5, wherein said sign indicating a specific frame to be displayed on said display screen is provided as fourth comparing means coupled to said second memory means. And fourth comparing means for comparing the frame mark stored at the pixel position in the second memory means with the frame mark, and when the two signs compared by the fourth comparing means are equal, the fourth mark The computer output device, wherein the frame information stored at the corresponding pixel position in the first memory is displayed on the display screen.