JP2854846B2 - Manufacturing method of semiconductor circuit - Google Patents

Manufacturing method of semiconductor circuit

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Publication number
JP2854846B2
JP2854846B2 JP8269078A JP26907896A JP2854846B2 JP 2854846 B2 JP2854846 B2 JP 2854846B2 JP 8269078 A JP8269078 A JP 8269078A JP 26907896 A JP26907896 A JP 26907896A JP 2854846 B2 JP2854846 B2 JP 2854846B2
Authority
JP
Japan
Prior art keywords
semiconductor circuit
manufacturing
current
semiconductor
ribbon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8269078A
Other languages
Japanese (ja)
Other versions
JPH09190930A (en
Inventor
孝雄 沢
勝彦 川北
順夫 広瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8269078A priority Critical patent/JP2854846B2/en
Publication of JPH09190930A publication Critical patent/JPH09190930A/en
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Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明者は電流スパイク、電
流リンギングを抑制するための半導体回路の製造方法
関する。 【0002】 【従来の技術】従来より、高周波領域で大電流の制御を
行なう、例えばスイッチング電源等の半導体回路におい
ては、半導体自身の性質や他の回路的要因により電流の
オン・オフ時の過渡現象に基づく規格値以上のピーク電
流、すなわち電流スパイクやパルス電流の揺らぎ、すな
わち電流リンギングが発生し易いという問題があった。
これらの現象は回路動作の正常化を妨げ、ついには半導
体を破壊してしまうおそれがあった。さらに、このよう
な急激な電流変化は機器のノイズの最大の原因となって
いた。近年、このようなノイズ障害に対する国際的な対
策強化の要請により、効率η(出力/入力)を低下させ
ず半導体使用機器の発生ノイズを防止する対策が強化さ
れつつあり、ノイズの防止が重要な問題となってきてい
る。このような電流スパイクや電流リンキングを抑制す
るため、半導体回路に半導体回路用リアクトルを配置す
ることが行われているが従来の半導体回路用リアクトル
のコアはフェライトあるいはパーマロイ等で形成されて
いるため、十分な抑制を行なうことができなかった。す
なわちフェライト製のコアを使用した場合は、角形比
(Br/B1 )および飽和磁束密度が小さいため抑制
効果が小さく、有効にするためにはコアの形状を大きく
する必要がありパーマロイ製のコアを使用した場合は、
保磁力(Hc)が大きくて、高周波化に対応できないと
いう難点があった。 【0003】 【発明が解決しようとする課題】本発明はこのような難
点を解消するためなされたもので、効率ηをほとんど低
下させずにノイズを発生する原因である電流スパイクや
電流リンギングを防止することのできる半導体回路の製
造方法を提供することを目的とする。 【0004】 【課題を解決するための手段】すなわち本発明の半導体
回路の製造方法は、非晶質磁性合金 【数1】 (t−)/t≦0.30(ここでtは最大板厚、は
平均板厚)の表面粗さを有するリボン状薄板とする工程と、前記リ
ボン状薄板を巻回してトロイダルコアを形成する工程
と、前記トロイダルコアと導体とを組合わせて半導体回
路用リアクトルとする工程と、前記半導体回路用リアク
トルを半導体に直列に挿入する工程と、を有することを
特徴とする半導体回路の製造方法 である。 【0005】ここでtは上記薄板に関する実測値として
求められ、tは上記薄板の重量、幅、長さ、密度をそれ
ぞれw,d,l,ρとしたときにt=w/d・l・ρの
式から算出される計算値である。この表面粗さの値が、
0.30を越えると該薄帯の表面凹凸の状態が顕著になり
(表面が粗くなり、)高周波領域での鉄損が著しく大き
くなって使用に適さなくなる。また、0.30を超える
と角形比も低下してしまう。更に、表面粗さが大きい
と、コアのパッキングファクタが小さくなるため結果と
して総磁束が小さくなり好ましくない。また、上記薄板
にあって、厚み最大値(t)が5μm未満の場合には、
得られた磁心の巻回時において層間絶縁体を大量に必要
とするためその占積率が著しく低下し実用的でなくな
る。更に、tが40μmを超えると高周波領域における
鉄損が著しく増大し電流スパイク等を抑制する効果が減
少する。したがって、本発明の磁心にあっては、その薄
帯の厚み最大値が5μm≦t≦50μmの範囲に設定す
ることが好ましい。本発明に使用する非晶質磁性合金と
しては一般にMaNbYcで表わされる合金が考えられ
る。この場合MはFe,Co,から選ばれる少なくとも
1種の元素、NはFe,Co以外の遷移金属から選ばれ
る少なくとも1種の元素、YはSi,B,P,C,G
e,Alから選ばれる少なくとも1種の元素であり、0.
60≦a≦0.90,0 ≦b≦0.15,0.10≦C≦0.35の組成で
あることが好ましい。本発明においては、非晶質磁性合
金を単ロール法によりリボン状にして巻回することによ
りトロイダルコアを形成、あるいはリング状に打抜いた
ものを積層してトロイダルコアを形成し、このコアに複
数個の巻線を施すことにより半導体回路用リアクトルが
得られる。この半導体回路用リアクトルを半導体に直列
に挿入することにより半導体回路の電流スパイクやリン
ギングを抑制することができる。 【0006】 【発明の実施の形態】次に本発明の実施例を説明する。 【0007】 【実施例】 (実施例1)(Co0.87 Fe0.05 Ni0.04 Mn
0.02 Nb0.0273Si1314 で表わされる非晶質磁
性合金を板厚が25μmで、表面粗さが種々変化させた
リボン状薄板にし、内径6mmで約20回巻回してトロイ
ダルコアとし、これに巻線を施して半導体回路用リアク
トルを形成した。これらの半導体回路用リアクトルをダ
イオードに直列に挿入してスイッチング電源として10
0kHzにおける効率η(出力・入力)を求めたところ
図1に示す結果が得られた。これより表面粗さが0.30以
下の場合に効率が良好であることがわかる。また、表面
粗さ0.30以下のものは電流スパイクおよび電流リンギン
グは大きく抑制されほとんど見られなかった。 【0008】(実施例2)(Co0.90 Fe0.06 Cr
0.0474 Si1412 で表される非晶質磁性合金
を単ロール法により表面粗さが0.20〜0.23で、板厚が各
々18μm,25μm,45μmのリボン状の薄板に
し、酸化マグネシウム粉末で層間絶縁し、内径6mmで2
0回巻いてトロイダルコアとし、各々のトロイダルコア
に巻線を施こし半導体回路用リアクトルを形成した。こ
れらの半導体回路用リアクトルをダイオードに直列に挿
入してスイッチング電源として100kHzにおける効
率η(出力/入力)を求めたところ表1のような結果が
得られた。 【0009】 【表1】【0010】 【発明の効果】本発明の製造方法により得られた半導体
回路は効率(出力/入力)をほとんど低下させることな
く電流スパイクや電流リンギングを防止することができ
る。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor circuit for suppressing current spikes and current ringing. 2. Description of the Related Art Conventionally, in a semiconductor circuit such as a switching power supply for controlling a large current in a high frequency region, a transient at the time of turning on and off a current is caused by the characteristics of the semiconductor itself and other circuit factors. There is a problem that a peak current exceeding a standard value based on the phenomenon, that is, fluctuation of a current spike or a pulse current, that is, current ringing is easily generated.
These phenomena hindered normalization of the circuit operation, and could eventually destroy the semiconductor. Further, such a sudden change in current has been the largest cause of equipment noise. In recent years, with the demand for strengthening international countermeasures against such noise disturbances, measures to prevent noise generated by semiconductor devices without lowering the efficiency η (output / input) have been strengthened, and prevention of noise is important. Is becoming a problem. In order to suppress such current spikes and current linking, a semiconductor circuit reactor is arranged in a semiconductor circuit.However, since the core of a conventional semiconductor circuit reactor is formed of ferrite or permalloy, etc. Sufficient suppression could not be achieved. That is, when a ferrite core is used, the squareness ratio (Br / B1) and the saturation magnetic flux density are small, so that the suppression effect is small. In order to make the core effective, the core shape needs to be large. If used,
There was a problem that the coercive force (Hc) was large and could not cope with a higher frequency. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to prevent a current spike or a current ringing which causes noise without substantially reducing the efficiency η. manufacturing of semiconductor circuit that can be
It is intended to provide a fabrication method . That is, according to the method of manufacturing a semiconductor circuit of the present invention, an amorphous magnetic alloy is formed by the following equation: (t −) / t ≦ 0.30 (where t is the maximum plate thickness). A ribbon-shaped thin plate having a surface roughness of (thickness, average plate thickness) ;
Step of winding a bon-shaped thin plate to form a toroidal core
And a semiconductor circuit by combining the toroidal core and the conductor.
A step of forming a road reactor;
And inserting the tor into the semiconductor in series.
This is a method for manufacturing a semiconductor circuit characterized by the following. [0005] Here, t is obtained as an actual measurement value of the thin plate, and t is t = w / d · l · when the weight, width, length, and density of the thin plate are w, d, l, and ρ, respectively. This is a calculated value calculated from the expression of ρ. The value of this surface roughness is
If it exceeds 0.30, the state of the surface irregularities of the ribbon becomes remarkable (the surface becomes rough), and the iron loss in a high frequency region becomes extremely large, making the ribbon unusable. If it exceeds 0.30, the squareness ratio will also be reduced. Further, when the surface roughness is large, the packing factor of the core becomes small, and as a result, the total magnetic flux becomes small. When the maximum thickness (t) is less than 5 μm in the thin plate,
When the obtained magnetic core is wound, a large amount of an interlayer insulator is required, so that the space factor thereof is significantly reduced, which is not practical. Further, when t exceeds 40 μm, iron loss in a high-frequency region increases significantly, and the effect of suppressing current spikes and the like decreases. Therefore, in the magnetic core of the present invention, it is preferable that the maximum thickness of the ribbon is set in the range of 5 μm ≦ t ≦ 50 μm. As the amorphous magnetic alloy used in the present invention, an alloy represented by MaNbYc is generally considered. In this case, M is at least one element selected from Fe and Co, N is at least one element selected from transition metals other than Fe and Co, and Y is Si, B, P, C, G
e, at least one element selected from Al.
The composition preferably satisfies 60 ≦ a ≦ 0.90, 0 ≦ b ≦ 0.15, 0.10 ≦ C ≦ 0.35. In the present invention, a toroidal core is formed by winding an amorphous magnetic alloy in a ribbon shape by a single roll method, or a ring-shaped punch is laminated to form a toroidal core. By providing a plurality of windings, a reactor for a semiconductor circuit can be obtained. By inserting the semiconductor circuit reactor in series with the semiconductor, current spikes and ringing of the semiconductor circuit can be suppressed. Next, an embodiment of the present invention will be described. (Example 1) (Co 0.87 Fe 0.05 Ni 0.04 Mn
An amorphous magnetic alloy represented by 0.02 Nb 0.02 ) 73 Si 13 B 14 is formed into a ribbon-like thin plate having a thickness of 25 μm and variously varying surface roughness, and is wound about 20 times with an inner diameter of 6 mm to form a toroidal core. This was wound to form a reactor for a semiconductor circuit. These semiconductor circuit reactors are inserted in series with diodes to provide a switching power supply of 10
When the efficiency η (output / input) at 0 kHz was determined, the result shown in FIG. 1 was obtained. This indicates that the efficiency is good when the surface roughness is 0.30 or less. In the case of the surface roughness of 0.30 or less, the current spike and the current ringing were largely suppressed and were hardly observed. Example 2 (Co 0.90 Fe 0.06 Cr)
0.04 ) An amorphous magnetic alloy represented by 74 Si 14 B 12 is formed into a ribbon-shaped thin plate having a surface roughness of 0.20 to 0.23 and a thickness of 18 μm, 25 μm, or 45 μm by a single roll method, and then using magnesium oxide powder. Insulation between layers, inner diameter 6mm 2
Twenty turns were made into toroidal cores, and each of the toroidal cores was wound to form a reactor for a semiconductor circuit. These reactors for a semiconductor circuit were inserted in series in a diode, and the efficiency η (output / input) at 100 kHz was obtained as a switching power supply. The results shown in Table 1 were obtained. [Table 1] The semiconductor circuit obtained by the manufacturing method of the present invention can prevent current spikes and current ringing without substantially lowering the efficiency (output / input).

【図面の簡単な説明】 【図1】表面粗さに対する効率ηを示す特性図。[Brief description of the drawings] FIG. 1 is a characteristic diagram showing efficiency η with respect to surface roughness.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特公 平7−118428(JP,B2) 特公 平4−80523(JP,B2) (58)調査した分野(Int.Cl.6,DB名) H01F 27/24────────────────────────────────────────────────── ─── Continued on the front page (56) References JP-B 7-118428 (JP, B2) JP-B 4-80523 (JP, B2) (58) Fields surveyed (Int. Cl. 6 , DB name) H01F 27/24

Claims (1)

(57)【特許請求の範囲】 1.非晶質磁性合金 【数1】 (t−)/t≦0.30(ここでtは最大板厚、は
平均板厚)の表面粗さを有するリボン状薄板とする工程と、 前記リボン状薄板を巻回してトロイダルコアを形成する
工程と、 前記トロイダルコアと導体とを組合わせて半導体回路用
リアクトルとする工程と、 前記半導体回路用リアクトルを半導体に直列に挿入する
工程と、 を有することを特徴とする半導体回路の製造方法。 2.非晶質磁性合金が5μm以上40μm以下の板厚の
薄板であることを特徴とする特許請求の範囲第1項記載
の半導体回路の製造方法
(57) [Claims] Amorphous magnetic alloy Equation 1] (t -) / t ≦ 0.30 ( where t is the maximum thickness, the average thickness) comprising the steps of a ribbon-like thin plate having a surface roughness of the ribbon To form a toroidal core
Process, and combining the toroidal core and the conductor for a semiconductor circuit.
A reactor and inserting the semiconductor circuit reactor in series with the semiconductor
And a method for manufacturing a semiconductor circuit. 2. The method of manufacturing a semiconductor circuit ranging first claim of claims, wherein the amorphous magnetic alloy is 40μm or less of the thickness of the thin plate or 5 [mu] m.
JP8269078A 1996-09-20 1996-09-20 Manufacturing method of semiconductor circuit Expired - Lifetime JP2854846B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8269078A JP2854846B2 (en) 1996-09-20 1996-09-20 Manufacturing method of semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8269078A JP2854846B2 (en) 1996-09-20 1996-09-20 Manufacturing method of semiconductor circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP59019337A Division JPH07118428B2 (en) 1984-02-07 1984-02-07 Reactor for semiconductor circuit

Publications (2)

Publication Number Publication Date
JPH09190930A JPH09190930A (en) 1997-07-22
JP2854846B2 true JP2854846B2 (en) 1999-02-10

Family

ID=17467367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8269078A Expired - Lifetime JP2854846B2 (en) 1996-09-20 1996-09-20 Manufacturing method of semiconductor circuit

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JP (1) JP2854846B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2828744B2 (en) * 1990-07-20 1998-11-25 三洋電機株式会社 microwave
CA2057716A1 (en) * 1991-09-30 1993-03-31 Bernard Cohen Hydrosonically microapertured thin thermoplastic sheet materials

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Publication number Publication date
JPH09190930A (en) 1997-07-22

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