JP2853043B2 - Storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device having a built-in address generation circuit.

(Prior Art) In recent years, as the application fields of semiconductor memory devices have expanded, higher integration and higher functionality have been required, and accordingly, semiconductor memory devices incorporating an address generation circuit have been developed.

FIG. 4 shows an example of a system using a conventional semiconductor memory device with a built-in address generation circuit. In the figure, 41,4
2 and 43 are semiconductor memory devices with built-in address generation circuits, and 44
Is an external control device. The plurality of semiconductor memory devices 41, 42, and 43 with built-in address generation circuits operate by receiving an address reset signal (hereinafter abbreviated as a reset signal) and an address control clock (hereinafter abbreviated as a clock) from an external control device 44. I have. When a reset signal is supplied from the external control device 44, internal addresses generated in the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits are initialized, and further, when a clock is supplied from the external control device 44, the address is reset. Semiconductor memory devices 41 and 4 with built-in generation circuits
The address generated at 2,43 advances. In a state where a reset signal is always given from the external control device 44 (hereinafter, abbreviated as a synchronous mode), the internal addresses of the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits are initialized for each reset signal,
The internal address is incremented every clock,
In a state where a reset signal is not supplied from the external control device 44 (hereinafter, abbreviated as asynchronous mode), the internal addresses of the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits are incremented for each clock, and when the maximum value is reached, the next clock is used. Returns to the initial value.

(Problems to be Solved by the Invention) In the above conventional example, in the synchronous mode in which a reset signal is supplied from the external control device 44 to the semiconductor memory devices 41, 42, and 43 with an address generation circuit, the semiconductor memory with an address generation circuit is reset for each reset signal. Since the internal addresses of all the devices 41, 42, and 43 are initialized, at this time, the internal addresses of the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits always match. Therefore, in the synchronous mode, as shown in FIG. 5, even if the internal addresses of the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits are shifted due to clock distortion or the like, the next control provided by the external control device 44 is performed. Reset signal causes semiconductor memory device with built-in address generation circuit 4
The deviation of the internal addresses of 1, 42 and 43 can be corrected and matched.

On the other hand, in the asynchronous mode, the external control device 44 does not need to provide a reset signal to the semiconductor memory devices 41, 42, and 43 with built-in address generation circuits. However, as shown in FIG. Storage device 4
If the internal addresses of 1, 42 and 43 are misaligned, a reset signal is not given from the external control device 44, so the internal addresses of the semiconductor memory devices 41, 42 and 43 with built-in address generation circuits must be forcibly matched. Therefore, it is not possible to correct the deviation of the internal address.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional drawbacks and to provide a plurality of address generation circuits even when an external control device controls an asynchronous mode without giving a reset signal to a plurality of semiconductor memory devices with built-in address generation circuits. An object of the present invention is to provide a storage device capable of correcting and synchronizing a shift of an internal address only with a built-in semiconductor storage device.

(Means for Solving the Problems) In order to achieve the above object, a storage device of the present invention sequentially changes an internal address in synchronization with an external clock signal, and when the internal address becomes the final address, the next external clock A plurality of semiconductor memory devices each having a built-in address generation circuit returning to an initial address by a signal, wherein at least one of the semiconductor memory devices has a first set value whose internal address is predetermined. The second semiconductor memory device receives the master clock signal output by the first semiconductor memory device and sets its own internal address to the second set value. A configuration having a circuit that performs Alternatively, a plurality of semiconductor memory devices each have both circuits.

(Operation) With the above configuration, a deviation of internal addresses among a plurality of semiconductor memory devices with built-in address generating circuits, which has occurred in the asynchronous mode, which was impossible in the past, is corrected, and a plurality of semiconductor memory devices with built-in address generating circuits are corrected. Just to be able to synchronize.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a configuration diagram of a storage device according to a first embodiment of the present invention. In the figure, 11 is a semiconductor memory device with a built-in address generation circuit having a master clock generation circuit,
Reference numerals 12 and 13 denote semiconductor memory devices with a built-in address generation circuit having a slave circuit, and 14 denotes an external control device. In this embodiment, the operation of the semiconductor memory devices 11, 12, and 13 with the address generation circuit in the synchronous mode is the same as that of the conventional example. Semiconductor memory devices 11 and 1 with built-in address generation circuits in asynchronous mode
The operations 2 and 13 are as shown in FIG. In the semiconductor memory device 11 with a built-in address generating circuit having a master clock generating circuit, when the internal address becomes a certain value, a master clock is generated and sent to the semiconductor memory devices 12 and 13 with a built-in address generating circuit having slave circuits. Can be In the semiconductor memory devices 12 and 13 with a built-in address generation circuit having a slave circuit, the slave operation is performed in response to the master clock, so that the internal address is set to an arbitrary value. Therefore, in the asynchronous mode, the third
Even when the internal addresses of the semiconductor memory devices 11, 12, and 13 with address generation circuits are shifted due to clock distortion or the like as shown in the figure, the master clock causes
By causing the semiconductor memory devices 12 and 13 with a built-in address generation circuit having a slave circuit to perform a slave operation, the deviation of the internal address of the semiconductor storage devices with a built-in address generation circuit 11, 12 and 13 is corrected, and the semiconductor memory with a built-in address generation circuit is corrected. Synchronization can be achieved only between the devices 11, 12, and 13.

FIG. 2 shows a second embodiment. In the figure, 21, 22,
23 is a semiconductor memory device with a built-in address generation circuit having a master clock generation circuit and a slave circuit, and 24 is an external control device.

As shown in the second embodiment, the master clock of the semiconductor memory device 21 with a built-in address generating circuit is also applied to the slave circuits of the semiconductor memory devices 22 and 23 with a built-in address generating circuit. Action is taken.

(Effects of the Invention) According to the present invention, the master clock of an arbitrary one of the plurality of semiconductor memory devices with built-in address generation circuits in the plurality of semiconductor memory devices with built-in address generation circuits is changed to the other semiconductor memory device with built-in address generation circuits. , The deviation of the internal addresses of the plurality of semiconductor memory devices with built-in address generation circuits in the asynchronous mode can be corrected, and synchronization can be achieved only with the plurality of semiconductor memory devices with built-in address generation circuits. Its practical effect is great.

[Brief description of the drawings]

1 and 2 are diagrams showing the configuration of a storage device according to an embodiment of the present invention, FIG. 3 is a diagram showing the operation of the internal address generation circuit, FIG. 4 is a configuration diagram of a conventional storage device, and FIG. FIG. 6 shows the operation of the internal address generating circuit. 11, 12, 13, 21, 22, 23 ... semiconductor memory devices with built-in address generation circuits, 14, 24 ... external control devices.

Continued on the front page (72) Inventor Yoshikazu Kageyama 1006 Kazuma Kadoma, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. 56) References JP-A-62-27813 (JP, A) JP-A-62-160519 (JP, A) JP-A-63-66633 (JP, A)

Claims (2)

(57) [Claims] An internal address is sequentially changed in synchronization with an external clock signal, and when the internal address becomes a final address, a plurality of semiconductor memory devices each including an address generating circuit that returns to an initial address by the next external clock signal. In addition, at least one first semiconductor memory device among the semiconductor memory devices has a circuit that outputs a master clock signal when an internal address reaches a predetermined first set value. The semiconductor memory device includes a circuit that receives a master clock signal output from the first semiconductor memory device and sets its own internal address to a second set value. 2. The semiconductor memory device according to claim 1, wherein the internal address is sequentially changed in synchronization with an external clock signal, and when the internal address becomes the final address, the semiconductor memory device includes an address generating circuit which returns to an initial address by the next external clock signal. Each of the semiconductor memory devices outputs a master clock signal when the internal address reaches a predetermined first set value, and receives a master clock signal output by another semiconductor memory device to receive a master clock signal. A circuit for setting an address to a second set value.