JP2850933B2 - Ghost removal device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ghost removing apparatus suitable for various video equipment such as a television (TV) receiver and a video tape recorder (VTR). It is another object of the present invention to provide a ghost removing apparatus capable of removing a waveform distortion such as a ghost stably in a short time.

[0002]

2. Description of the Related Art FIG. 5A shows a configuration example of a conventional ghost removing device. FIG. 5B shows an example of the detailed configuration. A typical algorithm of such a ghost removing device is a ZF method (Zero Forcing Methode).

[0003] Video signals of TV broadcasting include Japanese Patent Application No. 1-69.
As shown in No. 179, the GCR waveform of FIG. 7A and the 0 pedestal waveform of FIG. 7B are inserted in an eight-field sequence as a ghost canceling reference signal (GCR signal). (Insert on the sending side.)

FIGS. 8 (a) to 8 (h) are layout diagrams of GCR signals from the first field (F1) to the eighth field (F8), and are periodic signals having eight fields as one cycle. If a difference is taken between the signals of FIGS. 7A and 7B four fields apart from these signal arrangements, the horizontal synchronizing signal and the burst signal are erased (the same phase between the fields four fields apart) Therefore, a GCR waveform as shown in FIG. 7C can be obtained.

When this GCR waveform is subjected to difference processing at intervals of 1 / (4 fsc) (where fsc is the color subcarrier frequency), a ghost canceling reference pulse as shown in FIG. 7D, that is, a GCR pulse is obtained. be able to. GCR
The pulse has a flat characteristic up to fm (= about 4 MHz) which is a frequency occupied band of the video signal as shown in FIG. 9A. FIG. 7E is a GCR pulse when there is an in-phase ghost having a delay time Tg and a waveform diagram of the ghost. The ghost detection time range is the range of t1 + t2 between -t1 and t2 in FIGS. 7D and 7E. t
The values of 1, t2 are usually

[0006]

(Equation 1)

Is set to the value of

In FIG. 5A, an NTSC video signal received by an antenna is supplied to an input line L1. As described above, the GCR signals of FIGS. 7A and 7B are inserted into this video signal in an eight-field sequence as shown in FIGS. 8A to 8H. The insertion period of the GCR signal is 18H and 281H.

In the following processing system, description will be made mainly assuming digital signal processing. Therefore, it is assumed that the input signal is subjected to AD (analog-digital) conversion. Accordingly, the final output signal from line L2 is DA
(Digital-to-analog) conversion. The value normally used as the sampling frequency fs at this time is 4 fs.
c.

An input signal (analog signal) is first extracted by a sync separation circuit 2-1 from the horizontal and vertical sync signals in the signal. In this case, another burst signal, which is another sync signal, is extracted. A burst gate pulse is created. A circuit having such a synchronization separation function is commercially available as a general-purpose TV LSI. The input signal is further applied to a bandpass filter (BPF) 2-2, where a chrominance signal having a modulation frequency fsc is extracted.
The color signal is supplied to the next synchronous oscillator (VCO) 2-3 together with the burst gate pulse from the block 2-1, and the burst signal periodically inserted into the video signal at intervals of about 63.5 μsec is extracted. Then, a sampling pulse fs synchronized with the burst signal is formed by the VCO 2-3. VCO2-3 is also commercially available incorporated in an LSI for TV. The pulse signal of the sampling frequency fs output from the line L3 is used as a clock signal of a digital circuit (described later).

The input signal is also supplied to a low-pass filter (LPF) 2
-4, out of band of input signal (more than about 4MHz)
Is removed, and the signal is converted into a digital signal of about 8 bits by an AD converter (analog-digital converter) 2-5.

The output of the AD converter 2-5 is supplied to a transversal filter unit 2-6. FIG.
Is a specific circuit example. In FIG. 6, 3-A is an FIR filter, and 3-B is an IIR filter. The signal that has passed through these two filters is output from line L2. The FIR filter 3-A has a delay time T having the same value as the sampling period (see the following equation).

[0013]

(Equation 2)

A delay circuit group 3-1 in which 2M (M is a positive integer) delay circuits are connected in series, and input / output signals of each delay circuit are supplied. Coefficient setting circuit group 3-2 including 2M + 1 amplifiers to be amplified
And a combiner 3-3 for adding and combining the 2M + 1 signals amplified here. The output of this combiner is supplied to the next IIR filter 3-B.

The IIR filter 3-B includes an adder 3-4,
The FIR filter 3-C includes a delay circuit 3-5 that delays an output signal of the adder 3-4 by a time MT and supplies the delayed signal to the FIR filter 3-C. FIR filter 3
−C is N−1 (N) like the FIR filter 3-A.
Is an integer greater than 1), a delay circuit group 3-6, an N number of coefficient setting circuit groups 3-7, and a combiner 3-8.

The structure shown in FIG. 6 is expressed by the following expression that represents frequency characteristics.

[0017]

(Equation 3)

Ga (f) is the characteristic of the FIR filter 3-A responsible for waveform equalization and proximity ghost removal.
(F) is a characteristic of the IIR filter 3-B which normally performs ghost and long ghost removal. Gb
(F) is a combined characteristic of the delay circuit 3-5 and the FIR filter 3-C.

The output signal of the filter section 2-6 is converted into an analog signal by a DA converter (digital-analog converter) 2-7, and unnecessary high-frequency components are removed by an LPF 2-8. It is transmitted as an output video signal. On the other hand, the output of the filter unit 2-6 is
-9.

The waveform capturing unit 2-9 captures a GCR signal portion from the input video signal for each field (FIG. 8).
7), and obtains the difference between the GCR waveform of FIG. 7 (a) and the zero pedestal waveform of FIG. 7 (b) separated by, for example, four fields, and extracts the GCR waveform of FIG. 7 (c). doing.

In the next synchronous adder 2-10, the G
To reduce noise components included in the CR waveform, G
While adjusting the position of the rising slope of the CR waveform,
The CR waveform is averaged.

The waveform converter 2-11 is a difference circuit, and performs a difference process on the GCR waveform as shown in FIG. 7C at intervals of T = 1 / (4 fsc) to obtain a difference as shown in FIG. GCR pulse y (n) (where n represents the number of the data string,
y (n) means y (nT). Hereinafter, a similar expression method is used. ). As aforementioned,
When a ghost exists, the result is as shown in FIG.

The reference waveform generator 2-13 produces an original GCR pulse s (n) without distortion. Actually, it is performed in such a manner that the data is written in a ROM or the like in advance and the data is sequentially read out by a clock pulse. FIG. 7F shows the reference waveform. In this case, the waveform is the same as FIG. 7D.

The subtracter 2-12 obtains the difference between the signal y (n) from the waveform converter 2-11 and the signal s (n) from the reference waveform generator 2-13 to obtain an error signal e (n). ing.

[0025]

(Equation 4)

The coefficient forming unit 2-14 is a circuit block for performing a coefficient updating process based on the ZF method.

[0027]

(Equation 5)

A new coefficient value is determined. By changing the magnification α according to the state of the signal, adaptive control can be performed.

FIG. 5B shows an example of a specific configuration of the coefficient forming device. Block 2b1 is an amplifier that multiplies input e (n) by α. The block 2b2 is a subtractor, and calculates the difference between the input co (n) from the block 2b3 supplied via the switch circuit 2b4 and the input αe (n) from the block 2b1.

The block 2b3 is a memory circuit which has a function of storing the updated coefficient value cn (n) from the block 2b2. This is a storage circuit in which the numerical value co (n) is updated and stored as a new coefficient value cn (n). This memory circuit updates the memory by a read-modify-write function.

The switch circuit 2b4 has a function of changing the flow of the output signal of the memory circuit.
After a series of coefficient update operations based on the error signal e (n) from the block 2-12 is completed in a state where the terminal BC is OFF between N and the terminal BC, the switch is switched to ON between the terminals BC.
The state between the terminals AC is turned off, and the updated coefficient value c is set.
n (n) is sent to the filter unit of the block 2-6 to function to reset the filter coefficient value. The transfer destination of the filter coefficient value is the block 3-2 or 3-7 in FIG.
It is.

As described above, when the video signal input from the line L1 is filtered and output from the line L2, the GCR signal portion included in the video signal is extracted, the GCR pulse and the ghost are detected, and the reference is detected. The function of obtaining the error signal from the difference from the waveform, updating the coefficient value of the filter unit, and sequentially reducing the amount of ghost is the function of the ghost removing device of FIG. 5 based on the ZF method.

The disadvantage of the ZF method based on the configuration of the conventional apparatus shown in FIG. 5 is that as the near ghost is removed and the waveform equalization processing is sequentially performed, the equivalent peak position of the main signal passing through the filter unit is obtained. Is shifted from the sampling point position, causing the ghost removal operation to temporarily fall into a state such as oscillation or divergence, or to converge to a state different from the original convergence state. It is a point that becomes unstable.

On the other hand, the ZF method has a merit that the convergence time is short and the convergence speed is very fast because the processing is very simple, as can be seen from the above-mentioned equation for updating the coefficient of equation (5). It has.

[0035]

The problem to be solved by the present invention is that as the ghost elimination process proceeds, the equivalent peak position of the main signal passing through the filter section shifts from the sample point position. To solve the problem of the stability of the ZF method,
What means should be taken to make a ghost removal device that can bring out the original merits of the law?

[0036]

Therefore, in order to solve the above-mentioned problems, the present invention provides:

An input signal is a first signal,

A transversal filter to which the first signal is supplied and outputs a second signal;

The second signal is supplied, and a regularly inserted reference signal for ghost removal is taken in.
A waveform capturer that outputs as a signal of

A synchronous adder to which the third signal is supplied and which outputs a fourth signal obtained by averaging the third signal a predetermined number of times to reduce noise components;

A waveform converter to which the fourth signal is supplied and which outputs a fifth signal which is a reference pulse obtained by processing the fourth signal;

A reference waveform generator for outputting a reference waveform synchronized with the fifth signal for comparison with the fifth signal;

A subtracter to which the fifth signal and the reference waveform are supplied, subtracts the two signals and outputs a sixth signal which is an error signal;

A ghost eliminator, comprising: a coefficient generator that is supplied with the sixth signal and sequentially updates coefficient values set in the transversal filter;

A phase adjuster is provided between the coefficient former and the transversal filter,

The phase adjuster is supplied with one of the signal obtained by converting the waveform of the fourth signal and the reference pulse which is the fifth signal, and converts the supplied signal into the reference pulse. A deviation between the original peak position of the waveform of the reference pulse and the peak position detected on the sample point of the reference pulse is detected, and the coefficient value is subjected to a phase adjustment process so that both peak positions coincide on the sample point. A ghost removing device is provided.

[0047]

FIG. 1 is a diagram showing a first embodiment of a ghost removing device according to the present invention. FIG. 2 is a diagram showing a configuration diagram and an impulse response of a digital filter in the phase adjuster, and FIGS. 3 and 4 are explanatory diagrams of the operation. In the operation explanatory diagram, for convenience,
A simplified simulation expression is also used. Further, even when a digital circuit is given as a specific circuit example, a signal waveform may be shown as an analog waveform in order to make the operation description easy to understand.

In FIG. 1, reference numeral 1-6 denotes a filter unit,
9 is a waveform acquisition unit, 1-10 is a synchronous adder, 1-11 is a waveform converter, 1-12 subtractor, 1-13 is a reference waveform generator, 1-14 is a coefficient former, and 1-8 Is a phase adjuster.

For convenience of explanation, signal delays due to the processing time of each circuit itself, and delay circuits and the like normally used only for simply correcting the delays are omitted unless necessary for the sake of explanation. I do.

The input signal applied to the line L1 handled by the ghost removing apparatus is, for example, a TSC of the NTSC broadcasting system whose frequency band is up to fm (about 4 MHz) as shown in FIG.
V video signal.

Block 1-6, Blocks 1-9 to 1-1
The function of No. 3 is exactly the same as the function of Block 2-6 and Blocks 2-9 to 2-13 in the conventional example of FIG. 14 and the phase adjusters 1-8 will be mainly described.

Coefficient generator 1-14 and phase adjuster 1-8
FIG. 1B shows a specific example of the configuration. In the figure, two blocks surrounded by a dashed line are coefficient forming units 1-1, respectively.
4 and a phase adjuster 1-8. B-1, b-2, b-3, and b-4 of the coefficient former 1-14 are respectively shown in FIG.
2b1, 2b2, 2b3, and 2b4. The newly added block b-5 is a switch circuit for switching a write signal to the memory circuit b-3. The operation of FIG. 1B will be described together with the time chart of FIG. 7H to clarify the time relationship of each process.

The first block b-1 is an amplifier for giving a predetermined magnification α to the input error signal e (n). The resulting output is αe (n). Next block b
-2 subtracts and synthesizes a coefficient value co (n) input from the memory circuit b-3 via the switch circuit b-4 and the amplified error signal αe (n) to form a new coefficient. Numerical value c
This is a subtractor for obtaining n (n). (See Equation 5)

The memory circuit b-3 is used to store coefficient values, and the blocks b-5 and b-4 are two-circuit switches for switching signals when writing and reading data in the memory circuit. Circuit. In the figure, the memory circuit is read. Modification. It is set to the write state (ON between terminals AC and OFF between terminals BC of the switch circuit), and the updated coefficient value cn from block b-2
(N) will be written. The processing from the updating of the coefficient values to the storage in the memory circuit is performed within the TA time of the section A in FIG.

After the ghost detection section A in FIG. 7 (h), the connection of the switch circuits b-5 and b-4 becomes another.
Connection state (ON between terminals BC, OF between terminals AC
F), the memory circuit b-3 to the switch circuit b-
The updated coefficient value cn (n) is called via 4;
This is processed by the next-stage phase adjuster 1-8. Thereafter, the coefficient value c (n) after the phase adjustment by the phase adjuster 1-8 is stored again in the memory circuit b-3 via the switch circuit b-5. The processing time zone of this system is performed in the section C in relation to the processing system described later.

The phase adjuster 1-8 will be described. Outputs from the switch circuit b-4 of the coefficient former 1-14 at the preceding stage are output to blocks b-11 and b-1 in the phase adjuster 1-8.
2, b-13. Each of these three blocks is a digital filter circuit having a configuration as shown in FIG. 2A, but the coefficient values constituting the digital filter circuit are set to different values. The digital filter circuit shown in FIG. 2A is similar to the digital filter circuit shown in FIG.
This is the same FIR filter as C, and the delay time is T
(= 1 / (4fsc)) 16 cascade-connected delay circuit groups 4-1 and input / output signals of each delay circuit are supplied.
It comprises a group of 17 coefficient setting circuits 4-2 for giving and amplifying an arbitrary coefficient value, and a combiner 4-3 for adding and combining the 17 signals amplified here.

Digital filter circuits b-11 and b-1
The difference between 2 and b-13 is the coefficient value set in the coefficient setting circuit group 4-2 numbered from -8 to 8. The amplitude characteristics of these three digital filter circuits are the same,
It has characteristics of a low-pass filter as shown in FIG. Until the frequency f is fm (4 MHz), the amplitude characteristic is flat, and from fm to fc (= 1 / (2fsc)), the characteristic is attenuated in a cosine wave. When the three digital filter circuits are represented by impulse responses, each of them is shown in FIG.
(A), (b), and (c). That is, FIG. 4A shows a low-pass filter having a lagging phase, FIG. 4B shows a low-pass filter having the same phase, and FIG. 4C shows a low-pass filter having a leading phase. The characteristics of these three low-pass filters can be expressed as follows.

[0058]

(Equation 6)

In the above equation, A (f) is the amplitude characteristic of the low-pass filter, T1 is the time shift amount, and w0 (t) is the window function in the time domain.

Returning to FIG. 1B, the next block b-
Reference numerals 14, b-15 and b-16 denote a single switch circuit. The output of the digital filter circuit b-11 is applied to the switch circuit b-14, and the digital filter circuit b-
The output of the digital filter circuit b-13 is applied to the output of the switch circuit b-1.
6 is added. In the figure, only the switch circuit b-15 is O
At N, b-14 and b-16 are in the OFF state, and thus one of the three switch circuits is used in the ON state. The ON / OFF switching control signal is supplied from the block b-22. The output lines of the three switch circuits are combined into one and output.
One transfer destination of this signal is the filter unit 1-6. Another transfer destination is the switch circuit b-5 in the coefficient forming unit 1-14, and a new coefficient value C whose phase has been adjusted.
(N) is stored in the memory circuit b-3. This low-pass filter for phase adjustment (blocks b-11, b-12, b-1)
The processing in 3) is performed in the section C of FIG.

Next, the switch circuits b-14, b-15,
The method of forming the control signal supplied to b-16 will be described. In FIG. 1B, first, a signal y (n) from the waveform converter 1-11 is supplied to a block b-17 in the phase adjuster 1-8.
And b-19. A block b-17 is a peak detection circuit that obtains the position information of the sample point giving the maximum value in the ghost detection range in FIG. When the position (sample point) at which the maximum value is obtained is obtained, this is sent to the next stage as a pulse signal.

The next block b-18 is a time correction circuit, and the time t1 + t2 (where t1 is-
This is a circuit that gives a delay time of (the absolute value of t1) to an input signal and outputs the input signal. The peak position information thus obtained is used as a load pulse for the latch circuit of the block b-22. In FIG. 7H, the processing of the peak detection circuit b-17 is performed in the section A, and the processing of transmitting a pulse signal representing the position information of the peak is performed in the section C. Section B is consumed by the time correction circuit b-18.

On the other hand, FIG. 1 in which the signal y (n) is supplied
A block b-19 shown in (b) is a difference circuit, and its circuit configuration is as shown in FIG. Block 4 in FIG. 2A when considered as a difference circuit b-19.
The coefficient value of 2 is a value of +1 for blocks -8 to -1 and a value of -1 for blocks 1 to 8. When the impulse response of the difference circuit, that is, the digital filter, is obtained, the result is as shown in FIG. 2B (where N = 8 in the figure).
The processing in the difference circuit b-19 is processing for detecting the left and right waveform symmetry of the GCR pulse in the signal y (n) at the peak position described above. If the difference value is 0, there is symmetry. If the difference value is positive, the original peak position is delayed, and if the difference value is negative, the original peak position is advanced. In FIG. 2B, the value of N = 8 is set to enhance noise resistance.

FIG. 3 shows three examples of y (n) near the GCR pulse. FIG. 3A shows an example in which the peak position pk of the GCR pulse coincides with the position of the sampling point y (0), and FIG. 3B shows the original peak position pk of the GCR waveform.
Is an example at a position slightly delayed from the position of the sample point y (0), and FIG.
The vicinity of the waveform is disturbed, and the peak position pk is also changed to the sampling point y.
This is an example in a position slightly behind the position of (0). FIG.
In the cases of (b) and (c), when the difference processing is performed by the difference circuit b-19 of the phase adjuster 1-8, n = 0, that is, a positive value at the position of y (0).

The waveform of FIG. 3 (b) is exactly the same as the waveform of FIG. 3 (a), and is slightly delayed. Such a time delay often occurs due to the relationship between the input video signal and the clock signal in the AD converter, and the state shown in FIG.
The position of k is between n = 0 and 1 (between y (0) and y (1)) or between n = 0 and -1 (between y (0) and y (-1)). Is common. Such a shift in the position of pk is corrected by adjusting the phase of the coefficient value set in the filter unit 1-6 by the phase adjuster 1-8, and the position of pk is made to sequentially coincide with y (0). Can be.

Block b-20 in FIG. 1B is a delay circuit for time correction. This time correction is a circuit for time alignment with the above-described peak position detection system.

A block b-21 is a comparator, which determines whether the difference value supplied from the difference circuit b-19 via the delay circuit b-20 is a negative value, zero, or a positive value. In response to this, it has a function of sending out positive logic discrimination signals from the lines la, lb, and lc, respectively.

The next block b-22 is a latch circuit, as described above, and receives the signals of the lines la, lb, and lc at the peak position from the time correction circuit b-18. The captured signal is output line l
Through d, le, and lf, switch circuits b-14, b-
15 and b-16 are supplied as control signals for switch ON / OFF.

Considering the operation timing on the time chart shown in FIG. 7H, the difference processing of the difference circuit b-19 is performed in the section A, and the time correction of the delay circuit b-20 is also performed in the section A.
And the processing of the comparator b-21 is performed in the section B. The switch control signal latched by the block b-22 in the section B is equal to the switch circuits b-14 to b- in the section C.
The digital filter circuits b-11, b-12, and b are used as control signals for opening and closing
It has a function of selectively outputting the signal from -13.

As described above, the phase adjustment is performed by the circuit having the configuration shown in FIG. 1B by changing the phase of the coefficient value of the digital filter set in the filter section 1-6 shown in FIG. 1A. As described above, the amplitude characteristics of the filters of the digital filter circuits b-11, b-12, and b-13 in the phase adjuster 1-8 are flat up to the frequency fm as shown in FIG. Even at high frequencies, it gradually attenuates. Therefore, when the coefficient value set in the filter section 1-6 is repeatedly passed through this phase adjuster 1-8, the characteristics of the filter section 1-6 gradually progress in the direction of the thick arrow in FIG. Specifically, the characteristics shown in FIG. Since the frequency band of the input video signal is up to fm, the characteristics of the filter unit 1-6 gradually approach the characteristics of FIG. 9A, in other words, the filter unit 1-6.
Gradually enhances the ability to remove out-of-band components (eg, noise components) of the video signal. Accordingly, in addition to the original function of adjusting the peak position, the phase adjuster 1-8 performs the function of removing noise outside the band of the input video signal.

The switch circuit b-1 shown in FIG.
4, b-15 and b-16, when forming control signals to be supplied to the above embodiment, the method using the GCR pulse from the waveform converter 1-4 has been described. The same processing can be performed by using a signal obtained by subjecting the GCR waveform, which has been described above, to differential processing by a circuit as shown in FIG.

As described above, in the ghost removal processing according to the present invention, the phase adjuster 1-8 is provided after the coefficient former 1-14.
, The peak position of the GCR pulse is held at the sample point, so that the instability problem of the conventional ZF method is solved, the stability is improved, and the convergence speed is fast. Make the most of the features. Further, by repeatedly using the phase adjustment of the phase adjuster 1-8, there is an effect of improving the image quality such that the noise component outside the band of the video signal is greatly reduced.

In the above embodiment, the procedure has been described in which the phase is adjusted using the coefficient value updated based on the error signal. However, the updated coefficient value is not always used each time, but is stored in the memory. A process of reading the written coefficient value, adjusting the phase, and writing the coefficient value to the memory again can be repeatedly performed. In this way, the arrangement of the coefficient values, that is, the phase can be changed without changing the amplitude distribution of the coefficient values.

Next, a second embodiment will be described. FIG.
Is a block diagram of the second embodiment, and FIGS. 11 and 12 are operation explanatory diagrams. The operation explanatory diagram also employs a simplified simulated expression method for convenience. Further, even when a digital circuit is given as a specific circuit example, a signal waveform may be shown as an analog waveform in order to make the operation description easy to understand.

For convenience of explanation, signal delays due to the processing time of each circuit itself, and delay circuits and the like normally used only for simply correcting the delays are omitted unless necessary for the sake of explanation. I do.

The input signal of this embodiment is a video signal of an NTSC broadcasting television whose frequency band is up to fm (about 4 MHz) as in the first embodiment.

The functions of blocks 1-1 to 1-14a of the second embodiment shown in FIG. 10A are completely the same as the functions of blocks 2-1 to 2-14 of FIG. Therefore, the description thereof is omitted here, and the control signal generator 1-15 and the phase adjuster 1-16 constituting the phase adjustment circuit, which is a feature of the second embodiment, will be mainly described.

Control signal generator 1-15 and phase adjuster 1
FIG. 10B shows a specific configuration example of −16. Two blocks surrounded by broken lines in the figure are a control signal generator 1-15 and a phase adjuster 1-16, respectively. FIG. 10 (b)
The operation is described in conjunction with the time chart of FIG.
The time relationship of each process will be clarified.

The signal y (n) from the waveform converter 1-11 shown in FIG. 10A is applied to blocks b-1 and b-3 in the control signal generator 1-15. Block b-1
Is a peak detection circuit, which is a circuit for obtaining position information of a sample point giving the maximum value in the ghost detection range of FIG.

The next block b-2 is a time correction circuit for matching the time consumed in the difference processing system of blocks b-3 to b-6. Peak detection circuit b-
The peak position information obtained by 1 and the time correction circuit b-2 is used as a load pulse of a latch circuit (described later) of the block b-6. In the time chart of FIG. 7H, peak detection is performed in the section A, and a pulse signal indicating the position information of the peak is sent out through the time correction circuit b-2 in the section C.

On the other hand, FIG. 1 in which the signal y (n) is supplied
The block b-3 shown in FIG. 0 (b) is a difference circuit, and the circuit configuration is the configuration of the digital filter shown in FIG. 2 (a). The coefficient value is +1 for blocks -8 to -1 and -1 for blocks 1 to 8. When the impulse response of this digital filter is obtained, FIG.
N = 8 in the figure). The processing in the difference circuit b-3 is performed by the GCR in the signal y (n) at the aforementioned peak position.
This is a process for detecting the left and right waveform symmetry of the pulse. If the difference value is 0, there is symmetry. If the difference value is positive, the original peak position is delayed, and if the difference value is negative, the original peak position is advanced. FIG.
In (b), the value of N = 8 is set to enhance noise resistance.

FIGS. 12A to 12C show three examples of y (n) near the GCR pulse. FIG. 12A shows the GC
FIG. 12B shows an example in which the peak position pk of the R pulse coincides with the position of the sampling point y (0), and the original peak position pk of the GCR waveform is shifted from the position of the sampling point y (0). FIG. 12C shows an example in which the vicinity of the GCR waveform is disturbed by a proximity ghost or the like, and the peak position pk is also slightly delayed from the position of the sample point y (0). It is. In the case of FIGS. 12B and 12C, when the difference processing of the difference circuit b-3 is performed, n = 0, that is, a positive value at the position of y (0).

The waveform of FIG. 12 (b) is exactly the same as the waveform of FIG. 12 (a), and is slightly delayed. Such a time delay often occurs due to the relationship between the input video signal and the clock signal in the AD converter. A state without a time delay as shown in FIG. 12A is a rather rare state. Generally, the position of the peak position pk is between n = 0 and 1 (between y (0) and y (1)) or n = 0 and-
It is usually between 1 (between y (0) and y (-1)). The shift of the pk position is determined by adjusting the phase of the burst signal based on the sampling pulse to the phase adjuster 1-16.
And adjust the position of pk to y (0).
Can be successively matched.

Returning to FIG. 10B, block b-4 is a delay circuit for time correction. This time correction is a circuit for adjusting the time with the above-described peak position detection system (blocks b-1, b-2).

A block b-5 is a comparator, and determines whether the difference value supplied from the difference circuit b-3 via the delay circuit b-4 is a negative value, zero, or a positive value. It sends out the value according to the next stage.

The next block b-6 is a latch circuit as described above, and is a load pulse which is peak position information sent from the peak detection circuit b-1 via the time correction circuit b-2. It latches and stores the state signal of the peak position from the comparator b-5, and sends the state signal as a control signal to the next stage.

Block b-7 is a data conversion circuit.
The input control signals having negative, zero, and positive values are converted into 4-bit data here. The converted control signal is passed through the driver circuit b-8 to the next-stage phase adjuster 1-1.
6 are supplied to the analog switch circuits SW1 to SW4, and serve as control signals for switch ON / OFF.

Considering the operation timing on the time chart shown in FIG. 7H, the difference processing of the difference circuit b-3 is performed in the section A, and the time correction of the delay circuit b-4 is consumed in the section B. The processing of the comparator b-5 is performed in the section C. Further, in the section C, the control signal is latched by the latch circuit b-6, and the control signal is supplied to the phase adjuster 1-16 via the data conversion circuit and the driver circuit.
At -16, phase adjustment is performed. As described above, in this embodiment, the phase adjustment is repeatedly performed for each field after 2 (t1 + t2) when the GCR signal is captured.

The phase adjuster 1-16 shown in FIG.
Is an example configured by a discrete circuit. , R1 to R6 are resistors, C1 to C6 are capacitors, X
1 and X2 are npn transistors, and SW1 to SW4 are commercially available analog switch circuits. Vcc is a power supply voltage to be supplied and has a value of about 5 to 12V.

In FIG. 10B, B in FIG.
Modulation frequency f including burst signal passing through PF1-2
The sc color signal is first applied to the base of the transistor X1 biased by the resistors R1 and R2 after the DC component is cut off by the capacitor C1, and to the emitter terminal with the same polarity.
Then, it is output to the collector terminal with the opposite polarity. Resistance R3
If the resistance values of R4 are equal, signals with different polarities can be obtained. A phase shifter is formed by the following resistor R5, capacitor C2, and capacitors C3 to C6 connected by a switch circuit. The burst signal whose phase has been adjusted by the phase shifter passes through a driver X2 having a resistor R6 as an emitter resistor, and then a synchronous oscillator 1-3 (FIG. 10) at the next stage.
(VCO shown in (a)). Synchronous oscillator 1-3
Thus, a clock signal phase-synchronized with the burst signal is formed.

The transfer function P (f) representing the function of the phase adjustment in the phase adjuster 1-16 is represented by the following equation, where R is R, and C is the combined value of the capacitors C2 to C6.

[0092]

(Equation 7)

Therefore, it is very easy to adjust the value of the capacitor C and change the value of the phase φ in the range of -π / 4 to π / 4, and thereby the phase of the clock is changed from -π to π, that is, , −T / 2 to T / 2 (where T = 1 / fs). The value of the capacitor C is determined by the switch circuit SW1
SW4 is turned ON / OFF by a 4-bit control signal, and various values can be set by changing the combination of capacitors C3 to C6. FIG. 11 is a waveform diagram of the burst signal. The burst signal can be delayed or advanced by changing the value of the capacitor C, or while keeping the amplitude of the burst signal constant. .

By changing the phase of the burst signal in this manner, the phase of the sampling pulse obtained from the synchronous oscillator 1-3 can be changed. Thereby, between n = 0 and 1 (between y (0) and y (1)) as shown in FIG.
Even if there is a peak of the GCR pulse in FIG.
The peak of the GCR pulse can be brought over the sample point by moving the sample point as shown in FIG. Similarly, FIG.
2 (c), between n = −1 and 0 (y (−1) and y
Even if there is a peak of the GCR pulse at (between (0)), the peak of the GCR pulse can be brought over the sample point by moving the sample point as shown in FIG.

As described above, the point where the maximum value is obtained even when the sample point moves is the peak of the GCR pulse.
Since the coefficient update processing in blocks 1-11-2a can be performed, the passage position of the main signal of the filter section 1-6, which is a digital filter, can be determined.
As described above, determining the passing position of the main signal of the digital filter increases the stability of the ZF method.

The control signal generator 1- in FIG.
In the description of No. 15, the signal to be used is converted by the waveform converter 1-1.
Although one GCR pulse is used, the GCR waveform output from the synchronous adder 1-10 may be used after performing a waveform conversion process using a difference or the like.

As described above, in the ghost elimination processing according to the present invention, after the burst signal is taken out by the BPF 1-2, the phase adjuster 1-16 for adjusting the phase of this signal is placed, and the synchronous oscillator (VCO) 1- By adjusting the phase of the sampling pulse from Step 3, the peak position of the original waveform of the GCR pulse is held at the sampling point, so that the problem of the instability of the ZF method is solved, and the convergence speed is improved. The original feature of the ZF method that it is fast comes to life.

As described above, when changing the phase of the sampling pulse, instead of directly changing the phase of the sampling pulse, the phase of the burst signal on which the sampling pulse is based is changed. Is the frequency of the video signal band of fsc (= 3.579545 MHz), which is 1/4 of the frequency of the sampling pulse, so that it can be easily constituted by general low-cost components such as transistors, resistors and capacitors. be able to.

Further, since each component of the above-mentioned two embodiments can be easily constituted by a well-known circuit using a commercially available IC or the like, the entire apparatus can be realized at low cost. Also,
As an application field, it can be applied not only to a TV receiver but also to a VTR, and can be expected to have a mass production effect in a consumer field.

[0100]

As described above, the ghost removing device of the present invention has the following effects.

(A) The ghost eliminator according to the first or second aspect adjusts the phase of the coefficient value set in the filter section so that the original peak position of the GCR pulse (reference pulse) is held at the sampling point. By adjusting with the vessel,
The problem of stability, which was a disadvantage of the ZF method, can be greatly improved. Therefore, the present ghost removing device can always perform a stable ghost removing operation while making the most of the original merit of the ZF method that the convergence time is short.

(B) The ghost elimination device according to claim 1 or 2 suppresses unnecessary components outside the video signal band, such as noise components, by repeatedly filtering the coefficient value of the filter unit with a phase adjuster. The low-pass filtering characteristics that can be achieved can be realized, and the image quality is also improved.

(C) The ghost eliminator according to the third or fourth aspect is characterized in that after the band pass filter for extracting the burst signal,
By providing a phase adjustment circuit for adjusting the phase of the burst signal and adjusting the phase of the sampling pulse generated by the synchronous oscillator, the peak position of the original waveform of the GCR pulse (reference pulse) can be held at the sampling point. Therefore, the position of the main signal passing through the filter section which is a digital filter is determined. Therefore, the problem of the instability of the ZF method is solved, the ghost removal operation is stabilized, and the inherent advantage of the ZF method, that is, the fast convergence speed, can be maximized.

(D) The ghost eliminator according to claim 3 or 4 adjusts the phase of the sampling pulse by changing the phase of the burst signal whose frequency is sufficiently lower than that of the sampling pulse, so that it is inexpensive and simple. A phase adjustment circuit having a simple circuit configuration can be used, and costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 shows blocks b-11 to b13 and b-1 shown in FIG.
9 is a specific configuration diagram of FIG.

FIG. 3 is an operation explanatory diagram of the first embodiment.

FIG. 4 is an operation explanatory diagram of the first embodiment.

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is a diagram illustrating a specific configuration example of a filter unit.

FIG. 7 is an operation explanatory diagram of the conventional example and the first embodiment.

FIG. 8 is an operation explanatory diagram of a conventional example.

FIG. 9 is an operation explanatory diagram of the conventional example and the first embodiment.

FIG. 10 is a block diagram of a second embodiment.

FIG. 11 is an operation explanatory diagram of the second embodiment.

FIG. 12 is an operation explanatory diagram of the second embodiment.

[Explanation of symbols]

 1-6 Filter Section (Transversal Filter) 1-8 Phase Adjuster 1-9 Waveform Capturer 1-10 Synchronous Adder 1-11 Waveform Converter 1-12 Subtractor 1-13 Reference Waveform Generator 1-14 Coefficient former

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-296172 (JP, A) JP-A-5-30387 (JP, A) (58) Fields investigated (Int.Cl. ⁶ , DB name) H04N 5/14-5/217

Claims (2)

(57) [Claims] An input signal is a first signal, a transversal filter to which the first signal is supplied and outputs a second signal, and wherein the second signal is supplied and regularly inserted. A waveform capturer that captures a ghost removal reference signal and outputs the captured signal as a third signal, and the third signal is supplied, and the third signal is averaged a predetermined number of times to reduce noise components A synchronous adder that outputs a processed fourth signal, and a waveform converter that is supplied with the fourth signal and outputs a fifth signal that is a reference pulse obtained by processing the fourth signal. A reference waveform generator that outputs a reference waveform synchronized with the fifth signal for comparison with the fifth signal; and the fifth signal and the reference waveform are supplied, and two signals are subtracted. A subtractor that outputs a sixth signal that is an error signal; A ghost removing device that is supplied with the sixth signal and sequentially updates a coefficient value set in the transversal filter; A phase adjuster is provided, and the phase adjuster receives one of a signal obtained by converting the waveform of the fourth signal and a reference pulse being the fifth signal, and the supplied signal From, a deviation between the original peak position of the waveform of the reference pulse and the peak position detected on the sample point of the reference pulse is detected, and the coefficient value is calculated so that both peak positions match on the sample point. A ghost removing device that performs a phase adjustment process. 2. A ghost eliminator according to claim 1, wherein said phase adjuster comprises a low-pass filter, and the low-pass filter has an amplitude characteristic in a frequency domain where a frequency component of said input signal exists. A ghost eliminator characterized by having flat characteristics and gradually attenuating in a higher frequency region.