JP2849086B2 - Integrated bias circuit - Google Patents

Description

The present invention relates to a bias circuit used in a semiconductor integrated circuit, and more particularly to an integrated bias circuit capable of reducing the number of elements and the number of wiring leads. [Prior Art] FIG. 3 shows a conventional integrated bias circuit. In the figure, B is a constant voltage power supply, and R6 and Q14,
Q15, Q16, Q17 and Q18 are resistors and transistors that constitute a PNP-type constant current (current mirror) circuit 11,
Q19 and Q20 are transistors forming the first bias source 12a, Q4, Q5 and Q6 are constant current transistors forming the constant current circuit 3a, and C1 is a first power supply circuit block (load). Similarly, Q21, Q22 and Q23, Q24 are the second and third, respectively.
Q8, Q9, Q10 and Q12, Q13, Q14 are constant current transistors that constitute the second and third constant current circuits 3b and 3c, respectively, and C2 and C3 Are second and third electronic circuit blocks (loads), respectively. B1, B2, and B3 are respectively a bias source 12a and a constant current circuit 3a, a bias source 12b and a constant current circuit 3b, and a bias source 1
This is a first, second, and third bias circuit constituted by 2c and a constant current circuit 3c. Next, the operation will be described. In the PNP-type constant current circuit 11 shown in FIG. 3, the base potential of the transistor Q15 is B− (V _BE14 + V _BE15 ) (1) (where V _BE14 and V _BE15 are between the base and emitter of the transistors Q14 and Q15). The current I0 flowing through the resistor R6 is Becomes This current I0 becomes the collector current of the transistor Q14 (the base current IB15 of the transistor Q15 is small and I0 >> IB1
5 and can be ignored), transistors Q14, Q1
8, Q17, Q16 are configured in the same integrated circuit chip, each collector current I0, I1, I2, I3 and its collector area is proportional, each collector area is S14, S18, S17, S16 Then, equation (3) holds. Here, if S14 = S16 = S17 = S18, I0 = I1 = I2 = I3 (4) Then, from the PNP constant current circuit 11, the bias circuits B1,
The constant currents I1, I2, I3 supplied to B2, B3 respectively are
Transistors of NPN bias sources 12a, 12b, 12c constituting biases of second and third electronic circuit blocks (loads) C1, C2, C3
It is supplied to Q19, Q21 and Q23. Here, in the first constant current circuit 3a, the transistor Q1
9, Collector currents I1, I4, I5, I6 flowing in Q4, Q5, Q6 and their respective emitter sizes are proportional, and if each emitter size is S19, S4, S5, S6, Becomes Here, if S19 = S4 = S5 = S6, then I1 = I4 = I5 = I6 (6) (However, the base current IB20 of the transistor Q20 is I1 >> IB2
Also, the second and third constant current circuits 3b and 3c are similar to the first constant current circuit 3a described above, and the collector currents I8, I9,
It is possible to set I10 and I12, I13, I14. Generally, an electronic circuit configured by an integrated circuit includes a plurality of sets of electronic circuit blocks. FIG. 3 shows an example of a configuration composed of three sets of electronic circuit blocks C1, C2, and C3.
Crosstalk between electronic circuit blocks is reduced, and overall characteristics as an integrated circuit can be improved. When designing a pattern with an integrated circuit, the first bias circuit B1, the electronic circuit block C1, and the second bias circuit B2, the electronic circuit block C2, and the third bias circuit B3 and the electronic circuit block C3 are connected to each other. Lay out in blocks. This is for improving characteristics and reducing costs. Therefore, a PNP having three transistors Q16, Q17, Q18
Three sets of bias circuit blocks B1, B2, B3 from the constant current circuit 11
It is necessary to wire to each. However, when an integrated circuit is configured in this manner, the number of wirings increases with an increase in the number of bias circuits, which causes various disadvantages in characteristics and chip size. [Problems to be Solved by the Invention] As described above, in an integrated circuit, an electronic circuit is divided into circuit blocks in order to improve its overall characteristics. Therefore, in a conventional integrated bias circuit, a constant current source is used. The wiring that connects the PNP transistor and the constant current source to each block and each block is required for each electronic circuit block, and when integrated circuits are used, the chip size increases and the cost increases. there were. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional device, and can reduce the number of elements and the number of wirings, can reduce the chip size of an integrated circuit, and also prevent signal deterioration. It is an object of the present invention to obtain an integrated bias circuit capable of performing the following. [Means for Solving the Problems] An integrated bias circuit according to the present invention has a first output node and a collector connected to the first output node,
A first transistor having an emitter connected to the ground node; an emitter connected to the base of the first transistor; a base connected to the first output node; and a collector providing a voltage that does not cause the transistor to be saturated. A second transistor connected to a possible voltage source, a first resistor connected at one end to a power supply node, the other end connected to the base of the second transistor, and one end connected to a ground node; A second resistance means having the other end connected to the emitter of the second transistor, and a constant voltage generation circuit for generating a first constant voltage from the first output node, each of which has a first input The base is connected to the node, the second output node, and the first input node, and the emitter is connected to the second output node to supply a voltage that does not cause the transistor to be saturated. A level shift transistor having a collector connected to a possible voltage source; and third resistance means having one end connected to a ground node and the other end connected to the emitter of the level shift transistor. A first constant voltage from a first output node of the circuit to a first
, A plurality of level shift circuits for receiving a second constant voltage level-shifted from a second output node, and a first output node of the constant voltage circuit and each of the plurality of level shift circuits. Filters provided between the first input node and the first input node for blocking noise components, and provided corresponding to the plurality of level shift circuits; a second input node; a third output node; A constant current transistor having a base connected to the input node, a emitter connected to the ground node, and a collector connected to the third output node, and a second constant voltage from the level shift circuit. A constant current circuit that receives a bias current that is a constant current from a third output node based on the second constant voltage and that is provided corresponding to the plurality of constant current circuits. Third constant current times, each corresponding
And a plurality of electronic circuit blocks that are connected to the output node and driven by a bias current. [Operation] In the present invention, a first transistor having a first output node, a collector connected to the first output node, an emitter connected to a ground node, and an emitter connected to a base of the first transistor. A second transistor having a base connected to the first output node, a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to be saturated, one end connected to a power supply node, and the other end connected to a power supply node. Is connected to a first resistor means connected to the base of the second transistor, and one end is connected to a ground node;
A second resistance means having the other end connected to the emitter of the second transistor, and a constant voltage generating circuit for generating a first constant voltage from the first output node;
, A second output node, a base connected to the first input node, an emitter connected to the second output node, and a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to be saturated. Level shift transistor, and third resistance means having one end connected to the ground node and the other end connected to the emitter of the level shift transistor, and a first output node of the constant voltage circuit. A plurality of level shift circuits receiving a first constant voltage from a first input node to generate a second constant voltage level-shifted from a second output node, a first output node of the constant voltage circuit And a first input node of each of the plurality of level shift circuits.
A filter for blocking a noise component, provided corresponding to the plurality of level shift circuits, a base connected to the second input node, the third output node, and the second input node;
A constant current transistor having an emitter connected to the ground notebook, and a collector connected to the third output node;
A constant current circuit that receives a second constant voltage from the level shift circuit at a second input node, and outputs a constant bias current from a third output node based on the second constant voltage; Since a plurality of constant current circuits are provided corresponding to the plurality of constant current circuits, each of which is connected to the third output node of the corresponding constant current circuit, and is provided with a plurality of electronic circuit blocks driven by a bias current, a constant current circuit is provided. The voltage circuit and each level shift circuit can be connected by one line, and the number of elements can be reduced. In addition, by providing a filter, crosstalk, noise, and the like between circuit blocks are removed by this filter. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an integrated bias circuit according to one embodiment of the present invention. In FIG. 1, Q1, Q2 and R
1, R2 are transistors and resistors constituting a constant voltage circuit 1 for supplying a constant voltage to a bias system, Q3 and R3 are transistors and resistors constituting a first level shift circuit 2a, and Q7 and R4 are second transistors. Level shift circuit 2b
, And Q11 and R5 are the transistors and resistors that form the third level shift circuit 2c. F1, F2, and F3 are low-pass filters each including a resistor R and a capacitor C, and are provided between the constant voltage circuit 1 and each of the level shift circuits 2a to 2c. Next, the operation will be described. The current I1 flowing through the resistor R1 in the constant voltage circuit 1 of FIG.
0 is (Where V _BE1 and V _BE2 are forward saturation voltages between the base and the emitter of the transistors Q1 and Q2). Assuming that the current flowing through the resistor R2 is I20, I20 = _VBE1 / R2 (8), and the collector voltage Vc1 of the transistor Q1 is Becomes (However, k is Boltzmann's constant, q is the charge of electrons, T is the absolute temperature, Is is the reverse saturation current of transistors Q1 and Q2, and A1 and A2 are the emitter areas of transistors Q1 and Q2.) Next, resistor R3 Assuming that the current flowing through the transistor is I30, I30 = V _BE3 / R3 (10) (where V _BE3 is the forward saturation voltage between the base and the emitter of the transistor Q3) and the transistor serving as the output of the level shift circuit 2a The emitter voltage V _{E3 of} Q3 is It is. (However, A3 is the emitter area of the transistor Q3.) The output V _E3 of the level shift circuit 2a is applied to the base of the transistor Q4, and from V _E3 = V _BE4 , And therefore Here, if A1 = A2 = A3 = A4, then I40 = I10 · R3 / R2 (13) Similarly, when the emitter areas of the transistors Q5 and Q6 are A5 and A6, respectively, Becomes When the reference current I10 and the emitter area of the transistor are determined in this manner, the bias currents I40, I50, and I60 become resistors R2,
This is the function of R3 (Equations (12) to (15)). Second and third level shift circuits 2b and 2c, constant current circuit 3
b, 3c, the respective bias currents I80 to I100 and I120
~ I140 can be set in the same manner as above. When a pattern of an integrated circuit is designed using such a circuit of the present embodiment, the first and second patterns are designed in the same manner as in the conventional pattern design.
2. Performance of laying out the third level shift circuits 2a, 2b, 2c and the first, second, and third constant current circuits 3a, 3b, 3c collectively in each block of the bias circuits B10, B20, B30 This is for improvement and chip size reduction. Here, when wiring to the three sets of bias circuits B10, B20, and B30, it is only necessary to wire each of the constant voltage circuits 1 in series, so that only one wiring is required, which increases the chip size and the cost. Can be prevented from rising. Also, the constant voltage circuit 1 and the level shift circuits 2a, 2
Since filters F1, F2, and F3 are provided between b and 2c, crosstalk and noise between circuit blocks are reduced and signal quality is reduced as compared with a case where no filter is provided. Be improved. In the present embodiment, a configuration having three sets of bias circuits has been described. However, a configuration having N sets of bias circuits may be provided, and the same effects as those of the above-described embodiments can be obtained. FIG. 2 shows a circuit according to another embodiment of the present invention.
These are transistors Q1, Q4, Q5, Q6, Q8, Q9, Q10, Q12, Q13, Q1
The resistances R _E1 , R _E4 , R _E5 , R _E6 ,
R _E8 , R _E9 , R _E10 , R _E12 , R _E13 , and R _E14 are respectively inserted. By inserting these resistors, the effects of the current bogging, the Early effect, and the like are reduced, and the characteristics are improved. An integrated circuit using these bias circuits can be widely used in various consumer and industrial fields. [Effects of the Invention] As described above, according to the integrated bias circuit of the present invention, the first output node and the collector connected to the first output node and the emitter connected to the ground node are connected to the ground. A first transistor, an emitter connected to a base of the first transistor, a base connected to the first output node, and a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to be saturated. Transistor, one end connected to a power supply node, the other end connected to the base of the second transistor, a first resistance means, one end connected to a ground node, and the other end connected to the second
Constant voltage generating circuits for generating a first constant voltage from the first output node, each of which has a first input node; A level shift transistor having an output node, a base connected to the first input node, an emitter connected to the second output node, and a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to saturate; Third resistance means having one end connected to a ground node and the other end connected to the emitter of the level shift transistor, and a first constant voltage from a first output node of the constant voltage circuit. A plurality of level shift circuits for receiving a first input node and generating a second constant voltage level-shifted from a second output node; a first output node of the constant voltage circuit; A filter provided between each of the first input nodes of the bell shift circuit for blocking noise components, a second input node provided corresponding to the plurality of level shift circuits, and a third output node Nodes and
A constant current transistor having a base connected to the second input node, an emitter connected to the ground node, and a collector connected to the third output node, and a second constant voltage from the level shift circuit. To the second input node,
A constant current circuit that outputs a bias current that is a constant current from a third output node based on the second constant voltage; a constant current circuit provided corresponding to the plurality of constant current circuits, Since a plurality of electronic circuit blocks connected to the third output node and driven by a bias current are provided, the level shift circuit and the constant voltage circuit of each circuit block are connected by only one wiring. The number of elements can be reduced because the wiring is reduced and the constant current (current mirror) circuit corresponding to each block becomes unnecessary.
This is effective in reducing crosstalk and noise between circuit blocks, reducing noise and preventing oscillation, and can simplify the device and obtain a highly accurate device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an integrated bias circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention,
FIG. 3 is a circuit diagram showing a conventional integrated bias circuit. 1 ... constant voltage circuit, 2a-2c ... level shift circuit, 3a-
3c Constant current circuit, Q4 to Q6, Q8 to Q10, Q12 to Q14 Constant current transistors, F1, F2, F3 Low pass filters. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A first transistor having a first output node, a collector connected to the first output node, an emitter connected to a ground node, an emitter connected to a base of the first transistor, and a base connected to the first transistor; A second transistor connected to an output node of the first transistor and having a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to saturate; and a second end connected to the voltage source and the other end connected to the second transistor. A first resistor connected to a base; a second resistor connected at one end to a ground node and the other end connected to an emitter of the second transistor; A constant voltage generating circuit for generating a first constant voltage, each of which has a first input node, a second output node,
A level shift transistor having a base connected to the first input node, an emitter connected to the second output node, and a collector connected to a voltage source capable of supplying a voltage that does not cause the transistor to saturate; And third resistance means having the other end connected to the emitter of the level shift transistor, and a first constant voltage from a first output node of the constant voltage circuit to a first input. A plurality of level shift circuits receiving at a node and generating a second constant voltage level-shifted from a second output node; a first output node of the constant voltage circuit and a first of each of the plurality of level shift circuits A filter for blocking a noise component, which is provided between each of the input nodes and a plurality of level shift circuits;
, A third output node, a constant current transistor having a base connected to the second input node, an emitter connected to the ground node, and a collector connected to the third output node. A constant current circuit that receives a second constant voltage from the level shift circuit at a second input node and outputs a bias current that is a constant current from a third output node based on the second constant voltage; Are provided corresponding to the plurality of constant current circuits, and each is connected to the third output node of the corresponding constant current circuit,
An integrated bias circuit comprising a plurality of electronic circuit blocks driven by a bias current. 2. 2. The integrated bias circuit according to claim 1, wherein the filter that blocks the noise component is a low-pass filter including a resistor and a capacitor.