JP2845428B2 - Width multiplier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a width multiplier for performing a 2 ⁱ square operation (i is an integer) of elements of a Galois extended field required when using an error correction code. 2. Description of the Related Art As a conventional technique, when an element of a Galois extended field is represented by a vector, a square operation is performed using a multiplier. FIG. 4 shows a multiplier in the conventional field GF (2 ⁴ ) derived from X ⁴ + X + 1, where 1 is 2
2 GF (2) elements modulo 2 adder, 2 GF (2)
Is a multiplier of the element. In the multiplier configured as described above, two inputs of the multiplier are respectively (a ₃ , a ₂ , a ₁ ,
a ₀ ), the result of the square operation (b ₃ , b ₂ , b ₁ , b ₀ ) is obtained as an output. The 2 ⁱ -th power operation when i> 1 is realized by repeatedly performing multiplication. For example i = when seeking A ⁴ is 2 executes the B = A × A, it is necessary to perform more B × B. When i ≦ −1 (for example, i
==-1 Requires a table on a read-only memory. In the present invention, the elements of GF (2 ^m ) are represented by capital letters (for example, A, B,...)
GF in lowercase letters (eg, a, b, ...)
The element of (2) indicates a constant that is an element of GF (2 ^m ) in α ⁿ . When the elements of the Galois extended field are expressed by exponentials, the square operation is performed by doubling the exponent. FIG. 5 shows this conventional squarer. In the conventional squarer constructed as described above, the exponentially expressed elements ( _cm-1 , _cm-2 ,..., _{Co) are used.} ) As input, and performs a 1-bit rotate shift in the upper direction, and exponential expression (dm _-1 , dm _-2 ,... _Do ) of the result of the square operation = ( _cm-2 , _cm-3) ,…, C
_o , c _m-1 ) is output. In this case, for the 2 ⁱ -th power calculation, i-bit rotate shift is performed in the upper direction. Problems to be Solved by the Invention However, the above configuration has a problem that the circuit scale of the multiplier used for the square operation is very large in the case of the vector representation. In addition, when processing elements in a normal Galois field, not only squaring operation is required but also addition and multiplication are required. In the case of exponential expression, read-only operation is required to perform addition. -There is a problem in that a table on a memory is used, and the circuit scale as a whole becomes very large. In view of the above, an object of the present invention is to provide a width multiplier having a small circuit scale. Means for Solving the Problems The present invention performs a 2 ⁱ square operation (i is an integer) of an element of an extension field GF (2 ^m ) of a Galois field GF (2) on GF (2) for a vector representation of the element. And a linear combination operation means for performing a linear combination operation using an m × m matrix in the above, wherein the linear combination operation means is configured using only a modulo-2 adder. Function The present invention provides a width multiplier whose circuit scale is smaller than that of a multiplier conventionally used for a vector-expressed GF (2 ^m ) element because the circuit scale of the linear combination operation means is very small. Is configured. Embodiment FIG. 1 shows the configuration of a squarer on a field GF (2 ⁴ ) guided by X ⁴ + X + 1 in a first embodiment of the present invention. In FIG. 1, reference numeral 3 denotes a modulo-2 adder for elements of GF (2). The operation of the squarer according to the present embodiment configured as described above will be described below. Input A = (a ₃ , a ₂ ,
a ₁ , a ₀ ), the output B = (b ₃ , b ₂ , b ₁ ,
The calculation for obtaining b ₀ ) = A × A is as follows: When the primitive element of the used field GF (2 ⁴ ) is α = (0010), B = a ₃ · A · α ³ + a ₂ · A · α ² + a ₁ · A · α + a ₀ · A = (a ₃ , a ₁ + a ₃ , a ₂ , a ₀ + a ₂ ) where A · α ³ = (a ₀ + a ₃ , a ₂ + a ₃ , a ₁ + a ₂ , a ₁ ) A · α ² = (a ₁ , a ₀ + a ₃ , a ₂ + a ₃ , a ₂ ) A · α = (a ₂ , a ₁ , a ₀ + a ₃ , a ₃ ) Can be converted to a linear combination operation. Here, the operation represented by + is modulo 2 addition. 1 performs this linear combination operation. As described above, according to this embodiment, by performing the linear combination operation, the conventional example shown in FIG.
A circuit composed of two modulo-2 adders on GF (2) and 16 multipliers on GF (2) can be composed of two modulo-2 adders. FIG. 2 shows X ⁸ + X ⁴ + X ³ + in the second embodiment of the present invention.
Shows a second ^cuber arrangement on the body GF (2 ⁸⁾ guided by X ² +1. In FIG. 2, reference numeral 4 denotes a modulo-2 adder for elements of GF (2). The operation will be explained below 2 ^cuber of the second embodiment constructed as described above. Input A =
_{(A 7, a 6, a} 5, a 4, a 3, a 2, a 1, a 0) with respect to the output B = (b ₇ is a second _{^cube, b 6, b 5, b} 4, b ₃ , b ₂ , b ₁ , b ₀ ) = A × A × A ×
A × A × A × A × A is C = (c ₇ , c ₆ , c ₅ , c ₄ , c ₃ , c ₂ , c ₁ , c
₀₎ = A ² and put and Obtained by the linear combination operation. The circuit of FIG. 2 performs this linear combination operation. As described above, according to the present embodiment, the conventional three GFs
2 ³ square operation circuit that required (2 ⁸⁾ on the multiplier 13 of GF
(2) It can be constituted by the above modulo 2 adder. FIG. 3 shows X ⁸ + X ⁴ + X ³ + in the third embodiment of the present invention.
9 shows the configuration of a 2 ⁻¹ multiplier on a field GF (2 ⁸ ) guided by X ² +1. In FIG. 3, reference numeral 5 denotes a modulo-2 adder for elements of GF (2). The operation of the ^2-1 multiplier according to the second embodiment configured as described above will be described below. Input A = (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ) and the output which is the power of 2 ⁻¹ Is Obtained by the linear combination operation. The circuit of FIG. 3 performs this linear combination operation. According to this embodiment, as described above, by performing a linear combination operation, conventionally the 10 pieces of 2 ^-1 square operation which has been determined using a read-only memory for elements that are vector representation GF ( 2) Above mod 2
It can be obtained by an adder. Incidentally, p ^i-th power calculation in GF (p ^m) (i is an integer) also is possible to configure a small width multiplication unit circuit scale is converted into a linear combination calculation. Effect of the Invention As described above, according to the present invention, for the element A of GF (2 ^m ), its 2 ⁱ power, that is,. The width multiplier for obtaining A ² , A ⁴ ,... Can be configured with a very small circuit scale, and its practical effect is large.

Signal diagram of squarer of the first embodiment in the BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is the present invention, the signal diagram of 2 ^cuber of the second embodiment of FIG. 2 the present invention, FIG. 3 is a signal diagram of a ^2-1 multiplier according to a third embodiment of the present invention, FIG. 4 is a signal diagram of a multiplier used as a conventional squarer, and FIG. It is a signal line diagram of a vessel. 1,3,4,5… GF (2) element modulo 2 adder, 2… GF
A multiplier of the element of (2).

Claims (1)

(57) [Claims] The element of the extension field GF (2 ^m ) of the Galois field GF (2) is subjected to the 2 ¹ operation (i is an integer) by the GF
(2) A width multiplier, comprising: a linear combination operation unit for performing a linear combination operation using an m × m matrix described above, wherein the linear combination operation unit is configured using only a modulo-2 adder.