JP2842880B2 - IC test equipment - Google Patents

Description

The present invention relates to an IC test apparatus for testing an IC such as a memory.

[Prior Art] FIG. 9 shows a conventional IC test apparatus. 10 in the figure is the IC under test
Is shown. Each of the pins of the IC under test 10 is connected to one of the pin electronics cards 20A, 20B, 20C,. Therefore pin electronics cards 20A, 20B, 20C…
.. Are prepared for at least the number of terminals of the IC under test.

Each of the pin electronics cards 20A, 20B, 20C... Has a driving circuit 21 for applying a driving signal to each terminal of the IC under test 10,
A comparator 22 that determines whether or not the response output signal output to each terminal of the IC under test 10 has a regular logic level and captures the signal.
Are implemented. Reference numeral 23 denotes a pseudo load of the IC under test 10 and a resistor serving as a terminating resistor, and reference numeral 24 denotes a mode changeover switch for switching between a calibration mode and a test mode.

In the test mode, the mode changeover switch 24 is controlled to be turned off. In this state, a drive signal is input from the test apparatus 15 to the drive circuit 21 through the variable delay circuit 31, and the response output of the IC under test 10 output from the comparator 22 is output. The signal is a variable delay circuit
The IC under test is taken out through the test device 32 and taken into the test equipment 15
Ten good or bad is determined.

The fact that the phases of the drive signals applied to the terminals of the IC under test 10 in the test mode match, and that the response output signal output from the IC under test 10 does not receive a different phase delay for each pin electronics card, Required for some types of IC test equipment.

For this purpose, each pin electronics card 20A, 20B, 20
C are provided with variable delay circuits 31 and 32. The delay amounts of these variable delay circuits 31 and 32 are adjusted to adjust the phases of the drive signal and the response output signal at the terminals.

It is called adjustment timing calibration or skew adjustment for matching the phases, and is performed periodically while the IC test is being performed.

Conventional timing calibration is performed as follows.
The mode changeover switch 24 mounted on each of the pin electronics cards 20A, 20B, 20C,... Is controlled to be in an ON state. A calibration reference signal RS is provided.

The timing calibration reference signal RS is taken out to the test apparatus 15 through the logic comparator 22 and the variable delay circuit 32, and for each pin electronics card 20A, 20B, 20C,. Card 20A,
The variable delay circuit 32 is adjusted so that all the phases become the same every 20B, 20C,.... By this adjustment, the timing of the system of each logical comparator 22 of each pin electronics card 20A, 20B, 20C... Is calibrated. The adjustment of the variable delay circuits 31 and 32 is performed by outputting the phase measurement result output from the test apparatus 15 as a digital signal,
Set to 2 and adjusted automatically.

Next, a drive signal is given to the drive circuit 21, the drive signal is taken out through the logical comparator 22 and the variable delay circuit 32, and the variable delay circuit 31 is adjusted so that all the phases match, and the timing of the drive circuit system is calibrated. I do.

"Problems to be Solved by the Invention" Each pin electronics card 20A, 20B,
Buffers 41A, 41B, 41C,... Are arranged on a distribution path for distributing the calibration reference signal RS to 20C. For this reason, variations in the delay times of the buffers 41A, 41B, 41C,. It is difficult to remove this timing error.

Therefore, it is conceivable to replace the distributor 40 with a mechanical contact M as shown in FIG. 10, but the waveform of the calibration reference signal RS is distorted by reflection due to impedance mismatch at the contact M, and this waveform distortion Causes a timing error.

When the mechanical contacts M are used, the pin electronics cards 20A, 20B, 20C... Must be calibrated one by one, so that there is a disadvantage that the calibration takes time.

Further, there is a disadvantage that the calibration reference signal RS is distorted due to interference from other signals, and this distortion causes a timing error.

These drawbacks are pin electronics cards 20A, 20B,
The more the number of 20C….

An object of the present invention is to eliminate these disadvantages and to provide an IC test apparatus capable of performing accurate timing calibration in a short time.

[Means for Solving the Problems] In the first invention of this application, a light receiving element is connected to an input side of a logical comparator mounted on each pin electronics card via a switch, and a timing is supplied from a common light source to the light receiving element. Proposes an IC test device that is configured to irradiate a calibration light pulse, generate a light reception pulse from a light receiving element by irradiating this light pulse, and provide this light reception pulse to each logical comparator as a calibration reference signal. It is.

According to the IC test apparatus of the first aspect of the present invention, by driving one light source, a light pulse is applied to the light receiving element provided on each pin electronics card, and a timing signal can be given to the logical comparator at a time. , The delay time of the logical comparator can be calibrated at one time. Therefore, the drive circuit can be calibrated using the calibrated logical comparator.

As described above, according to the configuration of the first aspect of the present invention, since there is no distributor, it is possible to eliminate the influence of variations in the delay time of the buffers and wirings used in the distributor.
Further, since a semiconductor element such as a buffer is not used, a phenomenon in which the delay time of the timing calibration signal fluctuates due to a temperature change can also be eliminated.

Therefore, an IC test apparatus with a small timing error can be provided.

In the second invention of this application, a light emitting element is provided on the output side of a drive circuit of each pin electronics card via a switch, and the light emitting element is driven through the drive circuit to generate a timing calibration light pulse. The light pulse is received by a common light receiving element, and is used as a calibration pulse for the light reception signal.

According to this second aspect, the light emitting element is driven by the drive circuit, the light emitting pulse is received by the light receiving element, and the phase of the light receiving pulse is adjusted to a standard value to calibrate the drive circuit of each pin electronics card. it can. Since the second invention does not use the distributor, the timing error generated in the distributor can be eliminated.

Further, the delay time of the logical comparator can be calibrated using the calibrated drive circuit, and the second invention can also calibrate to a state where the timing error is small.

FIG. 1 shows an embodiment of the first invention of this application. In the first invention of this application, each pin electronics card 20A, 20A
The light receiving element 26 is connected to the input side of the logical comparator 22 of B, 20C... Via a switch 25, and a common light source 50 is provided for the light receiving element 26 to excite the light source 50 so that each electronic card The light receiving element 26 provided in each of 20A, 20B, 20C... Is irradiated with a timing calibration light pulse.

The light source 50 can be, for example, a laser diode, and is excited by a laser drive circuit 51. The laser drive circuit 51 receives a timing calibration reference signal RS from the test apparatus 15.
give. The light source 50 generates a light pulse by the timing calibration reference signal RS, and irradiates the light pulse to the light receiving element 26 provided in each of the pin electronics cards 20A, 20B, 20C.

For example, as shown in FIG. 2, the light receiving element 26 is mounted on the edge of each of the pin electronics cards 20A, 20B, 20C..., The edge is arranged in a circle, and the light source 50 is mounted at the center of the circle.

By arranging the light source 50 and the light receiving elements 26 in this manner, the distance between the light source 50 and each light receiving element 26 can be matched. 60 is a pin electronics card 20A, 20B, 20C ……
Shows a performance board for electrically connecting the device under test 10 to the pin electronics cards 20A, 20B, 20C,.

When a light pulse for timing calibration is emitted from the light source 50 to the light receiving element 26, the light receiving element 26 outputs a light receiving pulse. The switch 25 is controlled to be on during calibration, and the received light pulse is input to the logical comparator 22.

The light receiving pulse input to the logic comparator 22 is a variable delay circuit
It is taken into the test apparatus 15 through 32 as a timing calibration signal RR. The test apparatus 15 measures the delay amount of the timing calibration signal RR with reference to the timing calibration reference signal RS, and adjusts the variable delay circuit 32 so that the delay amount becomes a standard value. , 20
It is possible to calibrate the timing of the path of the logical comparator 22 of B, 20C...

After calibrating the timing of the logic comparator 22, switch 25
Is turned off, and the calibration reference signal DD for calibrating the drive circuit 21 to the drive circuit 21 through the variable delay circuit 31 in that state.
Supply. The calibration reference signal DD is taken out as a calibration signal DR through the logical comparator 22 and the variable delay circuit 32, and the phase difference (delay amount) between the calibration reference signal DD and the calibration signal DR is obtained.
Is measured by the test apparatus 15, and the delay amount of the variable delay circuit 31 is adjusted so that the phase difference becomes a standard value.

With this adjustment, each pin electronics card 20A,
The timing of the path of each drive circuit 21 of 20B, 20C... Is calibrated.

Thus, according to the first invention of this application, it is possible to apply the calibration reference pulse to all of the logical comparators 22 of each of the pin electronic cards 20A, 20B, 20C. At this time, the calibration DR is generated from the light receiving element 26 by an optical pulse. As a result, light receiving pulses are simultaneously generated in the light receiving elements 26 of all the pin electronics cards 20A, 20B, 20C. Since the light receiving pulse is generated by the light emitted from the common light source 50, the phase difference between the pin electronics cards 20A, 20B, 20C... Is very small.

Needless to say, the generation timing of the light receiving pulse does not fluctuate with respect to the temperature, and is stable even with a temperature change.

In the configuration of the first invention, if there is a variation in the sensitivity of the light receiving element 26, an error may occur in the rise of the calibration signal input to the logical comparator 22.
As shown in the figure, the peak values HH and HL of the light receiving pulse are obtained, and the voltage of 1/2 of the peak values HH and HL is set as a threshold voltage for input determination in the logical comparator 22 to obtain the light receiving pulse. A timing error at the time of detecting a pulse can be avoided.

In the embodiment shown in FIG. 2, the light receiving element 26 is mounted on the pin electronics cards 20A, 20B, 20C..., But the light receiving element 26 is mounted on the performance board 60 as shown in FIG. You can also. In this case, if the light receiving elements 26 are densely arranged at the center of the performance board 60, the utilization rate of the optical power can be increased.

Further, as shown in FIG. 5, a rotating mirror 56 which is rotated by a motor 55 is provided, and a laser beam is emitted from the light source 50 toward the rotating mirror 56 so that the position at which the rotating mirror 56 faces the light receiving element 26 is counted. May be configured to irradiate a laser beam from the light source 50 and cause the light receiving element 26 to receive the laser beam.

In addition, as shown in FIG.
The light receiving element 26 is attached to each end of the optical fiber 57.
Can be mounted to optically couple the light source 50 and the light receiving element 26.

Further, as shown in FIG. 7, the light source 50 can be attached to the donut-shaped test head 58 in which the pin electronics card is housed in an annular shape only at the time of calibration. In this example, a case where the test head 58 is mounted on a cart 59 is shown.

 FIG. 8 shows an embodiment of the second invention of this application.

In the second invention, the pin electronics cards 20A, 20A
A light source 27 is connected to the output side of the drive circuit 21 provided at B, 20C,.

At the same time, the light receiving element is located
The light receiving element 52 receives a light pulse emitted from each light source 27. Therefore, in the second invention, the pin electronics cards 20A, 20B, 20C... Are calibrated one by one.

That is, in the second invention, the timing calibration drive signal DD is supplied to the drive circuit 21 through the variable delay circuit 31,
The light source 27 is excited by the drive output of 21 to emit a light pulse. This light pulse is received by the common light receiving element 52, and this light receiving pulse DS is generated.

The phase difference between the light receiving pulse DS and the timing calibration drive signal DD is measured, and the delay amount of the variable delay circuit 31 is adjusted so that the phase difference becomes a standard value. This adjustment is performed for each of the pin electronics cards 20A, 20B, 20C,..., And the delay amount of the system of the drive circuit 21 of each of the pin electronics cards 20A, 20B, 20C,.

After the delay amount of the path of the drive circuit 21 is calibrated, the delay amount of the path of the logical comparator 22 is calibrated next. In this calibration, a timing calibration reference signal DD is supplied to the logic comparator 22 through the variable delay circuit 31 and the drive circuit 21 with the switch 25 turned off, and this timing calibration reference signal DD is Taken through circuit 32, this signal DR
The phase difference between the variable delay circuit 32 and the reference signal DD is measured, and the delay amount of the variable delay circuit 32 is adjusted so that the phase difference becomes a standard value. With this adjustment, the delay amount of the system path of the receiving circuit 22 is calibrated.

In this way, according to the second aspect of the invention, when the drive circuit 21 is calibrated, elements such as buffers are not individually inserted until the drive circuit 21 and the calibration signal DS are generated. As a result, it is possible to accurately calibrate the drive circuit 21 of each of the pin electronics cards 20A, 20B, 20C...

[Effects of the Invention] As described above, according to the present invention, a timing calibration light pulse is generated using a light emitting element, and the logical comparator 22 or the drive circuit 21 is generated using the timing calibration light pulse.
Can be configured.

In particular, according to the first aspect, since the timing calibration reference signal can be given to the circuit (logical comparator 22) for calibrating without using the divider constituted by the electric circuit, the delay amount of the circuit element in the divider is provided. The timing error caused by the difference can be removed, and in this regard, highly accurate calibration can be performed.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the first invention of this application,
FIG. 2 is a perspective view showing an example of the arrangement of a light source and a light receiving element in this embodiment. FIG. 3 is a waveform diagram for explaining a correction method when there is a sensitivity difference between the light receiving elements. FIG. 2 is a perspective view showing another example of the arrangement of the light source and the light receiving element used in the first invention, FIG. 8 is a connection diagram showing an embodiment of the second invention of this application, and FIG. Connection diagram for the
FIG. 10 is a connection diagram showing another example of the prior art. 10: IC under test, 20A, 20B, 20C ... pin electronics card, 21: drive circuit, 22: logic comparator, 25: switch, 26:
Light receiving elements, 31, 32: variable delay circuit, 50: light source.

Claims (2)

(57) [Claims] A pin electronic card mounted with a drive circuit for supplying a drive signal to an IC under test and a logic comparator for determining whether or not a response output signal of the IC under test has a regular logic level and taking in the signal. In an IC tester with more than the number of terminals of the IC under test, a light receiving element is connected to the input side of each logical comparator of the pin electronics card via a switch, and the timing is calibrated from a common light source to this light receiving element. IC test equipment configured to irradiate optical pulses for use. 2. A pin electronic card mounted with a drive circuit for providing a drive signal to an IC under test and a logic comparator for determining whether or not a response output signal of the IC under test has a regular logic level and taking in the signal. In an IC test apparatus provided with at least the number of terminals of the IC under test, a light emitting element is connected to the output side of each drive circuit of the pin electronics card via a switch, and the light emitting element is driven by the drive circuit. An IC test device that emits light, receives this light pulse with a common light receiving element, and uses the received light signal as a signal for timing calibration of a drive circuit.