JP2842602B2 - High quality character generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to, for example, laser printers, CRT displays,
The present invention relates to a high-quality character generation device that generates high-quality characters, symbols, and the like from encoded digital character data in an electronic computer typesetting machine or the like.

[Conventional technology]

There are a dot type and a vector type in digital character generation devices. In the dot method, since characters are stored in advance in the same dot data as when the characters are finally displayed, characters can be easily generated. On the other hand, in this method, it is necessary to code and store a space other than the pixel of the character, so that the data amount for one character is large, and when the size of the same character is different, another character is used. You have to prepare the data,
The capacity of the storage means for storing character data becomes extremely large.

On the other hand, the vector method stores only line segments of characters in the storage means as vector data,
If one character data is stored, its size can be freely changed to a predetermined value and displayed, and the capacity of the storage means can be small.

The vector system further includes a stroke system and an outline (polygon) system. Since the stroke method is configured with a small amount of data, it is possible to display characters at high speed, but it is difficult to express minute changes in the font of characters. On the other hand, in the outline method, since the outline of a character is converted into data, the expression speed is slightly slower than in the stroke method, but a finer typeface can be expressed.

FIG. 2 shows the conventional principle of displaying the character A in the outline method. As shown in the figure, first, the outline of the character A is displayed on the memory constituting the bitmap by a line segment connecting the vertices a to 1. Next, the bit map is scanned, for example, in the x-axis direction, and a position to be drawn (filled) is detected. Then, the searched position (the inside of the outline) is drawn (filled).

[Problem to be Solved by the Invention] As described above, the conventional apparatus once writes the outline of a character on a bitmap, and then scans the bitmap in, for example, the x-axis direction to start and end drawing (filling). Since points are searched and the search is performed from the start point to the end point (filling), the number of accesses to the bitmap increases, and the time to draw characters on the bitmap increases. there were.

The present invention has been made in view of such a situation, and aims to reduce the number of accesses to a bitmap and shorten the drawing time.

[Means for solving the problem]

A high-quality character generation device according to the present invention includes a first storage unit that stores outline data of a character having a plurality of line segments, and a parallel storage device that is parallel to the drawing direction based on the outline data read from the first storage unit. Generates coordinates of contour points corresponding to a line segment in two-dimensional coordinates having coordinate axes, selects an even number of contour points from each of a plurality of lines parallel to the drawing direction, and defines a drawing start position and a drawing end position. Contour coordinates generating means for outputting as drawing points to be drawn, and sorting means for rearranging the drawing points obtained from the contour coordinate generating means in each line along a drawing direction and further rearranging the lines in order along a plurality of lines. A drawing means for drawing from the odd-numbered drawing point to an even-numbered drawing point for each line based on the coordinates of the drawing points rearranged by the sorting means, and characters drawn by the drawing means. And a second storage means which is,
A coordinate calculating unit that calculates and outputs the coordinates of the contour points in the two-dimensional coordinates for each line segment based on the contour data, and a contour calculating unit that calculates the coordinates of the contour points from the contour points calculated for each line segment by the coordinate calculating unit A first coordinate selection unit that outputs a selected drawing point for each line segment based on a predetermined algorithm, and a coordinate calculation unit that calculates an even number of drawing points for each of the plurality of lines for each line segment And a second coordinate selection unit that selects and outputs 0, 1, or 2 drawing points from the intersection points where the line segments intersect with each other. .

[Action]

The polygon data read from the first storage unit is converted into coordinate data by the generation unit. The coordinate data is selected by the selecting means such that two coordinates are arranged on the same y-axis, for example. The drawing means immediately generates, from the selected coordinates, coordinates that sequentially increase from the first coordinate on the same y-axis to the subsequent coordinates, and generates a second coordinate corresponding to the generated coordinates.
Draw characters in the storage means.

Therefore, the number of accesses to the second storage means can be reduced, and the characters can be drawn faster.

〔Example〕

FIG. 1 shows a basic configuration of a high-quality character generating apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an editor for creating a sentence to be displayed, such as a personal computer. The editor 1 includes a CPU 11 for controlling a text editing operation and a display operation, a hard disk 12 for storing the edited text, and a VR to which data stored in the hard disk 12 is transferred.
It has an AM 13 and a RAM disk 14 for storing outline fonts. Reference numeral 15 denotes a coordinate conversion means (DSP) additionally connected to the editor 1, and a DSP board 16 and a DSP RAM
17 is comprised. DSP board 16 also has RAM 18A, 1
Built-in 8B.

Reference numeral 2 denotes CE system hardware connected between the editor 1 and the laser beam printer (LBP) 3, which includes a contour coordinate generating means (OCG) 21, a sorting means (CADM) 22, a drawing means (RG) 23, and a bit. It has a map 24. The coordinate conversion means 15, the contour coordinate generation means 21, and the drawing means 23 are mutually connected by the DSP external interface bus 5.
Reference numeral 4 denotes a CPU for managing the bitmap 24, which is connected to the drawing means 23 and the bitmap 24 via the VME bus 6.

FIG. 3 is a diagram for explaining an outline of an operation until a character edited by the editor 1 is drawn (stored) in the bit map 24. When creating a text (data) file in the editor 1, the CPU 11 first converts outline font data of characters represented by, for example, 256 × 256 dots stored in the hard disk 12 into a RAM disk in a format that can be easily transferred to the coordinate conversion means 15. Transfer to 14 and memorize.

The RAM disk 14 is composed of 32 banks, as shown in FIG. 4, banks 1 to 31 (FIG. 4 (a)) store font data, and bank 32 (FIG. 4 (b)) stores font data. A search table is stored. The address of the 32nd bank corresponds to the character code, and the upper 4 bits (bk) of the data at each address indicate the bank (one of the 1st to 31st banks) in which the data of the character code is stored. , The lower 28 bits (POINT) are stored in the bank (bk) in which font data corresponding to the character code is stored.
Bank). In the data of each address of the first to 31st banks, a value representing a predetermined command is stored in the upper 16 bits. For example, when the upper 16 bits are H (representing a hexadecimal number) 0001, the start point of the polygon is set to H00FF Indicates the end of the data for one character. The next lower 8 bits contain the X coordinate (x-axis address), the least significant 8 bits contain the Y coordinate (y-axis address),
Each is stored.

Since the lower 28 bits POINT of the 32nd bank represents the address of the font data of the character code, the size of the font data can be obtained from the difference from the POINT of the next address.

A sentence file is created with the outline font stored in the RAM disk 14. It takes time to access the text file while it is stored on the hard disk 12. Then, the CPU 11 causes the created text file to be transferred from the hard disk 12 to the VRAM 13 and stored therein. CPU1
1 further reads character data corresponding to a text file (for example, character A) stored in the VRAM 13 from the RAM disk 14 to create a data packet, and causes the coordinate conversion means 15 to output the data packet together with the command packet.

The coordinate conversion means 15 performs coordinate conversion of the input outline font for enlargement, reduction, inclination, rotation, average movement, and the like of the character. The font data subjected to the coordinate conversion is supplied to the outline coordinate generation means 21.

FIG. 5 shows the format of commands and data sent from the coordinate conversion means 15 to the contour coordinate generation means 21. As shown in the figure, a command is set in the upper 4 bits of a first (FD) word (WORD) composed of 16 bits, and the x coordinate value (Xc) of the vertex coordinates of the polygon is set in the lower 12 bits. The command is set in the upper 4 bits of the second (SD) word (WORD), and the y coordinate value (Yc) of the vertex coordinates of the polygon is set in the lower 12 bits.

 Commands are defined, for example, as shown in the following table.

The outline coordinate generation means 21 calculates and generates outline dot data from the input outline coordinates of the character. The outline dot data is sorted by the sorting means 22, and a combination of odd-numbered dots (odd-numbered dots in order) and even-numbered dots (even-numbered dots in order) is generated. The sorted data is input to the drawing means 23. The drawing means 23 stores the inputted odd-numbered dots and even-numbered dots in the bitmap 24 and its addresses, and draws (paints) the dots between them.

When the CPU sends a command to the output control circuit existing in the bit map 24, the image of the bit map is transferred from the video interface to the laser beam printer, and the characters drawn there are output to the laser beam printer 3, and Is printed on paper.

The input from the VRAM 13 and the RAM disk 14 to the coordinate conversion means 15 and the processing in the CE system hardware 2 are operated in parallel.

Sentence (text) files are described in ASCII text files, and Japanese character codes are expressed in Shift JIS. In the text file, describe the following command,
The contents can be executed.

-Wr value1 value2 value2 (decimal) address on the DSP system
Write (decimal) data ・ re value1 Read data at address of value1 ・ ps Initialize DSP system and prepare for print output ・ pe Print output end ・ pp margin of value1 paper type (A3, A4, etc.) Perform setting ・ pm value1 value2 value1 = 0 Draw with the character size set by .cw value1 = 1 CMT matrix (concatenation of matr
ix transformations) to draw characters by performing coordinate transformation. value2 = 0 Horizontal writing value2 = 1 Vertical writing ・ mg value1 value2 value3 value4 value1 = left margin (left margin) value2 = right margin (right margin) value3 = top margin (top Margin) value4 = bottom margin (bottom margin) ・ sc value1 value2 Step of moving character drawing (character pitch) value1 = X value2 = Y ・ po value1 value2 Absolute specification of character drawing position value1 = X value2 = Y ・ cw value1 value2 drawing character Value1 = X value2 = Y ・ rt value1 Character rotation angle value1 = angle ・ sl value1 Character inclination angle value1 = angle ・ sp value1 Spline conversion division value1 = division number ・ tx = value1 Character drawing Ff Form feed, paper output ・ lf Line feed, with line feed break ・ dg debug ・ rg value1 value2 RG board debug ・ bt value1 valu e2 value3 For RG boat debugging ・ mt value1 value2 value3 value4 CMT matrix setting value1 → CMTA value2 → CMTB value3 → CMTD value4 → CMTE Other lines specified by shift JIS code have drawing effect as character strings.

A program for executing each operation in the CPU 11 is described in C language. In this program, the following 2
Two functions are used.

The first is a main () function, which performs the following processing.

1) set_mode () function This function performs the initial setting specified on the command line.

1a) TEXT_IN Text file is extracted line by line and explained next.
Execute btoj (rramp, buf) (for example, expand a text file in VRAM13).

1b) HEX_SET The instruction code of the DSP is transferred from the CPU 11 to the DSP 15, and the DSP is activated (Trans ()).

2) (* communicat) () function Extract the text file expanded on VRAM13,
In the case of a character, the memory () function is called to combine the font data in the RAM disk 14 into a command packet and transfer it to the DSPRAM (DUAL PORT RAM) 17 of the DSP 15. VR
When the text data of AM13 ends, the variable sys_status
Set to FALSE.

3) Exit from this loop when sys_status is FALSE.

4) Next () function The communication processing of the command packet transferred to the DSP RAM 17 is performed by the (* communicat) () function.

5) Then return to the above 2).

6) When exiting the loop from condition 3) above main ()
The function ends.

The second function is the btoj () function. In the case of this function, one of the text files as shown in from in Fig. 6 (a)
The characters of the line (one character of Shift JIS is 2 bytes) are converted into the pointer of the VRAM 13 as indicated by to. To contains the address (pointer) for the VRAM, and the converted data is written to that address. Note that "$ 0" indicates the end of one line of characters. For example, as shown in FIG.
When the first byte of the from array is Shift JIS code,
The shift JIS is converted to a JIS code Kuten code and transferred to the VRAM13. The line feed “$ n” and the line end “$ 0” are converted into an identification format “Hffff” and a line feed command “H1500” indicating that the subsequent code is not a character but a command. As shown in FIG. 6 (c), when the first byte of the from array is ".", The command number H00 (.wr is the command number H00) is placed after the identification format "Hffff", and then the data size ( In the case of this embodiment 02), then the first data (10) and the second data (10) are set sequentially. As shown in FIG. 6 (d), when the first byte of the from array is "$ n", the identification format "Hffff" and the command set next to it ("$ 0" in this embodiment)
Therefore, it is converted to the line feed command “H1500”).

Next, a flow chart of the operation of the coordinate conversion means (DSP) 15 will be described. As shown in FIG. 7, when the DSP program is loaded from the CPU 11 to the coordinate conversion means 15, the system of the coordinate conversion means 15 is reset and the internal initialization is executed. At this time, DSP15 internal registers and RAM
18 is cleared and the program jump table is set (S1). Next, du of DSP RAM (dual_port RAM) 17
Loading data from al_port0 bank and executing load data (CommandExecute) (S2), incrementing and communicating a counter for communication with CPU11 (ComCounter) (S3), du
Loading data from the al_port1 bank and executing the load data (CommandExecute) (S4), and incrementing and communicating a communication counter with the CPU 11 (ComCounter) (S4)
An endless loop consisting of each subroutine of 5) is executed. That is, as shown in FIG.
It is configured by a port RAM, and communication is performed by a system of the CPU 11, the dual_port RAM0 (or 1), the dual_port RAM1 (or 0), and the DSP board 16. The communication counter counts communication circuits, and determines whether data transfer has been normally performed.

The details of the subroutine (S2) for loading data from the dual_port0 bank and executing the load data are as shown in FIG. 9 (the same applies to the subroutine (S4) for the dual_port1 bank). First, the header of the command packet is input (S11).

As shown in FIG. 10, in the header portion of the command packet, the first 8 bits are empty, the next 8 bits are the command number, and the next lower 16 bits are the size of the data portion following the header portion ( Buffer size) is set.

Next, one of the RAMs inside the DSP board 16 (for example, RAM 18A)
The data part of the command packet is loaded into (RAM0) (S12). Further, according to command numbers 0 to 16 and 20, C
_ExternalWrite (S14), C_ExternalRead (S15), C_Pl
otFont (S16), C_PlotStart (S17), C_PlotEnd (S1
8), C_PaperTypeSet (S19), C_PlotModeSet (S20),
C_MarginSet (S21), C_StepSet (S22), C_PositionSe
t (S23), C_CellWidthSet (S24), C_RotateSet (S2
5), C_SlantSet (S26), C_SplineSet (S27), C_Text
ureSet (S28), C_LineFeed (S29), C_FormFeed (S3
The process proceeds to a subroutine of either 0) or C_CMTSet (S31) (S13).

In the case of the C_ExternalWrite subroutine, as shown in FIG. 11, the command packet consists of a header, followed by a write address (WRITE ADDRESS) and write data (WRITE DATA).
Are sequentially set, and write data is written to the address specified by the write address.

In the command packet in the case of the C_ExternalRead subroutine, as shown in FIG. 12, a read address (READ ADDRESS) is set after the header. In this case, the data written therein is read from the address specified by the read address.

As shown in FIGS. 13 and 14, the command packet of the subroutine C_PlotStart and C_PlotEnd has only a header. In the former case, Plot Start
Is sent to the CPU 4 and a reply from the CPU 4 is received. In the latter case, the mail of the plot end (Plot End) is sent to CAP4, and the reply from CAP4 is received. C_Pa
In the case of the subType of perTypeSet, the paper type (Paper
Type) is transferred to RAM18B as a variable V_PAPER, and RAM18B
Is returned to the initial state. For example, as the initial state, Cell
If the Width (character size) is set to 40 × 40 and the margin is set to the maximum value of the paper, these values are set.

In the case of the C_PlotModeSet subroutine, the command packet has a configuration in which a plot mode (PLOT MODE) is added after the header as shown in FIG. In this case, the plot mode stores the variable V_M in the RAM 18B in the DSP board 16.
Transferred as ODE.

In the case of the C_MarginSet subroutine, the command packet consists of a header and a left margin (LEFT MAR
GIN), right margin (RIGHT MARGIN), top margin (TOP
MARGIN) and the bottom margin (BOTTOM MARGIN). In this case, the left, right, top and bottom margins are DS
Variables V_MARGINL, V_MARGINR, V_M are stored in RAM 18B in P board 16.
Transferred as ARGINT and V_MARGINB respectively.

In the case of the C_StepSet subroutine, the command packet includes a header, an X step (X Step), and a Y step (Y Step) as shown in FIG. In this case, the values of the X step and the Y step are stored in the RAM 18B by the variables V_STEPX and V_STE.
Each is transferred as PY.

In the case of the C_PositionSet subroutine, the command packet is composed of a header and an X position (X POSITIO
N) and Y position (Y POSITION). In this case, the values of the X position and the Y position are stored in the RAM 18B in the variables V_POSIX and V_POS.
Transferred as IY.

In the case of the C_CellWidthSet subroutine, a command packet is composed of a header, a cell X (CELL X) and a cell Y (CELL Y), and the values of the cells X and Y are stored in the RAM 18B in the variable V_
Transferred as CELLX, V_CELLY.

In the case of the C_RotateSet subroutine, as shown in FIG. 21, a command packet is composed of a header and rotate (ROTATE). In this case, the rotation value is transferred to the RAM 18B of the DSP board 16 as a variable V_ROTATE.

Since the character size is set by the variables V_CELL X and V_CELLY, and the rotation angle of the character is set by the variable V_ROTATE, the determinant for rotating the character is generated as follows.

In the case of the C_SlantSet subroutine, a command packet is composed of a header and a slant (SLANT) as shown in FIG. 22, and the slant value is transferred to the RAM 18B as a variable V_SLANT.

Since the character size is represented by variables V_CELLX and V_CELLY, and the inclination angle of the character is represented by variable V_SLANT, the determinant for inclining the character is generated as follows.

In the case of the C_SplineSet subroutine, the command packet consists of a header and a spline (SPLIN) as shown in FIG.
E), and the value of the spline is stored in the RAM 18B in the variable V_S
Transferred as PLINE. Thus, an initial value for spline conversion is obtained.

In the case of the C_TextureSet subroutine, the command packet is composed of a header and a text (Text) as shown in FIG.
ure). In this case, the value of the texture is R
Transferred to AM18B as variable V_TEXTURE.

In the case of the C_CMTSet subroutine, the command packet is composed of a header, SCMTA, SCMTB, SCMTD and SMTD as shown in FIG.
It is configured by CMTE. These values are divided by a value 256 to convert from fixed point representation to floating point representation and then transferred to RAM 18B as variables V_CMTA, V_CMTB, V_CMTD and V_CMTE, respectively.

These variables V_CMTA, V_CMTB, V_CMTD, V_CMTE are:
Used for CMT operation.

The input data (x, y) of this matrix is (0,
255), (255,0) and (255,255), the smallest of the output data (XY) is obtained, and when the value is negative, the values X and Y obtained by inverting the sign of the value are obtained. V_CMTC
And V_CMTF, and are transferred to the RAM 18B. This process is 26th
As shown in the figure, the coordinates converted when the character is rotated, tilted, or translated do not have a negative value.

In the C_LineFeed subroutine, as shown in FIG. 27, the value of the variable V_POSIX is set to the variable V_MARGINL (left margin) (S41), and the value of the variable V_STEPY is added to the variable V_POSIY (S42). Here, V_POSIY + = V_STEPY represents the following equation (the same applies hereinafter).

V_POSIY = V_POSIY + V_STEPY Next, the variable V_POSIY and the variable V_MARGINB (lower margin) are compared (S43), and when the former is greater than the latter, C_For
The mFeed subroutine is executed (S44).

In the C_FormFeed subroutine, as shown in FIG. 28, after the values of the variables V_RARGINL (left margin) and V_MARGINT (upper margin) are set in the variables V_POSIX and V_POSIY, respectively (S51), the bank of the bitmap memory 24 is Switching is performed, and the base address (see FIG. 111) is changed (V_OFFSET indicates the offset of the bank address of the bitmap memory) (S52). Next, the New Page mail is C
The reply is sent to PU4, and the reply is received (S53).

In the C_PlotFont subroutine, as shown in FIG. 29, the sorting means (CADM) 22 is reset and an initial value is set (S61). When the variable V_MODE is 0 (S6
2) The font vector data of the RAM 18A (RAM0) of the DSP board 16 is read out, and the x- and y-coordinates of 256 × 256 are calculated by the following equations to obtain variables V_CELLX and V_CELLY, respectively.
(S63).

WR4 = (xx (V_CELLX)) / 256 WR3 = (yx (V_CELLY)) / 256 Here, WR3 and WR4 are working registers inside the DSP board 16.

In the case of Plot Font, the command packet is configured as shown in FIG. The next upper 8 bits of the header are H00
In the case of, a data string consisting of the next 4 bits consisting of the x coordinate and the lower 4 bits consisting of the y coordinate is arranged. If the next upper 8 bits of the header are H01, the end of the polygon is reached. It is said.

Then, the type of the font data read from the RAM 18A is determined next, and when it indicates the end of the polygon or the end of the data, the process proceeds to step 78 (S78) (S64, S6).
5) When the polygon and the data are not finished, the font vector data (x, y) of the RAM 18A is read, and the results of the following arithmetic expressions are set in the working registers WR1 and WR2, respectively (S66).

WR1 = (y × (V_CELLY)) / 256 WR2 = (xx × (V_CELLX)) / 256 When the values WR1 and WR3 are equal (S67), that is, when the vector is horizontal in the horizontal direction, the working register WR1, The value of WR2 is stored (S68). After the values of the working registers WR1 and WR2 are set in the working registers WR3 and WR4, the process returns to step 64 (S69).

In step 67, if the values of the working registers WR1 and WR3 are not equal (if the vector is not horizontal in the horizontal direction), the logical sum (OR) of the value of H0 × H1000 and the value of the working register WR4 is calculated. As a result, the value of H1 is set in the upper 4 bits and the value of WR4 is set in the lower 12 bits, expressed in hexadecimal. The format at this time is as shown in FIG. Similarly, the value of H0 × H6000 and the working register WR2
Is calculated, and these values are transferred to the contour coordinate generation means (OCG) 21 together with the values of the working registers WR1 and WR3 (S70). Next, when the font data indicates the end of the polygon (S71), the data stored in the RAM 18B is transferred to the outline coordinate generation means 21 (S77), and the process proceeds to step 63.

If the font data does not indicate the end of the polygon and the data (S72), the next operation value is set in the working register WR0, and the value is transferred to the outline coordinate generation means 21 (S73, S74).

WR0 = (xx × (V_CELLX)) / 256 Next, similarly, the following calculation is performed, and the value is transferred to the contour coordinate generation means 21. Then, the process returns to step 71 (S75, S7).
6).

WR0 = (y × (V_CELLY)) / 256 When the font data indicates the end of the data (S72), the value of the variable V_POSIX is transferred to the drawing means 23 (S8).
1) Further, the value obtained by adding the variable V_OFFSET to the variable V_POSIY is transferred to the drawing means 23 (S82). After the variable V_TEXTURE is similarly transferred to the drawing means 23 (S83), PositionTra
The ns subroutine is executed (S84).

When the font data indicates the end of the polygon or the data in step 64 or 65, the maximum value (Xmax) and the minimum value (Xmin) of the x coordinate stored in the RAM 18B are obtained (S78), and the point (Xminy ) To the point (Xmax y), the command and data are transferred to the contour coordinate generation means 21 (S79). If the font data has not been completed, the process returns to step 62, and if completed, the process proceeds to step 81.

If the variable V_MODE is not 0 in step 62, the following equation WR3 = (xx (V_CELLY)) / 256 WR4 = (xx (V_CELLX)) / 256 is obtained by the following equation: WR3 = xx (V_CMTD) + y × (V_CMTE) + (V_CMTF) The same processing as in step 63 and subsequent steps is executed except that WR4 = x × (V_CMTA) + y × (V_CMTB) + (V_CMTC).

In the case of the PositionTrans subroutine, as shown in FIG. 31, after the variable V_STEPX is added to the variable V_POSIX (S9
1) The variable V_POSIX is compared with the variable V_MARGINR (right margin) (S92). If the former value is equal to or greater than the latter value, the C_LineFeed subroutine is executed (S93).

FIG. 32 schematically shows the processing of each subroutine. As shown in the figure, on a bitmap (corresponding to the paper to be printed) on which margins are set on the left, right, top, and bottom, characters are sequentially shifted rightward by PositionTrans processing and when they reach the position corresponding to the right margin, C_LineFe
The processing of ed (line feed, carriage return) is executed. When the position corresponding to the bottom margin is reached, FormFeed (page break) processing is executed.

Next, the contour coordinate generation means (OCG) 21 will be described.
The basic functions of the contour coordinate generating means 21 are the following two.

1) From the vector coordinates input from the coordinate conversion means 15,
The coordinates of a line segment connecting the start point and the end point of the vector are calculated and generated.

2) From the calculated and generated coordinates, coordinates suitable for the drawing process (filling process) in the subsequent drawing means 23 are selected.

The above two processes are performed in parallel for high-speed processing.

As shown in FIG. 33, the contour coordinate generation means 21 for performing such processing is constituted by an input control unit 31, a coordinate calculation unit 32, a linear coordinate selection unit 33, a corner coordinate selection unit 34, and an output control 35. .

The input control unit 31 has an input FIFO (First_In) incorporating the vector coordinates input from the coordinate conversion means (DSP) 15.
First_Out). The coordinate calculation unit 32 reads the coordinates of the start point and the end point from the input FIFO, and calculates and generates the coordinates of a line segment connecting the start point and the end point. For example, point A shown in FIG.
When the coordinates of the (start point) and the point B (end point) are read, the coordinates A _{1 of} the dots forming the line segment (straight line) connecting the points A and B
To determine by computation A _5. In the same manner, the coordinates of the line connecting point B and point C, point C and point D, and point D and point A are sequentially calculated. The linear coordinate selection unit 33 selects only necessary coordinates from the calculated linear coordinates. That is, line segments AB, BC, C connecting points A and B, B and C, C and D, and D and A, respectively,
In order to perform the process of filling the inside of a polygon constituted by D and DA, only two points, ie, the start point and the end point of the filling in the filling direction (for example, the x-axis direction) are required. Therefore, processing is performed so that only two points exist on the same y-axis.
Eg, point A ₂ and A ₃ as a point having the same y-coordinate values and the point D ₈
There so present only in A ₃ and more in this case the outside is selected. The result will be to fill the points between points D ₈ and the point A ₃ is later. Hereinafter, only necessary points are selected in the same manner from the point of forming a straight line.

The corner coordinate selection unit 34 selects necessary ones from the points constituting the corner. For example, in the embodiment of FIG.
There are four corners constituted by the points D to D. Of these, in the corner constituted by the point D, there is only one point having the same y-coordinate. The end point cannot be specified.
Therefore, in such a corner, the point D is selected as a drawing start point and also as an end point.

The output control unit 35 stores the coordinates on which the linear processing and the corner processing have been performed in the built-in output FIFO, and outputs the coordinates to the sorting unit 22 in the subsequent stage.

The five blocks from the input control unit 31 to the output control unit 35 operate in parallel for high-speed processing.

The coordinate calculation unit 32 is configured, for example, as shown in FIG.
It is controlled by a sequencer consisting of a PAL with a register as shown in the figure.

In FIG. 34, reference numeral 41 denotes an input FIFO,
The input vector coordinates are stored. 42 and 43 are FI
X coordinate (BUSX) and y coordinate (BUSY) read from FO41
Are stored in the register. 44 is a multiplexer (MUX) for selectively outputting a signal from ABUS or BBUS, 45 is an ALU for performing arithmetic processing on the output of the multiplexer 44, and 46 is a circuit for outputting the 2's complement of the output of the ALU 45. The output of the circuit 46 is supplied to registers 47 to 51 and up / down counters 52 and 53. The counter (CAPX) 52 is loaded with the x-coordinate (start x-coordinate) of the start point of the straight line among the input coordinates to the FIFO 41, and sequentially generates x-coordinates forming a line segment from the coordinates. The counter (CAPY) 53 is loaded with the y-coordinate (start y-coordinate) of the start point of the straight line, and then sequentially generates y-coordinates forming a line segment. Register (DELX) 48 is the register (BU
SX) 42 and the absolute value (| BUSX-CAPX |) of the difference between the stored value of the counter (CAPX) 52 (start x coordinate). This absolute value defines the amount of movement of the straight line in the x-axis direction.
A flag SX indicating the sign of (BUSX-CAPX) defines the direction of the straight line with respect to the x-axis, and a flag ZX indicating whether the value of (BUSX-CAPX) is zero or not indicates whether the straight line is parallel to the y-axis. Defines whether or not. Register (DELY) 49 and Register (DELY
_Y) 50 stores the absolute value (| BUSY-CAPY |) of the difference between the register (BUSY) 43 and the counter (CAPY) 53 (start y coordinate). This absolute value defines the amount of movement of the straight line in the y-axis direction.
The (BUSY-CAPY) sign flag SY defines the direction of the straight line with respect to the y-axis, and the zero flag ZY defines the straight line parallel to the x-axis. The register (DDXY) 47 is an absolute value of the difference between the stored value of the register (DELX) 48 and the register (DELY) 49 (| DELX-DELY
|) Is memorized. The sign flag SC of (DELX-DELY) defines whether the inclination of the straight line with respect to the x-axis is 45 degrees or more,
The flag ZC indicating whether (DELX-DELY) is zero defines whether the inclination is 45 degrees or not. The register (D_DELX) 51 stores the stored value of the register (DELX) 48 and Bresen
The error term e of the ham algorithm is stored.

Reference numerals 54, 55, and 56 denote shifters for shifting the data one bit to the left (upper) and doubling the data. 57 and 58 are counters (CAPX) 5
2. A buffer for setting the timing for outputting the value of the counter (CAPY) 53 to the B bus. 59 is a register (DEL
A multiplexer for selecting the output of the X) 48 and the register (DELY) 49, and a multiplexer 60 for selectively outputting the count enable signal CNTENX of the counter (CAPX) 52 and the count enable signal CNTENY of the counter (CAPY) 53. 61 is a down counter, which is a register (DELX) as an initial value
The value stored in the register 48 or the register (DELY) 49 is input, and the value is down-counted to generate a CNTOVR signal indicating the end of data generation for one line segment. 62,
Reference numeral 63 denotes a six-stage shift register for storing the status of a line segment. The two line segments are grouped together, the newly input line segment is referred to as OUT (output), and the old line segment is referred to as INP (input).
Signals OUT_SC, OUT_SY, OUT_ indicating the status of each line
SX, INP_SC, INP_SY, INP_SX or OUT_ZC, OUT_ZY, OUT_
Outputs ZX, INP_ZC, INP_ZY, INP_ZX, respectively.

In FIG. 35, a state counter 71 outputs a predetermined 6-bit code signal corresponding to another input signal every time the system clock SCLK is input. 72 has 4 registers with 9-bit input and 8-bit output
The output is latched by MEMCLK. The lower 6 bits of the 9-bit input are supplied with the output of the state counter 71, and the upper 3 bits are MODE (MODE0 to M0).
A signal representing ODE3) is provided. These four MODEs
Is generated by decoding the upper 4 bits of the command of the 16 bits transmitted from the coordinate converter 15 shown in FIG. Table 2 shows these correspondences.

The PROM 72 outputs various control signals shown in FIG. 35 according to the data input from the state counter 71. This control signal is supplied to each register, counter and the like in FIG. 34 to control this operation. Table 3 summarizes the control signals used in the block diagram of FIG.

FIG. 36 is a flowchart showing the coordinate calculation process in the block diagram of FIG. The data input to the FIFO 41 is first stored in the register (BUSX) 42 (S
1). Then, it is determined from the upper 4 bits which MODE shown in Table 2 is set (S2). MODE0 (1st
When the data is the (third data), an initial value setting process is executed (S3). That is, the value of the register (BUSX) 42 is sequentially stored in the counter (CAPX) 52, the value input to the FIFO 41 is stored in the register (BUSY) 43, and the value of the register (BUSY) 43 is sequentially stored in the counter (CAPY) 53. Will be transferred. As a result, an initial value (start coordinates of the polygon) is set in the counters (CAPX) 52 and (CAPY) 53.

If it is MODE 1 or 2 (the second and subsequent data of the polygon), step S6 and subsequent steps for constant calculation described later are executed.

When the mode is MODE3 (command or data to the sorting means 22), the value of the register (BUSX) 42 is set to the counter (CAPY) 53
The coordinate transfer clock TRANS is turned on and off (S5). Thereby, the command or data is transferred to the linear coordinate selection unit 33.

In the constant calculation step, first register (BUSX)
The absolute value of the difference between the value of 42 and the value of the counter (CAPX) 52 is calculated and stored in the register (DELX) 48 (S6). Then FIFO
After the value of 41 is stored in the register (BUSY) 43 (S7), the absolute value of the difference between the value of the register (BUSY) 43 and the value of the counter (CAPY) 53 is stored in the register (DELY) 49 (S8). Further, it is determined whether or not the value of the register (DELY) 49 is 0, and when it is 0 (when it is a straight line parallel to the x-axis), a special processing step is executed (S9). If it is not 0, after the absolute value of the difference between the value of the register (DELX) 48 and the value of the register (DELY) 49 is stored in the register (DDXY) 47, the process proceeds to the processing step of the Bresenham algorithm (S13 and subsequent steps) (S
9, S10).

Thus, in steps S6 to S10, constants required for Bresenham's algorithm for generating linear coordinates are calculated, and the status of the line is generated.
However, the constants of Bresenham's algorithm are converted as follows.

DELX-2DDXY = DELY-2 (DELX-DELY) = 2DELY-DELX (D_DELX) -2DDXY = (D_DELX) -2 (DELX-DELY) = (D_DELX) +2 (DELY-DELX) When the straight line is parallel to the x-axis In the special processing step, the value of the counter (CAPX) 52 is stored in the register (D_DELX) 51.
The value of the register (BUSX) 42 is stored in the counter (CAPX) 52,
Each is stored. The sign of the difference between the values of the register (D_DELX) 51 and the register (BUSX) 42 is obtained (S11). Next, the clock TRANS is turned on and off, and the process returns to step S1 (S12). In this way, only the coordinates of the end point of the straight line are transferred without using the Bresenham algorithm.

In the processing steps of the Bresenham algorithm, first, the sign of the difference between the values of the registers (DELX) 48 and (DELY) 49 is determined (S13). When this sign is negative or 0 (when the inclination of the straight line with respect to the x-axis is 45 degrees or more), a value obtained by subtracting a value obtained by doubling the value of the register (DDXY) 47 from the value of the register (DELY) 49 is the register ( D_DELX) 51 (S1
4) Also, the value of the register (DELY) 49 is decremented by 1 (S15). And the value of the register (DELY) 49 is 0
Is determined (S16). If the value is 0, the clock TRANS is turned on and off, and the process returns to step S1 (S17). When the value of the register (DELY) 49 is not 0, the sign of the register (D_DELX) 51 is determined (S18). When this value is positive or 0, the difference between the value of the register (D_DELX) 51 and the value obtained by doubling the value of the register (DDXY) 47 is the value of the register (D_DEX).
LX) 51 and the counter (CAPX) 52
Is incremented or decremented by 1 (S19). When the value of the register (D_DELX) 51 is negative, the value of the register (D_DELX) 51 and twice the value of the register (DELX) 48 are added and stored in the register (D_DELX) 51 (S20). Regardless of the value of the register (D_DELX) 51, after those processes, the value of the counter (CAPY) 53 is incremented or decremented by 1 and the step
The process returns to S15 (S21).

In step S13, when the difference between the register (DELX) 48 and the register (DELY) 49 is positive (the inclination of the straight line with respect to the x-axis is
When it is smaller than 45 degrees), a value obtained by subtracting a value obtained by doubling the value of the register (DDXY) 47 from the value of the register (DELX) 48 is stored in the register (D_DELX) 51 (S22), and the value of the register (DELX) is also obtained.
X) The value of 48 is decremented by 1 (S23). Then, it is determined whether or not the value of the register (DELX) 48 is 0 (S24). When the value is 0, the clock TRANS is turned on and off, and the process returns to step 1 (S25). Register (DEL
When the value of (X) 48 is not 0, the value of the register (D_DELX) 51 is determined (S26). When this value is positive or 0, the difference between the value of the register (D_DELX) 51 and the value obtained by doubling the value of the register (DDXY) 47 is stored in the register (D_DELX) 51, and the counter (CAPY) 53 depending on the condition. Is incremented or decremented by 1 (S27). Register (D_DEL
When the value of (X) 51 is negative, the value of register (D_DELX) 51 and twice the value of register (DELY) 49 are added and stored in register (D_DELX) 51 (S28). Register (D_DEL
X) after processing them in any case,
The value of the counter (CAPX) 52 is incremented or decremented by 1, and the process returns to step S23 (S29).

The operation of the coordinate calculation unit 32 shown in FIG.
Can be described by a state transition diagram expressed as a flow of a state in which a transition is made every time one is generated. FIG. 37 shows the overall flow of the state transition. When the clock SCLK is generated in the initial state (state ST0), the state shifts to a wait (WAIT) state (ST02). In this state, the control signal IEMP is monitored and the FIFO
If data of 41 is not empty (signal IEMP is logic 0) (! IEM
The state moves to the next MODE set state (ST1). Here, "!" Means NOT. In the MODE set state, the data input from the FIFO 41 is latched in the register (BUSX) 42, and the mode of the data (second
Table) is determined.

MODE0 (first polygon data)
After the initial value setting state (ST2 to ST5) is executed,
Move to the FIFO read state (ST01). In the FIFO read state, data stored in the FIFO 41 is read. After the FIFO read state, the operation returns to the initial state (ST0) again.

In the case of MODE1 or MODE2 (when the data is the second and subsequent polygons), the constant calculation state (ST2 to ST7)
Is executed, and DELX (Δx), DELY (Δy) and DDXY (Δ
After the calculation of (x−Δy) is performed, if the straight line is not parallel to the x axis corresponding to the status of the straight line, the state (ST8 to ST17) of the coordinate calculation by the Bresenham algorithm is as follows:
If parallel to the x-axis, the state of special processing (ST20 to ST20)
ST29) are respectively executed. After these processes, the process returns to the initial state (ST0) via the FIFO read state (ST01).

On the other hand, in the case of MODE3 (when the command or data is output to the sorting means 22), the state of the command processing (ST
2 to ST6), the state of the FIFO read (ST
01) to the initial state (ST0).

FIG. 38 shows the state of the initial value setting in more detail. First, the register (BUSX) 42 and the FIFO 41 are read (ST2), and the counter (CAPX) 52 and the register (BUSY) 4
Latched to 3 (ST3). If the FIFO 41 is empty (the signal IEMP is on), the process waits. If the FIFO41 is not empty (! IEMP
If so, the register (BUSY) 43 is read (ST4),
The data is latched by the counter (CAPY) 53 (ST
Five).

FIG. 39 shows a timing chart of the initial value setting. Each time the clock SCLK is input, the state becomes ST0, S
It changes sequentially from T02, ST1, ST2. Here is the clock SCL
There is a delay between the rising edge of K and the state transition because the clock SCLK
This is because there is a slight delay between the input of the PROM 72 and the output of the predetermined control signal from the PROM 72.

After the setting of MODE (MODE0 in the embodiment) corresponding to the control signal MODEST in the state ST1,
In state ST2, the data in register (BUSX) 42 is ABU
S, output to AMBUS via multiplexer 44. Further, since this data is output to the FBUS by the ALU 45, the data can be latched by the counter (CAPX) 52 in the state ST3. Also, in state ST2, data D of FIFO41
Since x ₀ is read out, in the next state ST3 FIF
The next data Dy ₀ is output to ORD, and this is
Y) Latched at 43. When FIFO41 is not empty (signal IEM
When P is logic 1, the register (BU) in state ST4
SY) 43 is read out to AMBUS and FBUS, and this is latched by the counter (CAPY) 53 in state ST5.

Next, before describing the state of constant calculation and coordinate calculation for executing the processing of Bresenham's algorithm,
The principle of Bresenham's algorithm will be described with reference to the drawings. As shown in FIG. 40, when a straight line connecting two points of the start point A and the end point B is represented as a set of points (dots), a point on the straight line located at a position other than an integral multiple of the coordinate unit is a coordinate unit. Will be approximated at a point at an integer multiple of. To perform this approximation, one of the x and y coordinates of a predetermined point on the straight line is left as it is, and the other is set to a coordinate value that is an integral multiple of the nearest coordinate unit. That is, when the straight line inclination angle is 45 ° or less with respect to the x-axis as shown in Figure 40 (a) (i.e. the starting point A of the x-coordinate of (x _1, y ₁₎ and the end point B (x _2, y ₂₎ When the difference (x ₂ −x ₁ ) is Δx (sign thereof is SX) and the difference (y ₂ −y ₁ ) of y coordinate is Δy (sign thereof is SY),
(| Δx | - | Δy | ) when the sign SC is SC ≧ 0 in), for example, linear to approximate the A ₁ point on AB, the point A ₁ and the same x-coordinate of the two points A ₂ and A ₃ the idea, the error between the point a ₁ these points
When e ₂ and e ₃ are set, the point with the smaller error (in this case, e ₂ <
selecting a point A ₂₎ since it is e _3. Since the error e is 1 or less (unit), a point whose value is 1/2 or less is selected as an approximate point. Similarly, the straight line AB is point A,
A ₂ , A ₄ , A ₅ ... A ₁₀ , and B are approximated.

When the inclination of the straight line is larger than 45 degrees as shown in FIG. 40 (b), the coordinate value in the y-axis direction is kept as it is, and the coordinate in the x-axis direction is such that the error e is less than 1/2. Coordinates.

For example, in the case of FIG. 40 (a), the coordinates of such an approximate point can be obtained by performing an operation shown by the following program.

e: 2DELY-DELX for i: 1 to DELX do begin Plot (x, y); if e> 0 then begin y: y + 1; e: e + 2 (DELY-DELX) end else e: e + 2 * DELY x: = x + 1; end; The coordinate calculation unit 32 in FIG. 34 executes this calculation by hardware, and FIGS. 41 to 43 illustrate the operation thereof with reference to a state transition diagram.

FIG. 41 shows a state transition diagram of the constant settlement state. In this constant calculation state, the difference between the value of the register (BUSX) 42 and the value of the counter (CAPX) 52 (BUSX
−CAPX) is calculated by the ALU 45, and the data in the FIFO 41 is read (ST2). In the next state, the operation result is latched in the register (DELX) 48 and the read data is latched in the register (BUSY) 43, and the shift enable signal FLGCLK is turned on. And 63 (ST3). If the FIFO 41 is not empty, the process proceeds to the next state, and the difference (BUSY-CAPY) between the value of the register (BUSY) 43 and the value of the counter (CAPY) 53 is calculated by the ALU 45 (ST4).
This operation result is stored in the register (DELY) in the next state.
It is latched by 49 and the register (DELY_Y) 50 (ST5). In this state, the clock FLGCLK is turned on again,
Outputs SIGN and ZERO of ALU 45 are latched in shift registers 62 and 63, respectively. If the signal ZERO is logic 1 (the straight line is parallel to the x-axis), the special processing substates (ST20 to ST20)
261).

If the straight line is not parallel to the x-axis then register (DELX) 48
Is stored in the register (D_DELX) 51 and the difference between the register (D_DELX) 51 and the register (DELY) 49 ((D_DELX)
DELX) -DELY) is calculated by ALU45 (ST51, ST51).
6). In the next state, the operation result is stored in the register (DDX
Y) While being latched by 47, the clock FLGCLK is turned on, and the outputs SIGN and ZERO of the ALU 45 are shifted to the shift registers 62 and 63.
(ST7). In this state, when output FIFOs 97 and 98 (FIG. 74), which will be described later, are full (when control signal OFUL is at logic 1), the process shifts to the coordinate calculation state if not.

42 and 43 are state transition diagrams of the coordinate calculation state. FIG. 42 shows that the output flag SIGN of the ALU 45 is logic 0 (the inclination of the straight line with respect to the x-axis is less than 45 degrees) and the output FI
If FO is not full, and FIG.
(When the inclination of the straight line is 45 degrees or more) and the output FIFO is not full, the process shifts from the state ST7 in FIG. 41.

In FIG. 42, first, the difference between the value of the register (D_DELX) 51 and the value obtained by doubling the value of the register (DDXY) 47 ((D_DELX)
−2DDXY) is calculated by the ALU 45, and the control signal STRT indicating the start of coordinate calculation is turned on (ST8).
In the next state, the operation result of ALU45 is stored in the register (D_D
ELX) 51, the clock TRANS is turned on, and the calculation coordinates are described in a pipeline register PIP1X8 described later.
2. Transferred to PIP1Y84 (FIG. 54) (ST91). From this state, when the flag SIGN is logic 1 and CNTOVR and OFUL are logic 0, the state ST11 and the flag CNTOVR are logic 1
When the flag OFUL is logic 0, the state ST12, the flag SI
State when all of GN, CNTOVR and OFUL are logic 0
The process proceeds to ST10 and waits when none of them is found.

In state ST10, the difference between the value of register (D_DELX) 51 and twice the value of register (DDXY) 47 ((D_DELX) −2DDX
Y) is calculated and the clock TRANS is turned off. The count enable signals CNTENX and CNTENY of the counters (CAPX) 52 and (CAPY) 53 are turned on. After performing these processes, the process returns from the state ST10 to the state ST91 again.

In the state ST11, the value of the register (D_DELX) 51 and twice the value of the register (DELY) 49 are added by the ALU 45, and the signal CNTENX is turned on. In the next state, the added value is latched in the register (D_DELX) 51, and the clock TRANS is turned on (ST92). In this state, the flags SIGN and OFUL are logic 1 and the flag CNTOVR is logic 0
State ST11, the flags SIGN, OFUL, CNTOVR
When both are logical 0, state ST10
State when CNTOVR is logic 1 and flag OFUL is logic 0
Transition to ST12, and wait if none of them.

In state ST12, the clock TRANS is turned off,
After the clock TRANS is turned on in the next state ST13, the process returns to the state ST01.

In FIG. 43, first, the difference between the value of the register (DELY_Y) 50 and twice the value of the register (DDXY) 47 ((DELY_Y) −2DDX)
Y) is calculated by the ALU45, and the signal STRT is turned on (ST
14). In the next state, register (D_DELX)
The operation result of the ALU 45 is latched at 51, and the clock TRANS is turned on (ST150). If the flag SIGN output by the ALU 45 is logic 0, the state ST16 is set to logic 1
If so, the process proceeds to state ST17.

In state ST16, the difference between the value of register (D_DELX) 51 and twice the value of register (DDXY) 47 ((D_DELX) -2DDX
Y) is calculated by the ALU 45, and the count enable signals CNTENX and CNTENY are turned on. In the next state, the operation result is latched by the register (D_DELX) 51, and the clock TRANS is turned on (ST151). In this state, the flag SIGN is at logic 1 and the flag CNTOVR and
When OFUL is logic 0, state ST17, flags SIGN, OFUL,
State ST16, flag when any of CNTOVR is logic 0
State when CNTOVR is logic 1 and flag OFUL is logic 0
The process proceeds to ST12, and waits at other times.

In the state ST17, the value of the register (D_DELX) 51 is added to twice the value of the register (DELX) 48 ((D_DELX)
X) + 2DELX), and the signal CNTENY is turned on. In the next state, the operation result in the previous state is latched in the register (D_DELX) 51 and the clock is output.
TRANS is turned on (ST152). In this state, when the flag SIGN is at logic 1 and the flags CNTOVR and OFUL are at logic 0, the state ST17 is reached. When all of the flags SIGN, OFUL, CNTOVR are at logic 0, the state ST16 is reached. When the value is logic 0, the state shifts to the state ST12, and otherwise stands by.

The clock TRANS is turned off in the state ST12, and turned on in the next state ST13. Thereafter, the flow shifts to the state ST01 in FIG.

FIG. 44 shows a timing chart of constant calculation and coordinate calculation in the case of MODE2. Data of register (BUSX) 42 is ABUS in state ST2 for constant calculation.
And read out to the AMBUS by the multiplexer 44. Similarly, the data of register (CAPX) 52 is BBUS
And read out from the multiplexer 44 to BMBUS. Then, the operation of (BUSX-CAPX) is performed by the ALU 45, and the result is output to the FBUS. The next data D in FIFORD the data Dx ₁ is read from FIFO41
y ₁ is output. As a result, FBUS and F
IFORD data is stored in register (DELX) 48 and register (BUS
Y) Each is latched at 43. In addition, ALU45 calculates (BUSX-CA
PX) SIGN and ZE of the operation value faster than the operation result of PX)
Output RO. As a result, clock F in state ST3
When LGCLK is turned on, the data of flags SIGN and ZERO
The symbols SX and ZX of ELX (Δx = BUSX−CAPX) are latched in the shift registers 62 and 63, respectively.

In state ST4, registers (BUS
Y) 43 and counter (CAPY) 53 data are output respectively,
The difference between the two (BUSY-CAPY) is output from the ALU 45 to the BUS. In state ST5, FBUS data is stored in the register (DEL
Y) 49 and (DELY-Y) 50 are latched and the clock FLG
Flags SIGN and ZERO output by ALU45 when CLK is turned on,
The symbols SY and ZY of DELY (Δy = BUSY−CAPY) are latched in the shift registers 62 and 63, respectively.

In state ST51, the data in the register (DELX) 48 is
The signal is output to the AMBUS via the ABUS and the multiplexer 44, is passed through the ALU 45, is output to the FBUS, and is latched by the register (D_DELX) 51. AM in state 6
The data of the registers (D_DELX) 51 and (DELY) 49 are output to BUS and BMBUS, and operated by ALU45 ((D_DELX)-DELY)
Is executed, and the result is output to FBUS. State ST
At 7, the FBUS data is latched in the register (DDXY) 47. Further, the flags SIGN and ZERO output by the ALU 45 at that time by the clock FLGCLK are latched in the shift registers 62 and 63 as signs SC and ZC of DDXY (Δx−Δy), respectively.

After the constant calculation is performed in this manner, the coordinate calculation is performed next (the embodiment corresponds to the state shown in FIG. 42). In the state ST8, the data of the register (D_DELX) 51 and the data of the shifter 54 which is twice the value of the register (DDXY) 47 are output to the AMBUS and the BMBUS, respectively.
Calculates the difference between the two and outputs the result to FBUS. This output is latched by the register (D_DELX) 51 in the state ST91. The signal STRT is turned on in the state ST8, and the clock TRANS is turned on in the state ST91.

In state ST10, the data of the shift register (D_DELX) 51 and the data of the shifter 54 (2DDX) are stored in AMBUS and BMBUS.
Y) is output, and the difference between the two is calculated by the ALU 45 and output to the FBUS. At this time, the count enable signals CNTENX and CNTENY are turned on again. Then state again
After the process of 91 is performed, the process proceeds to the state ST11. Register (D_DELX) in AMBUS and BMBUS in state ST11
The data of 51 and the data of the shifter 56 which is twice the value of the register (DELY) 49 are output, and the sum of both is
Output to S. This FBUS data is stored in the next state ST92.
Is latched by the register (D_DELX) 51 at In the state ST11, the signal CNTENX is turned on, and the state ST92
In, the clock TRANS is turned on.

After the predetermined state is repeated, the state ST
At 12 and ST13, the clock TRANS is turned off and on again. Thereby, the coordinates generated by the calculation are transferred to the next stage.

FIG. 45 is a state transition diagram of the special processing state. No.
From state ST5 in FIG. 41, this special processing is executed when the flag ZERO is at logic 1; when the flag INP_ZY is at logic 0 (when the input line segment is not parallel to the x-axis), (When the input line segment is parallel to the x-axis), the state shifts to the state ST26.

In the state ST20, the value of the counter (CAPX) 52 is set in the register (D_DELX) 51. In the next state, data is read from the register (BUSX) 42, and the clock FLGCLK is turned on for timing adjustment (ST21). ).

In state ST26, the difference between the data in the register (D_DELX) 51 and the data in the register (BUSX) 42 is calculated, and the clock FLGCLK is turned on in the next state (ST26).
1). That is, for later corner processing, D
IF and SAM codes are required. After the state ST261, the mobile terminal shifts to the state ST21.

In the state following state ST21, the counter (CAPX) 52
The data of the register (BUSX) 42 is latched, the flag STRT is turned on, and the control signal DF / S
M is set and the flag SIGN output by ALU45 is DIF / SAM
(ST22). After the clock TRANS is turned on (ST23), off (ST24), and on (ST25),
Move to the state ST01 in FIG.

FIG. 46 is a timing chart of special processing when the output line segment is parallel to the x-axis but the input line segment is not parallel to the x-axis (ZERO &! INP_ZY). In the state ST20, the data of the counter (CAPX) 52 is transmitted from the multiplexer 44 to the AMBUS.
Output from the ALU45 to the FBUS, register (D_DEL
X) Latched at 51. In state ST21, the data of the register (BUSX) 42 is read to AMBUS and further to FBUS. Then, the clock FLGCLK is turned on for timing adjustment. In state ST22, the register (BU
SX) 42 is latched by the counter (CAPX) 52. Further, the flag STRT is turned on, and the control signal DF / SM is set.

FIG. 47 is a timing chart of the special processing when the input line segment is parallel to the x-axis together with the output line segment (ZERO & INP_ZY). In this case, in the state ST26, the data of the register (D_DELX) 51 and the data of the register (BUSX) 42 are read to AMBUS and BMBUS, respectively, and the difference is calculated by the ALU 45 and output to the FBUS. In state ST261, the clock FLGCLK is turned on, and the flags SIGN and ZERO of the ALU 45 are latched in the shift registers 62 and 63.

FIG. 48 is a state transition diagram of a command transfer process executed when MODE is 3 in state ST1 of FIG. In the state ST2, the data of the register (BUSX) 42 is read, and in the state ST3, the data is latched by the counter (CAPY) 53, and the flag STRT is turned on. Further, after the signal TRANS is turned on, off, and turned on in the states ST4 to ST6, the process returns to the state ST01 in FIG.

FIG. 49 is a timing chart of the command transfer processing. In state ST2, the data in the register (BUSX) 42 is read out to AMBUS and FBUS, and latched in the counter (CAPY) 53 in state ST3. At this time, the flag ST
RT is turned on. In states ST4 to ST6, the signal TRANS
Are turned on, off, and on, and data is transferred.

FIG. 50 shows a delay state of each signal in FIGS. 34 and 35. The state counter 71 generates an output to the PROM 72 25 ns after the clock SCLK is input, and the PROM 72
Outputs a predetermined control signal 37 ns after a signal is input from the state counter 71. Registers 42, 43,
47 to 51 output signals to ABUS and BBUS 15 ns after the control signal is input from PROM 72,
44 is the AMBU 15 ns after the signal is input from each register
Outputs signals to S and BMBUS. The ALU 45 outputs data to CBUS 20 ns after data is input from AMBUS and BMBUS, and outputs the flags SIGN and ZERO 5 ns after that. The two's complement circuit 46 outputs data to the FBUS 15 ns after the flag is output from the ALU 45.

Clock MEMCLK inverts clock SCLK for an additional 25 ns
The PROM is delayed by its rising edge.
72 outputs are latched.

Next, the linear coordinate selection unit 33 will be described, but before that, the principle of linear coordinate selection will be described. The outer polygon is processed clockwise, and the inner polygon is processed counterclockwise.

As shown in FIG. 51, when Δx−Δy <0 (when SC = 1), the straight line has an angle of 45 degrees or more with respect to the x-axis. In other words, the angle is within 45 degrees with respect to the y-axis. In this case, since there are no more than two points constituting the straight line in the x-axis direction, all the points constituting the straight line are selected (LINE A
LL).

On the other hand, as shown in FIG. 52, when the angle of the straight line with respect to the x-axis is less than 45 degrees (Δx−Δy ≧ 0, that is, SC = 0) and the angle rises to the right, two or more points in the x-axis direction Exists. The starting point of the straight line (x _1, y _1), the end point (x _2,
The flag indicating the sign of (y ₂ ) and (x ₂ −x ₁ ) is set to SX (x ₂ −x ₁ ≧ 0).
SX = 1) when _{SX = 0, x 2 -x 1} <0 when, (y ₂ -y ₁₎
The flag indicating the sign of SY is set to SY (y = 0 when y _2- y ₁ ≥ 0, y ₂
Assuming that SY = 1 when −y ₁ <0, a straight line directed to the lower left (FIG. 52 (a)) is SX = 1, SY = 0, and a straight line directed to the upper right (FIG. 52 (b)) In this case, SX = 0 and SY = 1.
In these cases, the starting point (x ₁ , y ₁ ) and the coordinates generated by incrementing the coordinate y by 1 are selected (LINE NOW).

Further, as shown in FIG. 53, there are two or more points in the x-axis direction when the angle of the straight line with respect to the x-axis is less than 45 degrees (SC = 0) and the line goes down to the right. In the case of a straight line directed to the lower right (FIG. 53 (a)), SX = 0 and SY = 0, and in the case of a straight line directed to the upper left (FIG. 53 (b)), SX = 1 and SY = 1. In these cases, the end point (x ₂ , y ₂ ) and the coordinate immediately before the coordinate generated by incrementing the coordinate y by 1 are selected (LINE BFR). As described above, after incrementing the y coordinate by one, there is a case where the coordinate before the increment is selected, so that two stages (PIP1, PIP2) of pipeline registers described later are required.

In the case of FIG. 51, the flag SC is 1, and in the case of FIG. 52, the flag SC is set.
Since SC is 0 and the exclusive OR of the flags SX and SY is 1, and in the case of FIG. 53, the flag SC is 0 and the exclusive OR of the flags SX and SY is 0, each case is determined from these flags. can do.

Next, the function of the linear coordinate selection unit 33 will be described.

(1) Among the coordinates output from the coordinate calculation unit 32 (coordinates generated by the straight line interpolation processing), the coordinates of a line segment whose inclination with respect to the x-axis is less than 45 degrees are described above with reference to FIGS. The coordinates are selected according to the rules shown in the figure.

(2) Among the coordinates output from the coordinate calculation unit 32 (coordinates generated by the linear interpolation processing), all coordinates are selected for coordinates of a line segment whose inclination with respect to the x-axis is 45 degrees or more. .

(3) Select a start point and an end point of a line parallel to the x-axis output from the coordinate calculation unit 32, and a command and data for a CADM (sorting unit 22).

FIG. 54 is a block diagram of hardware of the linear coordinate selection unit 33 that executes the above functions. In the figure, reference numeral 81 denotes a sequencer composed of a PAL with a register, which corresponds to a pipeline register corresponding to various input signals shown on the left side of the figure.
The latch enable signal ENFLG of PIP2X83 and PIP2Y85 and the output FIFOs 97 and 98 of the next stage (corner coordinate selector 34) (Fig. 74)
A signal DATAEN for controlling the writing of data is generated. The pipeline registers PIP1X82 and PIP1Y84 are the counters (CA
PX) 52 and (CAPY) 53, and latches all data input from them. The pipeline registers PIP2X83 and PIP2Y85 are the pipeline registers of the previous stage.
Of the coordinates output from PIP1X82 and PIP1Y84, flag EN
Latch the coordinates when FLG is on.

FIG. 55 is a state transition diagram of the linear coordinate selection unit 33 in FIG. In the initial state ST00, the state shifts to the corresponding state when any of the following conditions is satisfied, and waits when none of the conditions is satisfied.

(1) Flags STRT and OUT_SC are logic 1 and flags CMD and OUT
LINE ALL state when _ZY is logic 0 (when the angle of the straight line to the x-axis is 45 or more).

(2) The flag STRT is logical 1, the flag OUT_SC, the flag OU
The LINE BFR state when the exclusive OR (＄) of T_SY and OUT_SX, the flag CMD, and the flag OUT_ZY are all logical 0 (when the angle on the straight x-axis is less than 45 degrees and the straight line descends to the right).

(3) When the exclusive OR of the flag STRT and the flags OUT_SY and OUT_SX is logic 1, and all of the flags OUT_SC, flag CMD, and flag OUT_ZY are logic 0 (the angle with respect to the linear x-axis is less than 45 degrees and When in a straight line) LINE NOW state.

(4) CMND / ZERO state when flags STRT and CMD are logic 1 or (#) flag STRT and OUT_ZY are logic 1 and flag CMD is logic 0 (when the straight line is parallel to the x-axis).

The flag CMD indicates whether or not the command or data is for a CADM.

In each of the states of LINE ALL, LINE BFR, LINE NOW, and CMND / ZERO, when the flag CNTOVR becomes logic 1, it returns to the initial state, and when it is logic 0, it stands by.

FIG. 56 shows the LINE ALL state. When the initial CNTENY is ON in the first state ST01, the state ST
02, flag CNTOVR is logic 1 and clock TRANS is processing 0
State (when the output FIFO is not FULL) state ST03
, Respectively. In state ST02, the signal DATAEN
And ENFLG are turned on, and the process returns to state ST01. In state ST03, after the signals DATAEN and ENFLG are turned on,
Return to the initial state ST00.

FIG. 57 shows a timing chart near the start point Co of the LINE ALL state. When the clock TRANS becomes logic 1 in the state ST01, the counter (CAPX) 52 and (CAPX)
Y) The x-coordinate and y-coordinate of the start point Co latched in 53 are transferred to the pipeline registers PIP1X82 and PIP1Y84, respectively. The signal CNTENY is a shift to state ST02 becomes a logic 1, the counter (CAPx) 52 and (Capy) of C ₁ 53 the following points x and y coordinates are respectively latched. When the signal TRANS becomes logic 1, the pipeline registers PIP1X82, PIP1Y
84 coordinates Cox, Coy are pipeline registers PIP2X83, PIP
Each is transferred to 2Y85 and the counter (CAPX) 52
And (CAPY) 53, the coordinates C ₁ x and C ₁ y correspond to the pipeline register PI
Transferred to P1X82 and PIP1Y84, respectively. Signals DATAEN, ENFL
When G becomes logic 1, the state returns to the state ST01 again, and the same operation is repeated, and the pipeline registers PIP1X82, PIP1Y
Coordinates C ₂ , C ₃ , and C ₄ are sequentially input to 84, and coordinates C ₁ , C ₂ , and C ₃ are sequentially transferred to pipeline registers PIP2X83 and PIP2Y85.

FIG. 58 represents a timing chart in the vicinity of the end point C _N of LINE ALL state. In this case also states ST01 and ST02
Are repeated, and the coordinates of the points C _N-2 and C _N-1 are sequentially transferred to the pipeline registers PIP182, 84, PIP283, and 85. Counter (CAPx) 52, the coordinate of the end point C _N is latched in (CAPY) 53, signal CNTOVR becomes logical 1. Signal CNTOVR In state ST02 is a shift to state ST03 becomes a logic 1, coordinates the pipeline register endpoint C _N PIP2X83, PIP
After the transfer to 2Y85, the flow shifts to the state ST00.

FIG. 59 shows how the pipeline registers PIP182, 84 and PIP283, 85 are sequentially latched by coordinates in the LINE ALL state. Now, coordinates a to k forming a straight line from the start point a to the end point k are counters (CA
PX) 52 and (CAPY) 53, these coordinates are sequentially transferred to the pipeline registers PIP 182 and 84 in synchronization with the rising edge of the signal TRANS, and these coordinates are all set to the signal ENFLG of logic 1 When the pipeline register PIP283, in synchronization with the rising edge of the signal TRANS,
It is further sequentially transferred to 85.

FIG. 60 shows the LINE BFR state. State
State ST12 when signal CNTENY is logic 1 in ST11
Then, when the signal CNTOVR is at logic 1, the state shifts to the state ST13, and otherwise stands by. In the state ST12, the signals DATAEN and ENFLG are turned on. When the signal CNTOVR is logic 0, the process returns to the state ST11, and when the signal CNTOVR is logic 1, the process shifts to the state ST13. In the state ST13, when the signal TRANS is logic 1 (when the output FIFO is full), the process waits, and when the signal TRANS is logic 0, the process shifts to the state ST14. In state ST14, the signal DATA
After EN and ENFLG are turned on, the process returns to state ST00.

FIG. 61 shows a timing chart near the start point Co in the LINE BFR state. When Following start Co coordinates thereof the following points C ₁ is latched in PIP182,84 in state ST11, the signal CNTENY becomes logic 1, state ST12
Move to In state ST12, the signals DATAEN and ENFLG
Together but are in a logic 1 on the rising edge of the signal TRANS, point C ₁ coordinates pipeline register PIP2
Latched at 83 and 85. Thereafter, the process returns to the state ST11. In this way, the points (C ₁ , C ₄ , C _7, ...) Immediately before the points (C ₂ , C ₅ , C _8, ...) Where the y coordinate is incremented by _one
Are transferred to the pipeline registers PIP283 and 85.

FIG. 62 represents a timing chart in the vicinity of the end point C _N in LINE BFR state. After the point y coordinate is incremented by 1 C _N-3, C just before the point of _{N-1 C N-4,} C N-2 are sequentially latched into pipeline register PIP283,85, end point C in the state ST11 The coordinate of _N is the counter (CA
P) When the signal CNTOVR is generated by 52 and 53 and becomes logic 1, the process proceeds to the state ST13. When the signal TRANS becomes logic 0 in the state ST13, the processing shifts to the state ST14 and the signal D
ATAEN's ENFLG is set to logic one, and the endpoint C _N is latched in the pipeline registers PIP283,85.

If the end point _CN itself is obtained by incrementing the y-coordinate by 1, as shown by the broken line in FIG.
At, the point CN _-1 is latched in the pipeline registers PIP283 and 85. Then, in the state ST12, the signal CNTOVR becomes logic 1, and the state shifts to the state ST13.

FIG. 63 shows the timing at which coordinates are sequentially latched in pipeline registers PIP182, 84, PIP283, 85 in the LINE BFR state. Coordinates a to j forming a straight line from the start point a to the end point j are counters (CAP) 5
When sequentially generated at 2, 53, these coordinates are
The data is sequentially transferred to the pipeline registers PIP182 and 84 in synchronization with the rising edge of RANS. Among these coordinates, the coordinates b, d, f, at the timing when the signal ENFLG becomes logic 1
Only h and j are transferred to the pipeline registers PIP283 and 85 in synchronization with the signal TRANS.

FIG. 64 is a state transition diagram relating to the signal ENFLG in the LINE NOW state. After transitioning to state FST2 via state FST1, the state changes to state FST3 when the signals CNTENY and TRANS are logic 0, and to state FST31 when the signal CNTENY is logic 1
, And wait at other times. State FS
After the signal ENFLG is turned on at T3, the state shifts to the state FST4. In the state FST31, after the signal ENFLG is turned on, the state shifts to the state FST6.

In the state FST4, when the signal CNTENY is logic 1, the processing shifts to the state FST6 via the state FST5, and otherwise stands by. In the state FST6, the state shifts to the state FST7 when the signals CNTENY and TRANS are logic 0, to the state FST8 when the signal CNTENY is logic 1, and waits in other cases.
In the state FST7, the state shifts to the state FST4 when the signal CNTOVR is logic 0, and to the state ST00 when the signal CNTOVR is logic 1. In state FST8, the signal returns to state FST6 after the signal ENFLG is turned on.

FIG. 65 is a state transition diagram relating to the signal DATAEN in the LINE NOW state. In the state ST1, the state transitions to the state ST2 when the signal CNTENY is at logic 1 and to the state ST00 when the signal CNTOVR is at logic 1, and waits otherwise.
In the state ST2, after the signal DATAEN is turned on, the process returns to the state ST1.

FIG. 66 is a timing chart near the start point Co in the LINE NOW state. The signal ENFLG will be described first. In the state FST1, the counter (CAPX) 52, (CA
After the start point Co latched in (PY) 53 is transferred to the pipeline registers PIP1X82 and PIP1Y84, the signal ENFLG is set to logic 1 in the state FST3. In the state FST3, at the rising edge of the signal TRANS, the latch coordinates Co of the pipeline registers PIP1X82 and PIP1Y84 are transferred to the pipeline registers PIP2X83 and PIP2Y85. In the state FST4, the signal CNTENY is set to logic 1. State
When the signal ENFLG is a logic 1 in FST7, latch coordinates C ₂ of the pipeline register PIP1X82, PIP1Y84 is transferred to the pipeline register PIP2X83, PIP2Y85. The point when the y coordinate is incremented by 1 in this way
C ₀ , C ₂ , C ₄ ... are pipeline registers PIP2X83, PIP
Transferred sequentially to 2Y85.

If the y coordinate continuously from the following points C ₁ of the start point C ₀ to the point C ₄ is incremented, the state FST6 and FST8 is repeated, as indicated by a broken line in the 66 figures, whenever made in the state FST8 The signal ENFLG is turned on, and these coordinates are sequentially transferred to the pipeline registers PIP2X83 and PIP2Y85.

Next, the signal DATAEN will be described. When the signal CNTENY changes to logic 1 in the state ST1, the process shifts to the state ST2, and the signal DATAEN is set to logic 1 in the state ST2.

67 Figure is a timing chart in the vicinity of the end point C _N of LINE the NOW state. First, the signal ENFLG will be described. When the signal CNTENY becomes logic 1 in the state FST4, and the signal ENFLG becomes logic 1 in the state FST7, the pipeline register PIP1X8 in the state FST7.
2.The latch coordinate C _{N-3 of} PIP1Y84 is the pipeline register PI.
Transferred to P2X83, PIP2Y85. Returning to the state FST4 again, when the signal CNTENY becomes logic 1, the logic becomes 1 in state FST7, and the pipeline registers PIP1X82, PIP1Y
84 latch coordinates C _N-1 are pipeline registers PIP2X83, PIP
Transferred to 2Y85.

When the end point C _N also coordinates incrementing the y-coordinate, as shown by the broken line in the 67 figures, the signal CNTENY the state FST6 transitions logic 1, and the state FST8.
After signal ENFLG is turned on in state FST8, state FST
When the state transits to the state FST7 via 6, the signal ENFLG is turned on again. This causes the end point _{CN to} be a pipeline register
From PIP1X82, PIP1Y84 to pipeline registers PIP2X83, P
Transferred to IP2Y85.

Next, the signal DATAEN will be described.
T2 is repeated, and the signal DATAEN is set to logic 1 in the state ST2.

Fig. 68 shows the start point a to end point j in the LINE NOW state.
This is a timing chart in which each point of a straight line constituted by the points a to j is sequentially transferred from the pipeline registers PIP1X82 and PIP1Y84 to the pipeline registers PIP2X83 and PIP2Y85.

All the coordinates a to j generated by the counters (CAPX) 52 and (CAPY) 53 are sequentially transferred to the pipeline registers PIP1X82 and PIP1Y84. However, since the signal ENFLG is generated corresponding to the point where the y coordinate is incremented, , Points a, c, e,
Only g and i are sequentially transferred from pipeline registers PIP1X82 and PIP1Y84 to pipeline registers PIP2X83 and PIP2Y85.

FIG. 69 is a state transition diagram of the CMND / ZERO state. When a transition is made to state ST22 via state ST21, a signal
If TRANS is logical 1, the process waits. If logical 0, the process proceeds to state ST23. In state ST23, signals ENFLG and D
After ATAEN is turned on, the process returns to state ST00.

FIG. 70 is a timing chart of the command CMND in the CMND / ZERO state. The command CMND latched by the counter (CAPY) 53 in the state ST00 is the state
In ST21, the data is transferred to the pipeline register PIP1Y84. When the signal ENFLG is set to logic 1 in the state ST23, the command CMND of the pipeline register PIP1Y84
Is transferred to the pipeline register PIP2Y85.

Fig. 71 shows that the input straight line is 45 degrees or more with respect to the x axis (SC = 0)
CMND / ZERO when the output straight line is parallel to the x-axis
It is a timing chart of ZERO coordinates (data of a line parallel to the x-axis) in a state. In state ST00, counters (CAPX) 52 and (CAPY) 53 are connected to the end point C _{N of the} output straight line.
Are latched, the coordinates are transferred to the pipeline registers PIP1X82 and PIP1Y84 in the state ST21. When the signals ENFLG and DATAEN are set to logic 1 in the state ST23, the coordinates of the pipeline registers PIP1X82 and PIP1Y84
C _N is transferred to the pipeline register PIP2X83, PIP2Y85.

Figure 72 shows that the input straight line is less than 45 degrees to the x-axis (SC = 1)
7 is a timing chart of ZERO coordinates in the CMND / ZERO state when the output straight line is parallel to the x-axis. Counter (CAPx) 52 in the state ST00, the coordinate of the end point C _N output line latched by the (Capy) 53, the state ST21
Are transferred to the pipeline registers PIP1X82 and PIP1Y84. At this time, pipeline registers PIP2X83 and PIP2Y
In 85, the coordinates of the point C _N 'immediately before the start point of the output line segment (end point of the input line segment) C _N ' are latched. When a signal ENFLG and DATAEN is set to a logic 1 in the state ST23, the coordinates C _N of the pipeline register PIP1X82, PIP1Y84 is transferred to the pipeline register PIP2X83, PIP2Y85.

Next, the corner coordinate selection unit 34 will be described. The corner coordinate selector 34 has the following functions.

(1) Linear coordinate selector 33 (pipeline register)
Among the coordinates transferred from the PIP2X83 and PIP2Y85), the coordinates of the line segment are subjected to corner selection processing according to a predetermined rule, and transferred to the output FIFO together with points other than the corners.

(2) Of the coordinates transferred from the linear coordinate selection unit 33 in the preceding stage, the start point and the end point of the line segment parallel to the x-axis are stored in the register (MIN9
1, latch to MAX92).

(3) Among the coordinates transferred from the linear coordinate selection section 33 in the preceding stage, the command and data for CADM (sort) are transferred to the output FIFO as they are.

As shown in FIG. 73 for the corner selection processing in the above (1), the corners are classified based on the status of the input straight line input to a predetermined point and the output straight line output therefrom, and the processing content is determined for each corner. Can be

The x coordinate of a valid point at the end point of the input straight line is defined as end X, and the x coordinate of a valid point at the start point of the output straight line is defined as start X. The selection and storage of these two points is the corner selection processing. Since the selected coordinates are points on the same y-axis (since the drawing scan direction is the x-axis direction), only the x-coordinate is used.

The corners include the normal corners (A1, B1, A4, B4), the beginning of special corners (A2, B2, A3, B3), and the middle of special corners (A2 ', B2', A3 ', B3'). Escape from special corners (A1 ', B1', A4 ', B4').

Table 4 summarizes the definitions of these corners.

In Table 4, corners A1 ', B1', A4 ', B4', A2 ', B2', A where the input straight line is parallel to the x-axis (INP_ZY = 1)
INP_SY at 3 'and B3' is the input straight line (parallel to the x axis)
Is the status of the straight line just before becoming parallel to the x-axis.

For example, at corner A1, the input straight line is not parallel to the x-axis (IN
P_ZY = 0) and downward (INP_SY = 0), and the output straight line is not parallel to the x-axis (OUT_ZY = 0) and downward (OUT_SY = 0).
In the corner A2, the input straight line is not parallel to the x axis and is directed downward, and the output straight line is parallel to the x axis (OUT_ZY = 1).
, And is defined as a case where the vehicle is moving leftward (OUT_SX = 1).

In corner A1 ', the input straight line is parallel to the x-axis (INP_ZY =
1) When the output straight line is not parallel to the x-axis (OUT_ZY = 0) and faces downward (OUT_SY = 0), and the straight line before the input straight line parallel to the x-axis is This is the case where the straight line immediately before becoming parallel faces downward (INP_SY = 0). Therefore, the corner A1 'includes a case where a straight line parallel to the x-axis reciprocates left and right a plurality of times.

The mode of SAM or DIF is set (defined) corresponding to each corner at the beginning of the special corner (A2, B2, A3, B3) and at the middle of the special corner (A2 ', B2', A3 ', B3'). . Corner A
4 'indicates that the input straight line is parallel to the x-axis (INP_ZY = 1), the output straight line is not parallel to the x-axis (OUT_ZY = 0) and points upward (OUT_SY = 1), and the input straight line is parallel to the x-axis. There are two cases because the straight line before the straight line, which is just before being parallel to the x-axis, is defined as facing down (INP_SY = 0). That is, the problem (in the case of DIF mode) and the problem (in the case of SAM mode) that the coordinate (x coordinate) of the intersection of the input straight line and the straight line before it is larger than the coordinate (x coordinate) of the intersection of the input straight line and the output straight line. is there. In the DIF mode, the vector direction of the straight line means clockwise, and in the SAM mode, it means counterclockwise. DI in the corner selection processing described later
In F mode, two points are selected, and in SAM mode, neither point is selected. The same applies to the corner B4 '.

FIG. 74 is a block diagram of the hardware of the corner coordinate selection unit. Reference numerals 91 and 92 denote registers MIN and MAX, respectively, which store the minimum data or the maximum data after the operation of the comparator CMP / MUX95. 93 is a pipeline register
This register ACC temporarily stores the output of the PIP2X83.
94 is register MIN91, register MAX92, or register ACC9
A multiplexer for selecting any one of the three outputs. The comparator CMP / MUX 95 outputs large data or small data after the operation, or passes the output of the pipeline register PIP2X83. 97 is comparator C
Output FIFO-X that latches the x coordinate output by MP / MUX95,
Reference numeral 98 denotes an output FIFO-Y for latching the y coordinate output from the pipeline register PIP2Y85.

The processing for each corner by the corner coordinate selection unit 34 is summarized as follows.

When corner A1, the end X at the corner is set to register AC
Once stored in C93, the content is compared with the start X, and the larger one is selected (1 data selection).

End X and Start X at corner A4
Is selected as it is (2 data selection).

When corner B1, the end X at the corner is registered in the register AC.
Once stored in C93, the contents are compared with the start X, and the smaller one is selected (1 data selection).

End X and Start X at corner B4
Is selected as it is (2 data selection).

At the corner A1 ', the value of the register MAX92 is compared with the start X at the corner, and the larger one is selected (1 data selection).

If the DIF / SAM mode is DIF mode at corner A4 ', select the value of register MAX92 and
Is compared with the start X, and the smaller one is selected (2 data selection). Not selected in SAM mode (0 data).

At the corner B1 ', the value of the register MIN91 is compared with the start X at the corner to select the smaller one (1 data selection).

If the DIF / SAM mode is the DIF mode at the corner B4 ', the value of the register MIN91 is selected, and the larger value is selected by comparing the value of the register MAX92 with the start X (2 data selection). Not selected in SAM mode (0 data).

At the corner A2, the DIF / SAM mode is set to DIF, the x coordinate of the end point of the output straight line is stored in the register MIN91, and the start X of the corner is set to the register MAX92 and the register (D_DELX) 51.
(0 data). Register (D-DE
LX) 51 is stored in the special processing state ST20 in the coordinate calculation shown in FIG.

At the corner A3, the DIF / SAM mode is set to SAM, the x coordinate of the end point of the output straight line is stored in the register MAX92, and the start X of the corner is set to the register MIN91 and the register (D_DELX) 51.
(0 data).

In the case of corner B2, the DIF / SAM mode is set to SAM, the x coordinate of the end point of the output straight line is stored in the register MIN91, and the start X of the corner is set to the register MAX92 and the register (D_DELX) 51.
(0 data).

At the corner B3, the DIF / SAM mode is set to DIF, the x coordinate of the end point of the output straight line is stored in the register MAX92, and the start X of the corner is set to the register MIN91 and the register (D_DELX) 51.
(0 data).

At the corner A2 ', the value stored in the register (D_DELX) 51 (the x-coordinate value of the starting point of the straight line parallel to the x-axis for the first time) is compared with the x-coordinate value of the ending point of the output straight line, and the register (D_DELX ) If the value of 51 is larger, set the mode to DIF,
If smaller, SAM. The x coordinate of the end point of the output straight line is compared with the value of the register MIN91, and the smaller one is stored in the register MIN91 (0 data). This comparison processing is performed in the state ST26 of the special processing in the coordinate calculation shown in FIG.

At the corner A3 ', the value stored in the register (D_DELX) 51 (the x-coordinate value of the start point of the straight line parallel to the x-axis for the first time) is compared with the x-coordinate of the end point of the output straight line, and the register (D_DELX) If the value of 51 is larger, DIF / SAM mode is set to DIF
And SAM if smaller. Compare the x-coordinate of the end point of the output straight line with the value in the register MAX92, and determine the larger one in the register MAX.
Stored in 92 (0 data).

At the corner B2 ', the value stored in the register (D_DELX) 51 (the x-coordinate value of the start point of the straight line parallel to the x-axis for the first time) is compared with the x-coordinate value of the end point of the output straight line, and the register (D_DELX) is compared. ) If the value of 51 is larger, set the DIF / SAM mode to SAM.
And DIF if smaller. Compare the x-coordinate of the end point of the output straight line with the value in register MIN91, and determine the smaller one in register MIN91.
Stored in 91 (0 data).

At the corner B3 ', the value stored in the register (D_DELX) 51 (the x-coordinate value of the start point of the straight line parallel to the x-axis for the first time) is compared with the x-coordinate of the end point of the output straight line, and the register (D_DELX) If the value of 51 is larger, set the DIF / SAM mode to SAM
And DIF if smaller. Compare the x-coordinate of the end point of the output straight line with the value in the register MAX92, and determine the larger one in the register MAX.
Stored in 92 (0 data).

FIG. 75 shows a sequencer for generating a control signal for controlling the corner coordinate selector 34 of FIG.
State counter 101 consisting of PAL and PROM 10 with register
It is composed of two. The state counter 101 has a 4-bit signal CNT0 corresponding to the signal described on the left side of the figure.
To 3 are output to the lower 4 bits A0 to 3 of the PROM 102. A signal DIF / SAM indicating the mode of DIF / SAM is supplied to the most significant bit A8 of the PROM 102, and the middle four bits, bit A
4 to 7 are supplied with a 4-bit CNUM signal. PRO
M102 outputs each control signal shown in Table 5 corresponding to these input signals.

Signals CNUM0 to f (H) are signals generated in accordance with the direct status and MODE0 to MODE3 shown in Table 2 and FIG. 37. When the start of the polygon and the second coordinate, CNUM0 is Generated. CNUM1 to 7 or CNUM8 to b are generated at the third and subsequent coordinates of the polygon, and CA
CNUMf is generated for a DM command or data.

As will be described later, no processing is performed for CNUM0, and corner processing and linear processing are performed for CNUM1 to CNUM, corner processing is performed for CNUM8 to b, and command processing is performed for CNUMf.

FIG. 76 shows an arrangement of control signals in the PROM 102. Two sets of data of CNUM0 to CNUMf are prepared, one of which is used in the case of the SAM mode and the other is used in the case of the DIF mode. SAM or DIF mode data is CNUM6,7
And the other data of CNUM0 to 5, and 8 to f are the same in the case of the SAM mode and the DIF mode.
The data of CNUM0 to CNUM is composed of data of states ST0 to STF arranged at respective addresses of 0 to F. For example, in CNUM0, state ST
For 0, CNUM1 and 2, addresses 0 to 4, 6, 7, 8
The data of the states ST0 to 4, 6, 7, and 8 are respectively arranged.

FIG. 77 is a state transition diagram of the corner coordinate selection unit 34 in FIG. In the initial state ST0, the signal STRT is turned on and MODE0 (polygon start data) or MODE1
If it is (the second data of the polygon) (if it is CNUM0), it waits, the signal STRT is turned on, and if it is MODE2 (data of the vertex of the polygon) or MODE3 (command or data to CADM) And a transition to the command processing state.

In the corner and command processing states, corner processing is executed when the mode is MODE2, and command processing is executed when the mode is MODE3.

The processing in the corner processing is classified into six types, CTYP1 to CTYP6. CTYP1 when corner A1 (CNUM1) or B1 (CNUM2), CTYP2 when corner A4 or B4 (CNUM3), CTYP3 when corner A1 '(CNUM4) or B1' (CNUM5), corner A4 '(CNUM6) or B4' (CNUM7) CTYP4, corner A2 or B2 (CNUM8) or corner A3 or B3 (C
NUM9), CTYP5, corner A2 'or B2' (CNUMa)
Alternatively, at the corner A3 'or B3' (CNUMb), each processing of CTYP6 is executed.

Command processing is performed in the case of CNUMf, and is set to CTYP7.

In the corner and command processing, when the signal CNTOVR is logic 1 and DATAEN is logic 0 at CTYP1 to 4 or 5 to 7, the processing returns to the state ST0. When the signal CNTOVR is logic 0 at CTYP1 to 4, the linear processing state (ST6, ).
After the end of the linear processing state, the process returns to the state ST0.

FIG. 78 is a state transition diagram of corner processing of CTYP1. If the signal STRT turns on and is CNUM1, the state shifts to state ST2 via state ST1, where the pipeline register PIP
2X83 data (end X) is latched in the register ACC93. In the state ST2, the control waits when the signal DATAEN is logic 0, and when the signal DATAEN is logic 1 (the pipeline register PIP2X83
When the start X is latched at the time, the state shifts to the state ST3.

In the state ST3, the value of the register ACC93 and the value of the pipeline register PIP2X83 are compared by the comparator CMP / MUX95, and when the former is equal to or larger than the latter,
The value of register ACC93 is transferred to output FIFO_X97, and if smaller, the data of pipeline register PIP2X83 is output to output FIF
Transferred to O_X97. That is, the larger of the value of register ACC93 and the value of pipeline register PIP2X83 is output F
Transferred to IFO_X97. In state ST3, the signal CNTOVR
Returns to the initial state ST0 when is a logical 1, and shifts to the state ST4 when is a logical 0. Signal CNTO in state ST4
Initial state ST when VR is logic 1 and signal DATAEN is logic 0
When the signal CNTOVR is logic 0 and the signal DATAEN is logic 1, the state shifts to the linear processing state ST6. When both the signals CNTOVR and DATAEN are logic 1, the state shifts to the linear processing state ST8. stand by.

In the case of CNUM2, the same process as in the case of CNUM1 is executed in state ST3, except that the smaller of the values of the register ACC93 and the pipeline register PIP2X83 is transferred to the output FIFO_X97.

FIG. 79 is a timing chart of the corner processing of CTYP1. In state ST2, pipeline register PIP2X
The data end X of 83 is latched in the register ACC93, and furthermore, the data is inputted to the comparator CMP / MUX95 through the multiplexer 94.
Is output to On the other hand, the start X is latched in the pipeline register PIP1X82 in synchronization with the rising edge of the signal TRANS in the state ST1.
Is transferred to the pipeline register PIP2X83 in the state ST2. Comparator CMP / MUX in state ST3
95 compares the end X input from the multiplexer 94 with the start X input from the pipeline register PIP2X83, and determines which is larger (in the case of CNUM1) or smaller (CNUM2).
) Is selected and output. This selection data is the signal OFIXWT
Is latched in the output FIFO_X97 in synchronization with the rising edge of.

FIG. 80 is a state transition diagram of the corner processing of CTYP2. When the state shifts to the state ST2 via the state ST1, the value of the pipeline register PIP2X83 is written to the output FIFO_X97. Next, the process proceeds to the state ST3, where the signal DATAEN is set to the logic 1
, And transitions to state ST4 when the logic 1 is reached. Here, the data of the pipeline register PIP2X83 is written to the output FIFO_X97. Output CNTOVR is logic 1
At this time, the process returns to the state ST0. In the state ST5, the signal DATAEN is set to logic 0.
And when the signal CNTOVR is at logic 1, the signal DATAE
When N is logic 1 and the signal CNTOVR is logic 0, the state shifts to the linear processing state ST6, and when both the signal DATAEN and CNTOVR are logic 1, the state shifts to the linear processing state ST8, and otherwise stands by.

FIG. 81 is a timing chart of the corner processing of CTYP2. The end X is latched in the pipeline register PIP2X83, and the next start X in the state ST1 is latched in the pipeline register PIP1X82. In the state ST2, the end X of the pipeline register PIP2X83 is output from the comparator CMP / MUX95, and this end X is written to the output FIFO_X97 in synchronization with the rising edge of the signal OFIXWT. In the state ST3, the start X of the pipeline register PIP1X82 is synchronized with the rising edge of the signal TRANS and the pipeline register PIP2
Transferred to X83 and output from comparator CMP / MUX95. This start X is the signal OFIXWT in state ST4.
Is latched in the output FIFO_X97 in synchronization with the rising edge of.

FIG. 82 is a state transition diagram of the corner processing of CTYP3. When the signal STRT is turned on and is CNUM4, in the state ST1, the state waits when the signal DATAEN is logic 0, and when the signal is logic 1 (when the start X is latched in the pipeline register PIP2X83), the state ST2 is entered.

In state ST2, the value of the pipeline register PIP2X83 and the value of the register MAX92 are compared by the comparator CMP / MUX95, and if the former is equal to or greater than the latter,
The value of pipeline register PIP2X83 is transferred to output FIFO_X97, and if smaller, the data in register MAX92 is output to output FIFO_X97.
Transferred to O_X97. That is, the larger of the value of the register MAX92 and the value of the pipeline register PIP2X83 is the output F
Transferred to IFO_X97. In state ST2, the signal CNTOVR
Returns to the initial state ST0 when is a logical 1, and shifts to the state ST3 when is a logical 0. Signal CNTO in state ST3
Initial state ST when VR is logic 1 and signal DATAEN is logic 0
When the signal CNTOVR is logic 0 and the signal DATAEN is logic 1, the state shifts to the linear processing state ST6. When both the signals CNTOVR and DATAEN are logic 1, the state shifts to the linear processing state ST8. stand by.

In the case of CNUM5, in the state ST2, the same processing as in the case of CNUM4 is executed, except that the smaller one of the values of the pipeline register PIP2X83 and the register MIN91 is transferred to the output FIFO_X97.

FIG. 83 is a timing chart of the corner processing of CTYP3. Pipeline register PIP1X in state ST1
The start X is latched at 82, and the multiplexer 94 is connected to the register MAX92 (for CNUM4) or the register MIN9.
Outputs the value of 1 (for CNUM5). When the signal DATAEN is turned on, the start X is further added to the pipeline register PI
Transferred to P2X83. Comparator in state ST2
The CMP / MUX95 selects and outputs the larger of the value of the register MAX92 and the start X in the case of CNUM4, and the smaller of the value of the register MIN91 and the start X in the case of CNUM5, and the selected data is the rising edge of the signal OFIXWT. Output in sync with
Written to FIFO_X97.

FIG. 84 is a state transition diagram of the corner processing of CTYP4. CNU
In case of M6, transition to state ST2 via state ST1,
Then, the value of the register MAX92 is written to the output FIFO_X97. After that, the state moves to the state ST3, and the signal DATAEN becomes
, And transitions to state ST4 when the logic 1 is reached. Pipeline register P in state ST4
The value of IP2X83 and the value of register MIN91 are compared, and the smaller value is written to output FIFO_X97. Further, when the signal CNTOVR is logic 1, the state shifts to state ST0, and when the signal CNTOVR is logic 0, the state ST5 shifts. In the state ST5, when the signal DATAEN is at logic 0 and the signal CNTOVR is at logic 1, the state ST0 is performed. When the signal DATAEN is at logic 1 and the signal CNTOVR is at logic 0, the processing is performed in the state ST6. The process proceeds to the processing state ST8, and waits otherwise.

In the case of CNUM7, except that the value of the register MIN91 is written to the output FIFO_X97 in the state ST2, and that the larger value of the pipeline register PIP2X83 and the register MAX92 is written to the output FIFO_X97 in the state ST4, The same processing is performed.

The above is the case where the signal DIF / SAM is logic 1 (DIF mode). If the signal DIF / SAM is logic 0 (SAM mode), after waiting in step ST1 until the signal DATAEN becomes logic 1, the state
Move to ST2. When the signal DATAEN is logic 0 and the signal CNTOVR is logic 1 in the state ST2, the state ST0, the signal DATAE
State N of linear processing when N is logic 1 and CNTOVR is logic 0
At T6, when both the signals DATAEN and CNTOVR are at logic 1, the state shifts to the linear processing state ST8, respectively, and otherwise stands by.

Figure 85 shows CTYP4 with signal DIF / SAM at logic 1 (DIF mode)
9 is a timing chart of a corner process in the case of FIG. In state ST1, the multiplexer 94 and the comparator CMP / MUX95 store the value of the register MIN91 when CNUM6 is
At this time, the value of the register MAX92 is selectively output. The value selected and output is written to the output FIFO_X97 at the timing of the rising edge of the signal OFIXWT in the state ST2. In state ST3, start X is transferred from pipeline register PIP1X82 to PIP2X83, and in state ST4, start X is compared with the value of register MIN91 or MAX92, and the smaller or larger one is selected, and signal OFIXWT
Is written to the output FIFO_X97 at the timing of the rising edge of.

Figure 86 shows CTYP4 with signal DIF / SAM at logic 0 (SAM mode)
9 is a timing chart of a corner process in the case of FIG. In this case, in state ST1, the pipeline register PIP1X82
Is latched, and this is further transferred to the pipeline register PIP2X83. Pipeline register P
IP1X82 the next data D _0, D ₁ are sequentially latched in the data D ₁ is a pipeline register in the state ST2 PIP2X83
And output from the comparator CMP / MUX95.

FIG. 87 is a state transition diagram of corner processing in the case of CTYP5. In the case of CNUM8, a transition is made to state ST2 via state ST1, where the value of pipeline register PIP2X83 is latched in register MAX92. Thereafter, the state shifts to state ST4 via state ST3, where the pipeline register P
After the value of IP2X83 is latched in the register MIN91, the state shifts to the state ST0.

In the case of CNUM9, except that the value of pipeline register PIP2X83 is transferred to register MIN91 in state ST2 and to register MAX92 in state ST4, respectively.
The same processing as in the case of is performed.

FIG. 88 is a timing chart of the corner processing of CTYP5. Pipeline register PIP1X in state ST1
The start X is latched at 82, and the end X of the pipeline register PIP2X83 is output from the comparator CMP / MUX95. In state ST2, the comparator CMP
End X output from / MUX95 is in register MAX92 (CNUM8
) Or MIN91 (for CNUM9). In state ST3, start X is the pipeline register P
Transferred from IP1X82 to PIP2X83, comparator CMP / MUX95
Output from This start X is latched in the register MIN91 (for CNUM8) or MAX92 (for CNUM9) in the state ST4.

FIG. 89 is a state transition diagram of corner processing in the case of CTYP6. In the case of CNUMa, after waiting until the signal DATAEN becomes logic 1 in the state ST1, the state becomes logic 1
Move to ST2. In the state ST2, the value of the pipeline register PIP2X83 is compared with the value of the register MIN91, and the smaller one is latched in the register MIN91, and then the state shifts to the state ST0.

In the case of CNUMb, in the state ST2, the value of the pipeline register PIP2X83 is compared with the value of the register MAX92, and the same processing as in the case of CNUMa is performed, except that the larger one is latched by the register MAX92.

FIG. 90 is a timing chart of the corner processing of CTYP6. In the state ST1, the value of the register MIN91 (for CNUMa) or the value of the register MAX92 (for CNUMb) is selected and output from the multiplexer 94, and the start X is transferred from the pipeline register PIP1X82 to PIP2X83. In state ST2, the comparator CMP / MUX95
Start X and value of register MIN91 (CNUMa)
Or, the value of the register MAX92 (in the case of CNUMb) is compared, and the smaller one or the larger one is the register MIN91 or the register MAX.
Latched at 92 respectively.

FIG. 91 is a state transition diagram of command processing in the case of CTYP7. When the signal DATAEN becomes logic 1 in the state ST1, the state shifts to the state ST2. After the data of the pipeline register PIP2Y85 is transferred to the output FIFO_Y98 in the state ST2, the process returns to the state ST0.

FIG. 92 is a timing chart of the command processing of CTYP7. When the signal DATAEN is turned on in the state ST1, the command CMND latched in the pipeline register PIP1Y84 is synchronized with the signal TRANS and the pipeline register P
Transferred to IP2Y85. In state ST2, the signal OFIYW
Command is output at the rising edge of T. FIF
Written to O_Y98.

The command for controlling the CADM (sorting means 22) is input only to the counter (CAPY) 53 and not output to the counter (CAPX) 52. Therefore, only in this case is the signal OF
Only the output FIFO_Y98 operates at the timing of IYWT, and in other cases, the output FIFO_X97 and the output FIFO_Y98 output the signal OFIWT (O
Data is latched simultaneously in synchronization with FIXWT and OFIYWT).

FIG. 93 is a state transition diagram of the linear processing. CTYP1 to 4
When the signal DATAEN is logic 1 and CNTOVR is logic 0, the pipeline registers PIP2X83, PIP2Y8
Data of 5 is written to the output FIFO_X97 and the output FIFO_Y98, respectively. Next, the process proceeds to the state ST7. When the signal DATAEN is logic 0 and CNTOVR is logic 1, the state ST0, the signals DATAEN and C
When both NTOVRs are logic 1, the signal DATA
When EN is at logic 1 and CNTOVR is at logic 0, the state shifts to the state ST6, respectively, and otherwise stands by.

In the case where the signals DATAEN and CNTOVR are both logic 1 in CTYP1 to CTYP4 and when the transition from the state ST7 is made, in the state ST8, the outputs of the pipeline registers PIP2X83 and PIP2Y85 are latched by the output FIFO_X97 and the output FIFO_Y98, respectively, and then the state is shifted to the state ST0. I do.

94 Figure is a timing chart of the linear processing in the vicinity of the end point C _N in the case of LINE ALL. State ST6 and ST7 are repeated, and in each state ST6, the pipeline register PIP2X
83, PIP2Y85 data C _N-3 and C _N-2 output FIFO_X97, output F
Each is sequentially written to IFO_Y98. Signal DATAEN and CNTOVR is shifted to the state ST8 becomes a logic 1 in the state ST7, C _N-1 point of the previous one endpoint C _N output FIFO_X97, output FI
After writing to FO_Y98, the state shifts to the state ST0.

95th figure is a timing chart of the linear processing in the vicinity of the end point C _N in the case of LINE BFR. In the state ST6, the outputs C _N-4 and C _N-2 of the pipeline registers PIP2X83 and PIP2Y85 are output in synchronization with the rising edge of the signal OFIWT to output FIFO_X97,
Each is sequentially written to the output FIFO_Y98. Then state
Move to ST0 via ST7.

When the point C _N-1 immediately before the end point C _N is also selected, the signal DATAEN is turned on in the state ST7 and transitions to the state ST8 as shown by a broken line in the figure, and the point C _N-1 is output as the output FIFO_X97 and the output FIFO_X97. F
Written to IFO_Y98. After that, the state shifts to the state ST0.

The 96 Figure is a timing chart of the linear processing in the vicinity of the end point C _N in the case of LINE the NOW. Dot in state ST6
After C _N-5 and C _N-3 are written to the output FIFO_X97 and the output FIFO_Y98, if the signal DATAEN is logic 0 in the state ST7, the state shifts to the state 0.

If the end point C _N is also chosen, as indicated by a broken line in the figure, the signal DATAEN becomes logic 1 in the state ST7, the process proceeds to state ST8. Therefore, point C _N-1 is output FIFO_X97, output F
After being written to IFO_Y98, the state transits to the state ST0.

As described above, in the straight line processing, data is written to the output FIFO up to the effective point immediately before the last effective point (end X) of the line segment. The end X is stored in the pipeline register PIP2 and used for the next corner processing.

FIG. 97 is an overall block diagram of the outline coordinate generating means 21. In the figure, reference numerals 111 and 112 denote state counters composed of PALs with registers, which constitute a sequencer of the input control unit 31 and the output control unit 35, respectively.

FIG. 98 is a timing chart of the overall operation of the contour coordinate generation means 21. Now, assuming that polygon data composed of four vertices a, g, k, and o are processed in the clockwise direction, the coordinate calculator 32 calculates a constant of a straight line defined by the start point a and the end point g. After that, the coordinates between them are calculated, and the coordinates of the points a, b, c, d, e, f, and g are sequentially output. Next, the same processing is sequentially repeated for the straight line defined by the start point g and the end point k, the start point k and the end point o, the start point o and the end point a, and the start point a and the end point g. The straight line ag is processed twice since the straight line oa and the straight line ag are required for the processing using the point a as a corner.

The coordinates of each point generated by the counters (CAPX) 52 and (CAPY) 53 are stored in pipeline registers PIP1X82, PIP1Y84, pipeline registers PIP2X83, PIP2Y85, output FIFO_X97, and output FIFO_Y98 each time one clock TRANS is generated. It is transferred sequentially. First stage pipeline register PI
The coordinates of all points are transferred to P1X82 and PIP1Y84,
In the second stage pipeline registers PIP2X83 and PIP2Y85,
Only the coordinates of the points (hatched points in the figure) selected so that two (even number) points exist on the same y-axis are transferred. Further, in the corner coordinate selecting section 34, for example, at the corner formed by the point o, one (odd number) is placed on the same y-axis.
Since only the point exists, one point o is selected twice so that two points are formally present on the y-axis. In this way, sorting at the subsequent stage and drawing processing between two points on the same y-axis can be performed quickly.

The coordinates of the points constituting the polygon are output from the outline coordinate generation means 21 in the order in which the polygon is traced clockwise or counterclockwise. Next sort means
Reference numeral 22 reorders the data in an order suitable for drawing.

For example, when there is a polygon composed of points a to n as shown in FIG. 99, the outline coordinate generation means 21 sequentially outputs the coordinates of points a to n in the order in which the polygon is traced clockwise. The sorting means 22 has the same y as shown in FIG.
The two points on the axis are arranged so as to form a set, with the smaller x-coordinate first, and the set with the smaller y-coordinate first. That is, in the case of this embodiment, the order of abcde ... mn is (na) (mb) (ec) (k
d) ... can be rearranged.

In order to perform such rearrangement, the x-coordinate and the y-coordinate of each point are combined such that the y-coordinate becomes the upper digit. If the combined data (number) is sorted as one number and the smaller one is sorted first, the above-described rearrangement is performed.

FIG. 101 is a block diagram of the sorting means 22 for performing such processing. Reference numerals 121 and 122 denote input and output interfaces, respectively. 126 to 129 are ICs that perform an operation of sorting input data in ascending order (for example, product name CADM (Content
Addressable Data Manager)). CADM126 to 129
Are controlled by sequencers 131 to 134, respectively. The sequencer 131 responds to the input of the data write end signal BLKE0, the sort end signal DONE0, and the data read end signal ZERO0, and outputs a write available (Write Avairable) signal WA.
0, Write Next Bank signal WNB
0, and outputs Read Available (RA), RA0, and Read Next Bank signal RNB0. The same applies to the other sequencers 132 to 134.

123 is a multiplexer and interfaces 121 and 12
2 is selectively connected to any one of the CADMs 126 to 129. Reference numeral 124 denotes a bank control, which controls the multiplexer 123 in accordance with the signals WNB0 to WNB3 output from the sequencers 131 to 134, and switches the interface 121 to the CADMs 126 to 1.
Connect to any of 29. Reference numeral 125 denotes a bank control, and signals RNB0 to RNB output from the sequencers 131 to 134 are provided.
The multiplexer 123 is controlled corresponding to B3, and the interface 122 is connected to one of the CADMs 126 to 129. CADM1
When any one of 26 to 129 is connected to the interface 121, the interface 122 is connected to another CADM.

FIG. 102 is a timing chart of the sorting means 22 in FIG. When the writing of any of the CADMs 126 to 129 (for example, 126) is completed, a signal BLKE0 is generated. At this time, the signal WA0 is inverted from logic 1 to logic 0, further writing is inhibited, and the CADM 126 starts sorting. On the other hand, a signal WNB0 is generated in synchronization with the signal BLKE0,
Writing of data to another CADM (for example, 127) is instructed. The CADM 126 generates a signal DONE0 when finishing the sorting. At this time, the signal RA0 is inverted from logic 0 to logic 1, the interface 122 is connected to the CADM 126, and the sorted data is read. When reading is completed, signal ZERO0 is generated, signal WA0 is inverted to logic 1 and CADM
126 becomes writable and waits for data input.
In addition, the signal RA0 is inverted to logic 0, the subsequent reading is prohibited, and the signal RNB0 is generated to instruct reading of another CADM.

FIG. 103 shows the number of CADMs 126 to 129 and the timing of sorting. Now, assuming that it takes 0.5 ms to generate outline coordinates of one character (transfer data to the sorting means 22), 1 ms to sort, and 0.5 ms to draw, if there is one CADM, 0.5 ms
After the data is input, the sorting is performed for 1 ms, and the drawing is performed for 0.5 ms after the sorting is completed.
One character can be drawn each time.

On the other hand, if there are two CADMs, data can be written to the other while one is sorted, so 1 ms
One character can be drawn each time. Similarly, if there are three CADMs, one character will be output every 0.7 ms, and if there are four CADMs, 0.5 ms.
One character can be drawn each time.

When the coordinates sorted by the sorting unit 22 are input to the drawing unit 23 in the next stage, the drawing unit 23 generates drawing data and draws a character on the bit map 24.

In the present invention, the bitmap 24 is used in two modes, a single mode and a double mode. In the case of single mode, as shown in FIG.
8912 bits for WORD, 8192 bits for Y axis direction,
In the case of double mode, as shown in FIG. 105, the X-axis direction is 4096 bits (256 words) and the Y-axis direction is 16384 (8192 ×
2) Bits are used.

Predetermined coordinate values (X,
When Y) is represented by the address of the bitmap 24 (memory), the bitmap 24 is written as a 16-bit W as shown in FIG.
If the lower 4 bits of the coordinate X are Xbit and the other upper bits are Xword, memory (byte) address = (512Y + Xword) x 2 memory bits = Xbit in double mode Memory (byte) address = (256Y + Xword) × 2 Memory bit = Xbit.

That is, as shown in FIG.
The memory addresses (byte addresses) are sequentially assigned from the upper left to the lower right in units of (2 bytes). FIG. 106 shows that each WORD is arranged in one column in the vertical direction. The position is specified by the memory address, and the position inside the WORD is specified to one of 16 ways by 4 memory bits.

FIG. 108 is a block diagram of hardware of the drawing means 23 for controlling the bitmap 24 according to such a principle. Data IO bus (DATA IO BUS) 141 has sorting means 22
Are input. The coordinates are output by the data IO bus 141 according to a format as shown in FIG. The coordinates (drawing data) are composed of 13 bits, and the MSB (D12) is the end of the block (logic 1).
Or, it indicates non-end (logic 0), and the lower 12 bits indicate coordinates. Therefore, it is possible to represent substantially 4096 kinds of coordinates. MSB is in the data IO bus control 142,
The coordinates are supplied to the adder 143, respectively. The coordinates are the Y coordinate (Y0, Y2, Y3 ...) of the starting point to be drawn, and the X coordinate (X
0, X2...) And the X coordinate (X1, X3...) Of the end point (the Y coordinate of the end point is the same as the Y coordinate of the start point).

On the other hand, a DSPIO bus (DSP IO B
US) 152 via a coordinate transformation means (DSP) 15 in accordance with the format shown in FIG. 110, X_BASE, Y_BASE, OPERATIO
RG drawing commands of N and TEXTURE are supplied and stored.
RG drawing command consists of 3 words, 1st word is X_BASE, 1st word
The 2 words are Y_BASE, the OPERATION is arranged in the D8 bit of the third word, and the TEXTURE is arranged in the lower 7 bits. FIFO output controller (FIFO OUTPUT CONTROLER) 150 is FIFO144
Control the X_BASE, Y_BASE, OPERATION, and TEXTURE data in registers X_BASE145, Y_BASE146, OPERATION147,
Output and memorize each in TEXTURE148.

X_BASE and Y_BASE are as shown in FIG.
The relative coordinates (Y0, X0, X1, Y2, X2, X3
..) are X and Y coordinate values of a drawing reference for converting into absolute coordinates on the bitmap 24. X_BASE takes a value from −8191 to +8191 in single mode, -4095 to +4095 in double mode, and Y_BASE takes a value from −8191 to +8191 in single mode and -16383 to +16383 in double mode. Take. Register X_BASE
One output of 145 or Y_BASE 146 is selected by the multiplexer 149 and supplied to the adder 143. The timing is controlled by the data IO bus control 142 and adder 1
43 is Y_BASE for coordinates Y0, Y2 ..., coordinates X0, X1, X2, X3
, And X_BASE is added to each. The storage register control (STORAGE REGISTER CONTROL) 167 controls the timing, and among the coordinates output from the adder 143, the Y coordinate is registered in the register YCOOR STORAGE161, the X coordinate of the drawing start point is registered in the register XSTART STORAGE163, and the X coordinate of the end point is registered in the register. Let XEND STORAGE165 latch each.

The data latched in the register YCOOR STORAGE 161 is input to the upper 14 bits of the 1-bit shifter selector 168 via the register YCOOR 162. Register XSTART STORAGE16
The data latched in 3 is loaded into the counter XSTART164, and the counter XSTART164 performs a count-up operation from the loaded value (the X coordinate of the starting point) in synchronization with the clock output from the VME bus and the system controller 178. The MSB (D12) of the output of the counter XSTART164 is the LSB of the 1-bit shifter selector 168, the upper 9 bits (D4 to D12) are to the comparator 171 and the lower 4 bits (D0 to D3) are the 4 bits (D4 to D4) of the bit pattern ROM 174. D7).

The data latched in the register XEND STORAGE 165 is the upper 9 bits (D4 to D12) via the register XEND 166.
Are supplied to the comparator 171 and the upper 4 bits (D0 to D3) are supplied to the lower 4 bits (D0 to D3) of the bit pattern ROM 174, respectively.

A single or double mode is set in the register RG control 181 via the VME bus 6 in response to an input from the CPU 4. Signal SINGLE corresponding to this mode
/ DOUBLE is supplied from the register RG control 181 to the 1-bit shifter selector 168. The 1-bit shifter selector 168 sets the bits D0 to D of the Y coordinate in the single mode.
13 input data in the double mode, bits D1 to 14
Are transferred to bits D9 to D9 of the address of the VME bus 6, respectively.
Output to 22. Bits D1 to D8 of the address of the VME bus 6 include bits D4 to D11 of the output of the counter XSTART164.
Is supplied. LSB (D0) of the address of VME bus 6
MSB (D23) is set to 0.

The above is schematically shown in FIG. 112. That is, in the case of the single mode, the X coordinate of the drawing start point or the ending point and the Y coordinate thereof are each represented by 13 bits, and the upper 9 bits (D4 to D1) of the X coordinate (X coordinate of the starting point)
Xword is calculated by 2) and Xb is calculated by lower 4 bits (D0 to D3).
it is each formed. On the other hand, in the case of the double mode, the lower one bit of the Y coordinate is increased, and the upper one bit of the X coordinate is reduced accordingly. 13 bits of Y coordinate and upper 9 of X coordinate
The position of the word on the bit map 24 is specified by the (or 8) bits, and the bit pattern in the word is determined by the lower 4 bits of the X coordinate as described later.

As shown in FIG. 111, when starting drawing from the starting point (X0, Y0) of the X coordinate to the ending point (X1, Y0), the counter X START164 counts up the loaded value by one and increments the drawing point. Generate an X coordinate. Comparator COMP EQUAL
171 uses this count value as the value of register XEND166 (the X
The coordinates are compared with the coordinates X1), and when they match, a signal is output to the ROM mode select array (ROM MODE SELECT ARRAY) 172.
The ROM mode select array 172 determines whether or not the signal supplied from the VME bus and the system controller 178 immediately after the start of drawing and the X coordinate of the drawing point supplied from the comparator COMP EQUAL 171 match the X coordinate of the end point. The following ROM MODE signal is output in response to this signal.

(1) Immediately after the start of drawing and when the coordinates match ... ROM MODE11 (2) Immediately after the start of drawing and when the coordinates do not match ... ROM MODE01 (3) When the coordinates match rather than immediately after the start of drawing ... ROM MODE10 ( 4) When the coordinates do not match immediately after the start of drawing ... ROM MODE00 This ROM MODE signal is the bit D of bit pattern ROM174.
8, supplied to D9. This bit pattern ROM174 M
The signal OPE output from the register OPERATION147 is provided to SB (D10).
RATION has been entered.

The bit pattern ROM 174 includes two portions 174A and 174B as shown in FIG. 113, and when a predetermined signal is input, generates the upper 8 bits and the lower 8 bits of the corresponding predetermined bit pattern. The bit pattern ROM 174 outputs the signal OP
Positive pattern when ERATION (POLARITY) is logical 0,
Invert patterns are respectively generated when logic one. The patterns generated corresponding to the data (ROM START) from the counter XSTART 164 and the data (ROM END) from the register XEND 166 are defined as shown in Tables 6 and 7, respectively.

When the ROM MODE is 01, the start pattern (6th
When the table is 10, the end pattern (Table 7) is selected, and when 11, the logical product of the start pattern and the end pattern is generated. At 00, the 16-bit ROM output generates HFFFF if OPERATION is 0, and OPERATION
If H is 1, H0000 is generated.

Table 8 shows an example of a bit pattern generated by the bit pattern ROM 174 in response to an input.

Fig. 114 shows the ROM MODE and the number of drawing (WRITE) times (WORD
Number). Normal (when OPERATION is logic 0 and standard OR mode) Start point X0 is ROM MODE01, end point X1 is 1
It is set to 0, and 00 in the meantime. If the start and end points are within 1 word, ROM MODE11 is set. FIG. 114 (a), (b),
(C) is W The case where the number of RITEs (the number of WORDs) is 4, 2 or 1 is shown.

As shown in FIG. 115, the texture pattern ROM (TE
XTURE PATTERN ROM) 173 has the upper 7 bits (D8 to
D14) contains the data TEXTURE from the register TEXTURE148, and the middle 6 bits (D2 to D7) contain the lower 6 bits (D0 to D5) from the register YCOOR 162 as Y_TEXTURE SELECT.
4 bits (D0, D1) for the bit pattern from the counter X START164 as X_TEXTURE SELECT in the lower 2 bits (D0, D1)
The lower two bits (D4, D5) except for the bits D3 to D3 are supplied. TEXTURE represents the density (gray scale) from black to white by the values 0 to 15, and the predetermined geometric texture such as hatching by the values 16 to 31, and the values 32 to 127 are used for other designations. Is reserved. Two texture patterns ROM173 (173A, 173
B), and a predetermined texture pattern of 8 bits is generated corresponding to the input data. This allows
As shown in FIG. 116, a predetermined texture can be drawn in units of 64 × 64 bits. In this case, the X-axis direction is in units of WORD (16 bits), and the Y-axis direction is in units of bits.

Bit pattern ROM174 output and texture pattern
The output of the ROM 173 is calculated by the AND OR LOGIC ALU 175. This operation is controlled by the output of the register OPERATION147, and when its value is logic 0, the logical product of both inputs (AND)
Is the logical sum (OR) of both inputs when the value is logic 1.
Are respectively calculated.

When a predetermined character or the like is drawn at a predetermined address of the bit map 24, data already drawn at that address is read out first and latched by the register 177 via the VME bus 6. AND OR LOGIC ALU176 is AND OR LOGIC ALU1
The arithmetic operation of 75 and the data of the register 177 is performed. This operation is also controlled by the output of the register OPERATION147, and its value is logic 0.
The logical sum (OR) of both inputs is (logical OR mode), and the logical product (AND) of both inputs is logical 1 (reverse AND mode)
Are respectively calculated.

In the case of the standard OR mode (set mode), as shown in FIG. 117, drawing is performed by setting the bit map 24 to a logical 1 while the bit map 24 is cleared to a logical 0, but a certain pattern has already been drawn. Is not erased, a new character or the like is overwritten thereon.

On the other hand, in the case of the reverse AND mode (clear mode), as shown in FIG. 118, drawing is performed by clearing the state in which the bit map 24 is set to logic 1 to logic 0.

FIG. 119 shows that the register RG CON is transmitted from the CPU 4 through the VME bus 6.
7-bit signal RG CONTROL COMMAN sent to TROL181
D format, value 0 is DOUBLE MODE, value 1 is SI
NGLE MODE is set, and the former is set to Default. Values 2 through 255 are reserved.

FIG. 120 shows the format of a 7-bit signal RG STATUS sent from the register RG STATUS 182 to the CPU 4 via the VME bus 6, in which the value 0 is NOT BUSY, the value 1 is BUSY, and the values 2 to
255 is reserved. The signal BUSY is turned on when the drawing means 23 is accessing the bitmap 24, and at this time, the CPU 4 is prohibited from accessing the bitmap 24.

FIG. 121 shows the DSP (coordinate conversion means) 15 to the DSP IO bus 15
2. Register MAILBOX DSP TO VME183, to CPU 4 via VME bus 6, and from CPU 4 to VME bus 6, register MAILBOX V
This is a format for transferring data to the DSP 15 via the ME TO DSP 184 and the DSP IO bus 152, and each uses 16 bits.

MAILBOX DSP TO VME183 and MAILBOX VME TO DS
P184 is controlled by the DSP IO BUS controller 151 together with the FIFO 144.

FIG. 122 is a timing chart of the system control by the VME bus and the system controller 178. Once the system is reset by the reset pulse, DSP IO B
A command is input from the US 152 to the FIFO 144 and further read out, and the registers X_BASE 145, Y_BASE 146, OPERATION 147,
Transferred to TEXTURE148. When the preparation of DATA IO BUS141 is completed, the values of registers X_BASE145 and Y_BASE146
The values are added to the X and Y coordinates input from the BUS 141 and transferred to the registers YCOOR STORAGE 161, XSTART STORAGE 163, and XEND 165. A predetermined pattern is generated from the texture pattern ROM 173 and the bit pattern ROM 174 corresponding to the data of these registers, and the VME is generated together with the address data.
The data is transmitted to the bit map 24 via the bus 6. Thereby, a predetermined drawing is performed. When the block end data is input to the DATA IO BUS 141, after completing the processing of the last block, the next command is input again from the FIFO 144, and the same processing is repeated.

FIG. 123 shows a sequence of pattern generation and drawing by the VME bus and the system controller 178. When the start of drawing is input, register YCOOR STORAGE161,
Predetermined data is latched in XSTART STORAGE 163 and XEND STORAGE 165, respectively. When the address of the bit map 24 to be drawn on the VME bus 6 is input, the data already drawn there is read out first and latched by the register 177.

On the other hand, the counter XSTART164 increments the count value sequentially from the X coordinate value of the loaded starting point,
Compare with the value of ND166. The ROM mode select array 172 generates a predetermined ROM MODE according to the comparison result. The bit pattern ROM174 is used for this ROM MODE and register XEND166.
A predetermined bit pattern is generated in accordance with the data from, and a texture pattern ROM 173 generates a specified texture pattern. These patterns correspond to the signal OPERATION from the register OPERATION147 and ALU17
The operation is performed by 5, 176, and written to the specified address of the bit map 24.

When the writing of one word is completed, the counter clock is output from the VME bus and the system controller 178, the drawing point (WORD) is moved, and the next word is read and written. Such an operation is repeatedly performed.

FIG. 124 is a more detailed timing chart when data is read from a predetermined address of the bit map 24 and further written. After the address data has been entered,
When the address strobe signal is set to logic 0, the address data is made valid. When the output signal DTACK of the bit map 24 becomes logic 1 and the signal READ / WRITE of the drawing (RG) means 23 becomes logic 1 (READ), the data strobe signal of the drawing means 23 becomes logic 0. As a result, data is read from the bitmap 24. When reading is started, the signal DTACK is inverted to logic 0. Signal DTACK
Becomes logic 0, the data strobe signal is inverted to logic 1 at a predetermined timing. As a result, the signal READ / WRITE is inverted to logic 0 (WRITE), the read data is completed, and the signal DTACK is again inverted to logic 1. At this time, the drawing means 23
The write data is output, the data strobe signal is inverted to logic 0, and the signal DTACK is also inverted to logic 0. Thereafter, at a predetermined timing, the data strobe signal is inverted to logic 1, and the write data ends. At this time, the address strobe signal is also inverted to logic 1. When the data strobe signal becomes logic 1, the signal DTACK
Is inverted to logic one.

As described above, the process of reading data before writing data on the bitmap 24 by the drawing unit 23 is performed by READ_MODIFY_WRITE
It is performed according to a sequence. As a result, the processing time can be shortened as compared with the case where the READ mode is first executed by designating the address, and once terminated, and then the address is again designated and the WRITE mode is executed.

〔The invention's effect〕

As described above, according to the present invention, only the starting point and the ending point of the drawing are selected from the coordinates forming the polygon, and the characters are drawn on the bit map while generating the coordinates that sequentially increase from the starting point to the ending point. As a result, the number of accesses to the bitmap can be reduced and the rendering time can be reduced as compared with the case where a polygon is once drawn on the bitmap, and then scanning is performed to search and select the start and end points of the drawing. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a high-quality character generator of the present invention, FIG. 2 is a principle diagram of an outline system, FIG. 3 is an explanatory diagram of processing of the high-quality character generator of the present invention, and FIG. FIG. 5 is an explanatory diagram of a format of a command and data output from the coordinate conversion means, FIG. 6 is an explanatory diagram of a btoj () function process, FIG. 7 is a flowchart of a coordinate conversion process, FIG. 8 is an explanatory diagram of a dual port RAM, FIG. 9 is a flowchart of a subroutine for loading data from a dual port 0 bank and executing load data, FIGS. 10 to 25 are explanatory diagrams of a command packet, and FIG. Is a diagram for explaining rotation, inclination or translation of characters, FIG. 27 is a flowchart of a subroutine of C_LineFeed, FIG. 28 is a flowchart of a subroutine of C_FormFeed, FIG. 29 is a subroutine of C_PlotFont FIG. 30 is an explanatory diagram of a command packet, FIG. 31 is a flowchart of a subroutine of PositionTrans, FIG. 32 is an explanatory diagram of a margin on a bitmap, FIG. 33 is a block diagram of a contour coordinate generating means, FIG. 34 is a block diagram of the coordinate calculation unit, FIG. 35 is a block diagram of a sequencer of the coordinate calculation unit, FIG. 36 is a flowchart of the coordinate calculation, FIG. 37 is a state transition diagram of the coordinate calculation, and FIG. 38 is an initial value setting 39 is a timing chart for setting initial values, FIG. 40 is an explanatory diagram of Bressenham's algorithm, FIG. 41 is a state transition diagram for constant calculation, and FIGS. 42 and 43 are states for coordinate calculation. FIG. 44 is a timing chart of coordinate calculation, FIG. 45 is a state transition diagram of special processing, FIGS. 46 and 47 are timing charts of special processing, and FIG. 48 is a state transition of command transfer processing. FIG. 49 is a timing chart of a command transfer process, FIG. 50 is an explanatory diagram of signal delay, FIGS. 51 to 53 are explanatory diagrams of linear coordinate selection, and FIG. 54 is a block of a linear coordinate selection unit. Figure, Figure 55 is the state transition diagram of the linear coordinate selection unit, Figure 56 is the state transition diagram of LINE ALL, Figures 57 to 59 are the timing chart of LINE ALL, Figure 60 is the state transition diagram of LINE BFR 61 to 63 are LINE BFR timing charts, FIGS. 64 and 65 are LINE NOW state transition diagrams, FIGS. 66 to 68 are LINE NOW timing charts, and FIG. 69 is CMND / State transition diagram of ZERO, FIG. 70 is a timing chart of CMND, FIGS. 71 and 72 are timing charts of ZERO, FIG. 73 is an explanatory diagram of corner classification, FIG. 74 is a block diagram of a corner coordinate selection unit, Fig. 75 is a block diagram of the sequencer of the corner coordinate selection unit. Fig. 76 is the control signal in the PROM. Layout diagram, Fig. 77 is the state transition diagram of corner coordinate selection, Fig. 78 is the state transition diagram of CTYP1 corner process, Fig. 79 is the timing chart of CTYP1 corner process, Fig. 80 is the state of CTYP2 corner process FIG. 81 is a timing chart of the corner processing of CTYP3, FIG. 82 is a timing chart of the corner processing of CTYP3, FIG. 83 is a timing chart of the corner processing of CTYP3, and FIG. 84 is a state of the corner processing of CTYP4. 85 and 86 are timing charts of corner processing of CTYP4, FIG. 87 is a state transition chart of corner processing of CTYP5, FIG. 88 is a timing chart of corner processing of CTYP5, and FIG. 89 is CTYP6. State transition diagram of corner processing, Fig. 90 is timing chart of CTYP6 corner processing, Fig. 91 is state transition diagram of CTYP7 command processing, Fig. 92 is timing chart of CTYP7 command processing, Fig. 93 is linear processing State transition diagram Fig. 94 is a timing chart for linear processing (LINE ALL), Fig. 95 is a timing chart for linear processing (LINE BFR), Fig. 96 is a timing chart for linear processing (LINE NOW), and Fig. 97 is contour coordinate generation means. FIG. 98 is a timing chart of contour coordinate generation processing, FIGS. 99 and 100 are explanatory diagrams of sorting, FIG. 101 is a block diagram of a sorting means, and FIGS. 102 and 103 are timings of sorting. Charts, FIGS. 104 to 107 are explanatory diagrams of bitmaps, FIG. 108 is a block diagram of drawing means, FIG. 109 is a diagram illustrating the format of drawing data, FIG. 110 is a diagram illustrating the format of drawing commands, FIG. 111 is an explanatory diagram of a drawing process, FIG. 112 is an explanatory diagram of a format of a drawing address and a bit pattern, FIG. 113 is an explanatory diagram of a bit pattern ROM, FIG. 114 is an explanatory diagram of a ROM MODE, and FIG. Texture Illustration of turn ROM, Fig. 116 explanation of texture pattern, Fig. 117 explanation of standard OR mode, Fig. 118 explanation of reverse AND mode, Fig. 119 explanation of format of RG CONTROL COMMAND Fig. 120 is an explanatory diagram of RG STATUS format, Fig. 121 is an explanatory diagram of MAILBOX format, Fig. 122 is a timing chart of drawing system, Fig. 123 is a timing chart of bit pattern generation, Fig. 124 is 5 is a timing chart of reading and writing. 1 ... editor 2 ... CE system hardware 3 ... laser beam printer 4 ... CPU 5 ... DSP external interface bus 6 ... VME bus 11 ... CPU 12 ... hard disk 13 ... VRAM 14 ... RAM disk 15 ... Coordinate conversion means 21 ... Contour coordinate generation means 22 ... Sort means 23 ... Drawing means 24 ... Bitmap 31 ... Input control 32 ... Coordinate calculation unit 33 ... Linear coordinate selection unit 34 ... Corner Coordinate selection section 35 Output control

Continuation of front page (56) References JP-A-1-166275 (JP, A) JP-A-62-42273 (JP, A) JP-A-63-318686 (JP, A) JP-A-62-200473 (JP, A) JP-A-62-115580 (JP, A) JP-A-63-4380 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 5/24 G09G 5/36 G06T 11/00 G06T 11/40 B41J 2/485

Claims (2)

(57) [Claims] A first storage unit for storing outline data of a character having a plurality of line segments; and a coordinate axis parallel to a drawing direction based on the outline data read from the first storage unit. Generating the coordinates of the contour points corresponding to the line segments in the two-dimensional coordinates, selecting an even number of the contour points in each of a plurality of lines parallel to the drawing direction, and starting and ending the drawing position Contour coordinates generating means for outputting as drawing points defining the following, and the drawing points obtained from the contour coordinate generating means are rearranged along the drawing direction in each line, and further along the direction in which a plurality of lines are arranged. Sorting means for rearranging in order, and drawing from the odd-numbered drawing points to the even-numbered drawing points for each line based on the coordinates of the drawing points rearranged by the sorting means. Drawing means, and a second storage means on which the character is drawn by the drawing means, wherein the outline coordinate generation means calculates the coordinates of the outline point in the two-dimensional coordinates based on the outline data by a line segment. A coordinate calculation unit for calculating and outputting each line, and from the contour points calculated for each line segment by the coordinate calculation unit, each line segment is selected based on a predetermined algorithm and output as the drawing point. A first coordinate selection unit; the contour points calculated for each line segment by the coordinate calculation unit so that the drawing points are an even number in each of the plurality of lines; A high-quality character generation device, comprising: a second coordinate selection unit that selects and outputs zero, one, or two drawing points from the intersections. 2. A first selection process in which the second coordinate selection unit selects one intersection as one drawing point.
A second selecting one of the intersection points as two of the drawing points;
A third selection process that does not select the intersection as the drawing point, and a third selection process that selects, as the drawing point, a contour point on the line segment having the intersection that is different from the intersection. 2. The high-quality character generating apparatus according to claim 1, wherein any one of the four selection processes and the four selection processes is performed.