JP2842335B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a video signal processing apparatus for processing a television video signal in which signals of different types such as NTSC and EDTV-2 are mixed.

[0002]

2. Description of the Related Art A 16: 9 wide aspect ratio video signal system including a high-quality information signal can be transmitted and received together with a signal of the current 4: 3 aspect ratio NTSC system. A certain EDTV-2 system has been studied, and the result of the study was reported to the Ministry of Posts and Telecommunications on January 23, 1995, and commercialization is scheduled for July of the same year.

In the EDTV-2 system, a letterbox format is adopted, and a current receiver receives a broadcast signal of an EDTV image having an aspect ratio of 16: 9 according to the current NTSC system having an aspect ratio of 4: 3. Has 30 non-image portions per field at the top and bottom, respectively, and has 180 aspect ratios per field at the center of the screen.
Nine main picture images are allocated.

Further, a horizontal resolution enhancement signal (hereinafter, HH signal) is superimposed on the main picture area by frequency multiplexing, and two types of vertical resolution enhancement signals are multiplexed on the upper and lower non-picture areas. An identification control signal indicating the signal state of the EDTV-2 signal is arranged before the line. The display scanning is performed by a non-interlace method.

A video signal processing apparatus compatible with the EDTV-2 signal and the current NTSC signal reproduces a horizontal and vertical resolution enhancement signal based on the information of the discrimination control signal in the signal, thereby achieving higher image quality than the current NTSC signal. It is possible to realize a 16: 9 wide aspect ratio at the same time as providing an excellent image.

[0006] Further, the EDTV-2 signal includes a simple EDTV signal which does not include a vertical resolution enhancement signal.

[0007] As one specification of the video signal processing apparatus compatible with the EDTV-2 / NTSC signal, as for the EDTV-2 signal input, for a still image, a luminance signal obtained by widening the bandwidth by three-dimensional Y / C separation and reproduction of the HH signal ( A wide-band luminance signal) and a color signal are output, two-dimensional Y / C separation is performed for a moving image, and three-dimensional Y / C is input for an NTSC signal input.
Simple EDTV that outputs luminance signal and color signal by separation
/ NTSC decoder is assumed. In the case of the EDTV-2 signal input, since the reproduction of the vertical resolution enhancement signal is not performed, the characteristics correspond to the simple EDTV signal reception.

It is important to reduce the price of this kind of simplified EDTV / NTSC decoder in order to spread a high-definition television compatible with EDTV-2 signals in the future. One of the important factors in the price of the decoder is the capacity of the field memory. Reduction of the memory capacity, that is, how to realize the decoder with a small memory capacity is a major issue.

Referring to FIG. 7, which shows a block diagram of a first conventional video signal processing device which is the above-described simplified EDTV / NTSC decoder, this conventional video signal processing device converts an input video signal VI from analog to digital and converts it into a digital signal. An AD converter 1 for outputting a video signal a, a field memory unit 2 for storing the digital video signal a for four fields and outputting delayed signals be, and an image having a small correlation between fields in response to the supply of the signal a Two-dimensional Y for separating the luminance (Y) signal f and the color (C) signal g when the movement of
A C separation circuit 3, a Y separation circuit 4 for separating the Y signal h of the still image portion in response to the supply of the signal b, and a C separation circuit for separating the C signal i of the still image portion in response to the supply of the signal c Circuit 5
HH that separates the HH signal j in response to the supply of the signal d
In response to the supply of the signal e, the separation circuit 6 determines whether the processing target frame is a still image or a moving image, and determines a determination signal k.
, A HH reproduction circuit 8 that reproduces an HH image in response to the supply of the HH signal j and outputs a high-frequency luminance (HHY) signal m, and a signal f in response to the supply of the signal k. , H and outputs a signal 1 and a selector 9 which selects one of the signals g and i and outputs a digital color signal CD in response to the supply of the signal k. The circuit includes a selector 10, a selector 11 for disconnecting the signal m in response to the supply of the signal k, and an adding circuit 12 for adding the signals l and n and outputting a digital luminance signal YD.

Next, the operation of the first conventional video signal processing apparatus will be described with reference to FIG.
Is an input video signal VI of an NTSC signal or an EDTV signal.
Is converted into a digital video signal a and supplied to the two-dimensional YC separation circuit 3 and the field memory unit 2.

Referring to FIG. 8 showing the configuration of the field memory unit 2, the field memory unit 2 is configured to directly transmit the signal b
a and six serially connected memories 201, H21, 20 for outputting delayed signals b1, b2, b3, b4, b5, b6.
Each of the frame memories 201 to 204 has a memory capacity of one frame, and each of the line memories H21 and H22 has a memory capacity of one line. Therefore, the total memory capacity is about 8 Mbits for about 4 fields. .
The Y separation circuit 4 outputs a signal b (b
a, b3, b6) and the bandwidth 4.
The Y signal h of the 2 MHz still image portion is separated and output to the selector 9.

Referring to FIG. 9 showing the configuration of the Y separation circuit 4, the Y separation circuit 4 generates a signal b, that is, ba, b3,
Multiplier M for multiplying b6 by 1/4, 1/2, 1/4
41, M42, and M43 and these multipliers M41 to M43
, And outputs an Y signal h, and separates the Y signal by calculating a correlation between mutually adjacent fields.

Referring to FIG. 10A showing the configuration of the C separating circuit 5, the C separating circuit 5 outputs a signal c, ie, b
a, b1 to b6 are -−１,-／, 1 /
Multipliers M51 to M57 for multiplying by 8, 1/4, 1/8,-1/8, and-1/8, and an adder A51 that adds outputs of the multipliers M51 to M57 and outputs a C signal i. , C signals are separated by correlation by addition and subtraction between mutually adjacent fields.

FIG. 10B showing the configuration of the HH separation circuit 6.
, The HH separation circuit 6 converts the signal d, that is, ba, b1 to b6, into −1/8, ８, −1 /
Multipliers M61 to M67 that multiply by 8, 1/4,-1/8, 1/8, and 1/8, and an adder A61 that adds the outputs of the multipliers M61 to M67 and outputs an HH signal j. , The HH signal j is separated by correlating by addition and subtraction between mutually adjacent fields and lines. HH
The reproduction circuit 8 converts the frequency of the signal j to a bandwidth of 4.2 to 6M.
A high-frequency luminance signal of Hz, that is, an HHY signal m is generated.

The motion detection circuit 7 outputs a signal e, that is, a signal b.
In response to the supply of a, b3, and b6, a change in image between adjacent frames is detected, and a motion detection signal k is output.

In the still picture portion when the input video signal VI is an EDTV signal, the motion detection signal k is a value corresponding to the still picture, and the selectors 9 and 10 select the signals h and i respectively and change the signals 1 and CD. At the same time, the selector 11 is in the contact state and outputs the HHY signal m. Therefore, the adder 12 adds the signal l, that is, the Y signal i and the signal m,
A broadband luminance signal YD having a bandwidth of 6 MHz is output.

In the moving image portion in the case of the EDTV signal, the motion detection signal k has a value corresponding to the moving image, and the selectors 9 and 10 respectively select the output signals f and g of the two-dimensional YC separation circuit and output them as signals 1 and CD. I do. At this time, the selector 1
1 is turned off and the HHY signal m is not supplied to the adder 12, so that the signal f is output as it is as the signal YD.

In addition to the simple and simple EDTV / NTSC decoder described above, a standard EDTV which further includes, for example, a vertical interpolation signal reproduction function described in Japanese Patent Application Laid-Open No. 64-1387, performs scanning line interpolation and converts it into a non-interlaced scanning signal /
There is a second conventional video signal processing device that is an NTSC decoder. The field memory of the second conventional video signal processing device also uses a memory capacity of about 8 Mbits for 4 fields, similarly to the first video signal processing device.

Japanese Laid-Open Patent Application No. 4-2 for reducing the memory capacity
The conventional third video signal processing device described in Japanese Patent No. 73691 (Document 1) uses a field memory for Y / C separation in combination with a memory for storing a video signal of one field, so that one field of video data is stored. 3 in field memory
A dimension Y / C separation process is performed. That is, a field memory for storing video signals for one field and a line memory for storing video signals for one line are provided. In a normal image, three-dimensional Y / C separation and two-dimensional Y / C are performed according to a motion detection signal. Switching of C separation is performed, and in the case of a still image, the storage of the field memory is fixed (frozen), and the video signal therefrom is subjected to two-dimensional Y / C separation using the line memory.

However, in the processing using the field memory for one field, the Y / C separation is a correlation processing between only two adjacent fields, and the performance is insufficient as the three-dimensional Y / C separation processing.

[0021]

SUMMARY OF THE INVENTION The above-mentioned first and second prior arts are known.
Each of the second video signal processing devices has a drawback that the field memory requires a memory capacity of 4 fields, that is, about 8 Mbits, which causes an increase in price.

In the third conventional video signal processing apparatus which aims to reduce the memory capacity of the field memory, the Y / C separation is a correlation processing between only two adjacent fields, and the three-dimensional Y / C separation processing performance is insufficient. There was a disadvantage.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the required field memory capacity without sacrificing performance.
It is an object of the present invention to provide a video signal processing device which realizes an / NTSC decoder at low cost.

[0024]

According to the present invention, there is provided a video signal processing apparatus comprising a first aspect ratio of a display image, a first scanning mode, and a horizontal resolution enhancement signal for enhancing horizontal resolution during display. Frame / field for storing at least one frame of first and second video data obtained by digitizing the first video signal, the second aspect ratio of the display image, and the second video signal in the second scanning mode, respectively A memory means for correlating the delayed video data read from the field memory to output a wide-band luminance signal and a chrominance signal with enhanced horizontal resolution when the first video signal is input;
In the video signal processing device for outputting a luminance signal and a chrominance signal when the video signal is input, the frame / field memory means stores at least one frame of the first video data and delays the first video data by one frame. A first memory for outputting delayed video data; and a second memory for storing at least one field of the first video data and outputting second delayed video data delayed by one field. A horizontal enhancement color signal obtained by superimposing the horizontal resolution enhancement signal on the luminance signal and the color signal is extracted by a correlation operation between the first delayed video data and the first video data, and the horizontal enhancement color signal is stored in the second memory. A luminance signal separation circuit to be supplied; and the second delay in which the second memory is delayed by one field in response to the supply of the horizontal reinforcement color signal and the horizontal reinforcement color signal. Is constituted by a color signal horizontal resolution reinforcement signal separation circuit for generating said color signal horizontal resolution reinforcement signal by correlation calculation between the delay horizontal reinforcing color signal is an image data.

[0025]

FIG. 7 shows an embodiment of the present invention.
Referring to FIG. 1 in which the same components are denoted by the same characters with common characters and similarly shown in blocks, the video signal processing apparatus of the present embodiment shown in FIG. A field memory unit 22 including two field memories 221, 222 and outputting a signal group o, p, r, s having delay signals ba, bb, bc, bd, be, bf, bg as constituent elements; Two-dimensional YC separation circuit 23 that outputs Y signal u and C signal v in response to supply of signal group o composed of signals ba, bb and bc, and responds to supply of signal group p composed of delayed signals bb and bf And Y signals w, C and H
A Y separation circuit 24 that outputs an H (hereinafter, CHH) signal q;
A motion detection circuit 27 that outputs a motion detection signal k in response to the supply of a signal group s including delay signals ba, bb, bc, be, bf, and bg, and a C signal y in response to the supply of signals q and r And a CHH separation circuit 26 for outputting an HH signal z;
H that generates a broadband luminance signal m in response to the supply of signal z
The input signal u, v, w, y is selected in response to the H reproduction circuit 28 and the supply of the motion detection signal k, and the output Y signal 1 and the color signal C are selected.
D, a switch circuit 29 for outputting a signal D, an addition circuit 30 for adding a signal l and a signal m in response to the supply of the motion detection signal k to generate a signal YD, and a field memory unit. And a memory control circuit 31 that controls the memory 22.

FIG. 2 is a block diagram showing the structure of the field memory unit 22. Referring to FIG.
Is a line memory H22 for storing video signals for one line.
1 to H224, and the delay amount is controlled by the control signal MC.
The field memory 221 is switched to 523 lines in the case of NTSC and 261 lines in the case of NTSC and stores a video signal for one field, a field memory 222 with a fixed delay amount of 262 lines, and a memory control signal MC. Switch circuits S1 and S2 for controlling the switching of the NTSC / EDTV in response to the delay signals ba and b
b, bc, bd, be, bf, and bg are output.

Referring to FIG. 3A, which shows a block diagram of the configuration of the two-dimensional YC separation circuit 23, the two-dimensional YC separation circuit 23 includes a non-delayed delay signal ba and a 2H delay signal output from the frame memory unit 22. bc and adder A
231, a subtractor R231 that subtracts the output of the adder A231 from the delay signal bb, a BPF 231 that limits the band of the output signal of the subtractor R231, and generates a C signal v,
A subtractor R232 for subtracting the delayed signal bb from the C signal v to generate a signal u.

Referring to FIG. 3B, which shows a block diagram of the configuration of the Y separation circuit 24, the Y separation circuit 24 adds the delay signals bb and bf output from the frame memory unit 22 to generate a Y signal w. An adder A241 for outputting the signal and a subtractor R241 for subtracting the delayed signals bb and bf and outputting the CHH signal q are provided.

Referring to FIG. 3C, which shows a block diagram of the configuration of the CHH separation circuit 26, the CHH separation circuit 26 includes a CHH signal q output from the Y separation circuit 24 and a delay signal r of the field memory unit 22, that is, a signal bd. Adder A 261 for adding a signal q and r, and subtracter R 261 for taking the difference between signals q and r and outputting a signal z; and selectively outputting a signal q and an output of adder A 261 in correspondence with NTSC / EDTV as a C signal y. And a switch S261 for outputting as

FIG. 4 is a block diagram showing the configuration of the motion detecting circuit 27. Referring to FIG.
The circuit shown in FIG. 2 described in Japanese Patent No. 260294 (Document 2) is used, and an adder A271 that adds the delayed signals ba and bc and outputs a signal ca, and an adder that adds the signals bb and ca and outputs a signal cb. Abe 272, a subtractor R271 that subtracts the signals bb and ca and outputs a signal cc,
An adder A273 that adds bg and outputs a signal cd and an adder A27 that adds signals bf and cd and outputs a signal ce.
4, a subtractor R272 that subtracts the signals cb and ce and outputs a signal cf, and a C-component signal cg by band-limiting the signal cc.
BPF 271 for generating the signal c
A BPF 272 for generating a component signal ch, an LPF 273 for removing a high-frequency component of the signal cf to generate a signal ci,
LPF for generating signal ck by removing color components of signal cf
274, a switch S271 for cutting off the signal cg by the signal ch, and a signal ci,
and a switch S272 for outputting one of ck as a motion detection signal k.

Referring to FIG. 5A, which shows a block diagram of the configuration of the switch circuit 29, this switch circuit 29 responds to the supply of the motion detection signal k by setting either one of the signals u and w to a Y signal 1. Switch S291 for selecting and outputting
And a switch S that selects and outputs one of the signals v and y as the C signal CD in response to the supply of the motion detection signal k.
292.

FIG. 5 is a block diagram showing the configuration of the adder circuit 30.
Referring to (B), the addition circuit 30 is in contact with the EDTV, is connected to the switch S301 that passes the signal m and outputs the signal ms, and is connected in response to the supply of the motion detection signal k to pass the signal ms. switch S that outputs mt
302, and an adder A301 that adds the signals l and ms and outputs a Y signal YD.

Next, the operation of the present embodiment will be described with reference to FIGS. 1 to 5 (B).
The AD converter 1 converts the input video signal VI of the NTSC signal or the EDTV signal into a digital video signal a and supplies the digital video signal a to the field memory unit 22. Field memory unit 22
Are the delayed signals ba, bb, bc, b
d, be, bf, bg are generated, and signals ba, bb, bc are generated.
, A signal group p composed of signals bb and bf,
Signal r composed of signal bd, signals ba, bb, bc, b
A signal group s including e, bf, and bg is output. here,
The delayed signal ba is a direct output of the signal a, that is, a non-delayed signal. The delayed signals bb and bc are respectively 1 with respect to the signal ba.
This is a signal delayed by two lines. The signal bd is a signal obtained by delaying the supplied signal q for EDTV by one field, that is, 262 lines. Delay signal be
Is a signal delayed by one frame, that is, 523 lines from the signal bc. Each of the delay signals bf and bg is a signal delayed by one line and two lines, respectively, with respect to the signal be.

The two-dimensional YC separation circuit 23 receives the signals ba, bb, and bc of the delay difference of one line from each other, and the adder A 231 and the subtractor R 231 operate as a comb filter between three lines to perform subtraction. The device R231 outputs the C signal bv and supplies it to the BPF 231. The BPF 231 outputs the signal bv
Is band-limited to generate a C-component signal v of 3.58 MHz. The subtractor R232 subtracts the signal bb and the signal v to generate a Y signal u.

Next, in the Y separation circuit 24, the following correlation operation is performed utilizing the fact that the phase of the C signal and the HH signal is inverted between frames in the stationary portion of the video signal. Adder A
241 generates a Y signal w by adding the delayed signals bb and bf forming the signal group p, and the subtractor R241 generates the delayed signal b
The CHH signal q is generated by subtracting b and bf.

The CHH separation circuit 26 performs the following correlation operation by using the fact that the phase of the C signal and the HH signal is inverted between the fields in the stationary portion of the video signal, and separates them. The adder A 261 generates the C signal yE for EDTV by adding the signals q and bd (r), and the subtractor R 261 generates the HH signal z by subtracting the signals q and r. The switch S261 outputs the signal yE as the C signal y in the case of EDTV, and outputs the signal q as it is as the C signal y because the HH signal is not superimposed in the case of NTSC. As described above, the HH signal z is superimposed only in the case of EDTV. As described later, the signal q is supplied as a signal bd, that is, a signal bd, delayed by one field by the memory 222 of the field memory unit 22 at this time.

The HH reproducing circuit 28 generates a high-frequency luminance signal m by performing frequency shift of the supplied HH signal z and band limitation by a high-pass filter.

The motion detection circuit 27 discriminates between a moving image portion and a still image portion of the input video signal VI and outputs a motion signal k as described below.

As described above, the motion detection circuit 27
The signal b having a delay difference of one line
a, bb, and bc are supplied to adders A271 and A27.
2. The subtractor R271 operates as a comb filter between three lines, the adder A272 outputs a luminance signal cb, and the subtractor R271 outputs a chrominance signal cc. Similarly, adders A receive signals be, bf, and bg delayed by one frame.
273 and A274 operate as a comb filter between three lines, and the adder A274 outputs the luminance signal ce of one frame before. The subtractor R272 calculates a difference signal cf between the current field and the luminance signal cb, ce one frame before, and detects a motion signal from the difference signal cf. The BPF 271 is
3.58 MHz C-component signal c by band-limiting signal cc
g, and the BPF 272 band-limits the signal ca to generate a Y component signal ch of 3.58 MHz. LPF2
73 removes the high-frequency component of the signal cf of 5 MHz or more to generate the signal ci, and LPF274 cuts off the vicinity of 3.58 MHz or more to remove the color component of the signal cf, generates the signal ck, and switches respectively. It supplies to S272. The switch S271 inhibits the C signal component cg when the signal ch, that is, the Y component signal is large. Switch S27
Reference numeral 2 selects one of the signals ci and ck according to the C signal component cg. With such a configuration, only the Y signal components of the current signal and the signal of one frame before are extracted, and a motion signal is detected based on the difference signal. At this time, the LPF 274 removes color signal leakage in the case of non-correlation. However, since the high frequency component of the motion signal is also removed by the LPF, the motion signal of the high frequency when the horizontal stripe moves is also erased. Therefore, the signal ck is output as the signal k only when there is no Y signal component near 3.58 MHz and there is a C signal component. On the other hand, when there is no C signal component or a strong Y signal component near 3.58 MHz, the signal ci is output as the motion signal k.

In the switch circuit 29, the switch S291
Selects and outputs the Y signal w of the Y separation circuit 24 when the motion detection signal k is a still image and the Y signal u from the two-dimensional YC separation circuit 23 as the Y signal 1 when the motion detection signal k is a moving image.
The switch S292 selects and outputs the output C signal y of the Y separation circuit 24 when the motion detection signal k is a still image and the C signal v from the two-dimensional YC separation circuit 23 as the C signal CD when the motion detection signal k is a moving image.

The adder circuit 30 detects that the input video signal VI
At the time of TV, the switch S301 is turned on to pass the signal m and supply the signal ms to the switch S302. Switch S
The signal 302 is connected when the motion detection signal k is a still image, passes the signal ms, and supplies the signal mt to the adder A301.
An adder A301 adds the signals l and ms, and adds a wideband Y signal Y
D is output.

As described above, the field memory 221
Is delayed by a control signal MC from the memory control circuit.
In the case of DTV, it is switched to 523 lines, and in the case of NTSC, it is switched to 261 lines. The field memory 22
The delay amount of 2 is fixed at 262 lines. The memory capacities of these field memories 221 and 222 are 2M bits and 1M bits, respectively.

In order to realize the above-mentioned delay amount with such a small memory capacity, the memory control unit 31 controls only the effective portion of the display in addition to the switching of the delay amount and the control of the switches S221 and S222 by the control signal MC. The write / read operation of the memory is controlled to store the data. That is, enable / disable of these write / read operations is switched according to the timing of the input video signal VI.

The control timing of enable / disable of the write / read operation is determined by EDTV and NTSC.
6 (A) and 6 (B), which schematically show the respective signals, the portion of the display area indicated by hatching in FIG. 6 shows the period in which the write / read operation of the field memory is enabled.

First, in the case of the EDTV signal shown in FIG. 6A, the switches S221 and S222 are switched to the EDTV side, and at the same time, the upper and lower non-image portions 102 and 104,10
Main picture portions 103 and 107 which are video portions except for the portions 6 and 108
The write / read operation of only the effective display portion excluding the 182 pixels in the horizontal blanking period is enabled. The main signal period of the main picture units 103 and 107 is 360 per frame.
The number of horizontal pixels per line is 910.
The effective display period corresponding to the horizontal effective display portion is set to 80.
%, Assuming that the data length per pixel is 8 bits, the required memory capacity of the field memory in this case is as follows.

360 × 910 × 0.8 × 8 = 2,09
6,640 (bits) On the other hand, the capacity of a 2M-bit memory used for a normal field memory is as follows: 262,144 × 8 = 2,0
97, 152 (bits). Therefore, it can be sufficiently used as a field memory in this case.

Next, in the case of the NTSC signal of FIG. 6B, the switches S221 and S222 are switched to the NTSC side and the field memory 221 and the field memory 222 in which the delay amount is set to 261 lines are used, and 523 is used. Delay for lines. Also in this case, the write / read operation is enabled only during the effective display period of the main image sections 202 and 204 for 480 lines of one frame (2 fields). Similarly, if the horizontal effective display period is 80%, the required memory capacity of the field memory in this case is as follows.

480 × 910 × 0.8 × 8 = 2,79
5,520 (bits) This value is sufficiently smaller than the capacity of 3,145,728 (bits) of the 3M-bit memory used for a normal field memory, and thus can be used sufficiently as a field memory in this case.

[0049]

As described above, according to the video signal processing apparatus of the present invention, the frame / field memory means stores the first frame of video data and delays it by one frame; Memorize 1 field and save 1
A second memory that delays by a field and extracts a luminance signal and a horizontal reinforcing color signal by performing a correlation operation between the input video data and the delayed video data of the first field memory; A luminance signal separation circuit for supplying a color signal and a horizontal resolution enhancement signal by performing a correlation operation between the horizontal enhancement color signal and the delayed horizontal enhancement color signal from the second memory. By providing a signal separation circuit, the simplified EDTV / N
The function of the TSC decoder can be realized with a memory capacity of 3 Mbits, which has the effect of reducing the cost of the device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a field memory unit in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of each of a two-dimensional YC separation circuit, a Y separation circuit, and a CHH separation circuit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a motion detection circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of each of a switch circuit and an adder circuit of FIG. 1;

FIG. 6 shows the ED of the field memory according to the present embodiment.
FIG. 4 is an explanatory diagram schematically showing an enable period of each write operation for a TV / NTSC signal.

FIG. 7 is a block diagram illustrating an example of a conventional video signal processing device.

FIG. 8 is a block diagram illustrating a configuration of a field memory unit in FIG. 7;

FIG. 9 is a block diagram illustrating a configuration of a Y separation circuit in FIG. 7;

FIG. 10 is a block diagram showing a configuration of each of a C separation circuit and an HH separation circuit of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 A / D converter 2, 22 Field memory part 3, 23 2-dimensional YC separation circuit 4, 24 Y separation circuit 5 C separation circuit 6 HH separation circuit 7, 27 Motion detection circuit 8, 28 HH reproduction circuit 9-11, 29 Switch Circuits 30, 12 Addition circuit 31 Memory control circuit 201-204, 221, 222 Field memory 231, 271, 272 BPF 273, 274 LPF A231, A241, A261, A271-A274
A301 Adder R231, R232, R241, R261, R271,
R272 Subtracters H21, H22, H221 to H224 Line memories S221, S222, S261, S271, S272
S291, S292, S301, S302 switch

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 11/00-11/24 H04N 7/00-7/015 H04N 9/64-9/78

Claims (3)

(57) [Claims] 1. A first video signal including a first aspect ratio of a display image, a first scanning mode, and a horizontal resolution enhancement signal for enhancing horizontal resolution during display, and a second aspect ratio of the display image. Frame / field memory means for storing at least one frame of the first and second video data obtained by digitizing the second video signal and the second video signal in the second scanning mode, respectively. The delayed video read from the field memory is provided. A video signal processing device that performs a correlation process on data to output a broadband luminance signal and a color signal whose horizontal resolution is enhanced when the first video signal is input, and outputs a luminance signal and a color signal when the second video signal is input. The frame / field memory means stores at least one frame of the first video data and outputs first delayed video data delayed by one frame; A first memory for storing at least one field of the first video data, and a second memory for outputting second delayed video data delayed by one field, the first delayed video data Signal for extracting a luminance signal and a horizontal enhancement color signal in which the horizontal resolution enhancement signal is superimposed on the color signal by a correlation operation between the first video data and the luminance signal and supplying the horizontal enhancement color signal to the second memory A circuit for calculating a correlation between the horizontal reinforcement color signal and the delayed horizontal reinforcement color signal, which is the second delayed video data delayed by one field in the second memory in response to the supply of the horizontal reinforcement color signal. A video signal processing apparatus comprising: a color signal horizontal resolution enhancement signal separation circuit that generates a color signal and the horizontal resolution enhancement signal. 2. The method according to claim 1, wherein the first memory switches so as to provide a delay of one frame when the first video signal is input and to provide a delay of one field when the second video signal is input. Wherein the frame / field memory means is configured to: when the first video signal is input, the first memory separates the first delayed video data corresponding to the first video data into the luminance signal separation. Circuit, the second memory supplies the second video data corresponding to the horizontal enhancement color signal to the color signal horizontal resolution enhancement signal separation circuit, and the first video data is input when the second video signal is input. And a second switch unit configured to connect a memory and the second memory in series and to switch the second delayed video data corresponding to the second video data to be supplied to the luminance signal separation circuit. Video signal processing apparatus according to claim 1, wherein that. 3. The first and second memories store the first and second video data only in the first and second effective display periods corresponding to the first and second video signals, respectively. 2. The video signal processing apparatus according to claim 1, further comprising a memory control unit for controlling writing.