JP2839107B2 - Photoelectric conversion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device including a plurality of photoelectric conversion elements capable of storing photoelectrically converted charges. INDUSTRIAL APPLICATION This invention is used suitably for the photoelectric conversion apparatus used for the focus detection apparatus etc. of the passive method of a camera, for example.

[Prior Art] Conventionally, as an apparatus of this type, for example, Japanese Patent Application Laid-Open No. 1-222583 by the present applicant has already been proposed.

FIG. 14 shows an equivalent circuit diagram of the photoelectric conversion element array disclosed in Japanese Patent Laid-Open No. 1-222583.

In FIG. 14, _1-1-1 to 1- _n are storage type phototransistor arrays (cells), a common power supply is connected to the collector, and the photoelectrically converted charge is stored in the control electrode region (base). Having a structure that can be read out from the main electrode region (emitter), and its specific contents are described in, for example, JP-A-62-128678, JP-A-62-113468,
63-24664, JP-A-63-76476, JP-A-63-76582 and the like have detailed descriptions. 2 _-1 to 2 _-n are PMOS switches for resetting connected to the power supply V _c when the base of each bipolar transistor constituting the phototransistor array 1 is phi _res given, 3 _-1 to 3 _-n Represents the signal connected to each emitter of the bipolar transistor and accumulated by φ _t
NMOS switches for taking out to the subsequent stage in synchronization with, 4 _-1 to 4
_-n is an NMOS switch connected in series to each of the NMOS switches 3 _{-1 to} 3 _-n for transmitting an image signal to the read line 7. 5 _{-1 to} 5 _-n are storage capacitors for reading signals of each pixel connected between the connection points of the NMOS switches 3 _{-1 to} 3 _-n and 4 _-1 to 4- _n and the ground, and 6 is the NMOS switches 4 _-1 to 4 _-n are turned on in sequence a shift register for reading out image signals sequentially. 8 NMOS switch for initializing grounded when given a read line 7 in which the output terminal of the NMOS switches 4 _-1 to 4 _-n are connected in common with the signal phi _nrs, 9 is output to the read line 7 Output amplifier that amplifies the output image signal, 10
_-1 to 10- _n are NMOS switches for grounding the respective emitters of the phototransistor arrays _1-1 to 1- _n when _φvrs is given. Reference numeral 107 denotes a maximum / minimum value detection circuit, which includes minimum value detection circuits 11 _{-1 to} 11 _-n , maximum value detection circuits 12 _{-1 to} 12 _-n , and output amplifiers 13 and 14.

 FIG. 15 shows a configuration of one unit of the minimum value detection circuit.

As shown in FIG. 15, one minimum value detection circuit
It is composed of one differential amplifier 30 and one PNP transistor 31. The differential amplifier 30 includes a constant current circuit 411, a PMOS
It comprises transistors 407 and 408 and NMOS transistors 409 and 410. The emitter line of the PNP transistor 31 is fed back to the inverting input (I _n2 ) of the differential amplifier 30, and the non-inverting input (I _n1 )
Is input to each emitter of each pixel column of the phototransistor arrays _1-1 to 1- _n . When the level of the non-inverting input (I _n1 ) of the differential amplifier 30 is higher than the level of the inverting input (I _n2 ), the base potential of the PNP transistor 31 is displaced almost to the power supply voltage level, and the PNP transistor 31 is turned off. Let it. Therefore, no voltage is generated at the input of the output amplifier 13 shown in FIG. The output voltage of the PNP transistor 31 is generated by the non-inverting input (I
_This is the case where the lowest voltage is applied to _n1 ), and the minimum value is detected.

 FIG. 16 shows a configuration of one unit of the maximum value detection circuit.

As shown in FIG. 16, one maximum value detection circuit
It is composed of one differential amplifier 32 and one NPN transistor 33. The differential amplifier 32 includes a constant current circuit 401, a PMOS
Transistors 402 and 403, and NMOS transistors 404 and 405. The emitter line of the NPN transistor 33 is fed back to the inverting input (I _n2 ) of the differential amplifier 32 to be an output line. Each emitter of each pixel column is connected to the non-inverting input (I _n1 ). When the non-inverting input (I _n1 ) of the differential amplifier 32 is lower than the inverting input (I _n2 ), the base potential of the NPN transistor 33 is reduced to almost the voltage level of the negative power supply, and the NPN transistor 33 is turned off. Become. The output voltage of the NPN transistor 33 is
This is the case where the highest voltage is applied to the non-inverting input (I _n1 ) of the differential amplifier 32, and the maximum value is detected. R indicates the load resistance in both the minimum value detection circuit and the maximum value detection circuit.

FIG. 17 is a timing chart for explaining the operation of the photoelectric conversion element array of FIG.

First, a reset is performed. The phi _res to the low level at time t ₁ ~t ₂ period, by turning on the PMOS switches 2 _-1 to 2 _-n, the photo transistor array (hereinafter,
Based pixel column called) 1 _-1 to 1 _-n is fixed to the potential of V _c.

Next, during the period from time t _{3 to} t ₄ , φ _vrs and φ _t are set to a high level (ON), whereby the NMOS switches 10 _-1 to 10 _{-1 are} turned on.
_-n and 3 _{-1 to} 3 _-n conduct, the storage capacitors 5 _{-1 to} 5 _-n are grounded, and the residual charges are reset. When the reset of each of the bases and the emitters of the pixel columns _1-1 to 1- _n is completed, the storage operation starts.

When the storage operation is started, the photoelectrically converted charges are stored in the pixel column _1-1.
It accumulates in ~ 1 _-n base regions. At this time, the base and the emitter of the pixel column are floating (capacitive load state).
, And a voltage reflecting the base potential is generated at the emitter.

When sequentially reading out signals, the NMOS switches _4-1 to 4
_-n is sequentially _{turned on} by the shift register 6 and the storage capacity 5
_The signal charges stored in _{-1 to} 5- _n are read out to the readout line. Shift register 6 sequentially selects NMOS switches 4 _-1 to 4 _-n each time phi _ck is input. This NMOS switch 4 _-1
HMOS switch 8 is turned ON by φ _nrs immediately before selecting ~ 4 _-n
State, and reset the charge remaining on the read line 7.

In Japanese Patent Application No. 63-47644, a photoelectric conversion element array equipped with the above-described maximum / minimum value detection circuit is shown in FIGS.
By configuring the photoelectric conversion device as shown in Fig. 19, a method is proposed in which the accumulation time is controlled so that the difference between the pattern of the subject and the bright and dark parts is constant, and A / D conversion is performed only on the characteristic part of the pattern. Have been.

In these devices, whether or not accumulation is performed to an appropriate level is determined based on whether or not the difference between the maximum value and the minimum value of the accumulation level of the photoelectric conversion element array has reached the reference level _Vref . Reference numeral 102 denotes a differential amplifier for _calculating a difference between Vmax and _Vmin, and 103 compares the output of the differential amplifier 102 with a predetermined reference level _Vref to determine that an appropriate accumulation level has been reached. When the signal φ _{comp of the} comparator 103 is inverted, the microcomputer 104 detects that the accumulation has been performed up to the reference level, and outputs a pulse φ _t for terminating the accumulation to the photoelectric conversion element array 101. To send to. At the same time, a signal SH is sent to the storage circuit 105 to store the _Vmin level at the end of accumulation. Next, read pulses φ _ck and φ _nrs are sent, and an image (Video) signal is read from the photoelectric conversion element and A / D converted.

At this time, in the example of FIG. 18, the A / D conversion range is level-shifted according to the range of the image signal, and in the example of FIG. 19, the pixel signal is level-shifted according to the A / D conversion range. In each case, the A / D conversion is performed between the maximum value and the minimum value of the image signal.

Based on the digitized pixel signals thus obtained, JP-A-58-142306, JP-A-59-107313, JP-A-60-101513, or JP-A-63-18314. The in-focus determination can be made by performing the calculation disclosed in the above.

However, in the above-described conventional photoelectric conversion device, the maximum value and the maximum value of the image signal and the accumulation signal of the photoelectric conversion element array are output through different read circuits, so that a difference in read gain and a mismatch between the amplifiers 9, 13, and 14 are caused. causes and becomes, sometimes the actual value of the maximum value and the minimum value and V _max and V _min of the pixel signal is deviated, the difference between V _max and V _min as in the example of FIG. 11 and Figure 12 When the control of the accumulated charge is performed based on the above, there is a case where a part of the image signal exceeds the A / D conversion range.

Note that the difference in read gain occurs as follows. For example, in FIG. 14, the capacitance of the storage capacitor _5-1 is C _T1 ,
When the parasitic capacitance of the read lines 7 and C _H, when reading the emitter potential V _E1 of the phototransistor 1 _-1 to the read line 7, the output , And the gain does not become 1.

In contrast, V _min and V _max that output read by the gain 1, a deviation occurs.

To solve such a problem, the present applicant has proposed a photoelectric conversion device described in Japanese Patent Application No. 1-301818.

[Problems to be Solved by the Invention] However, the above-mentioned Japanese Patent Application No. 1-301818 has the following problems, and improvements have been desired.

That is, in the configuration in which the maximum value and the minimum value are detected and output on the same line as the image signal, the path from the light receiving element to the common output line via the readout circuit and the path from the maximum / minimum value detection circuit to the common output line If the balance with the path leading to is not properly achieved, the S / N ratio will decrease and the signal will vary greatly from bit to bit. In this case, it is not enough to simply improve the quality of the image signal itself, and it is necessary to accurately detect the maximum value / minimum value data for determining the storage time of the light receiving element, and further, to detect the maximum value / maximum value. The data must be output to the common output line without adding a noise component to the minimum value data.

In particular, recently, in a photoelectric conversion device for photometry, a configuration in which a photoelectric conversion element array is two-dimensionally arranged to sense a subject in a vertical direction and a horizontal direction is desired. As a configuration for this, a configuration in which chips of a plurality of photoelectric conversion devices are arranged vertically and horizontally is also conceivable. However, adopting such a configuration not only increases the manufacturing cost, but also may not provide a signal with a small SN ratio depending on the combination.

In particular, when a digital circuit that generates a clock signal or the like for driving the corresponding photoelectric conversion element array is arranged near the light receiving element array portion of another photoelectric conversion element array, the SN
A noticeable decrease in the ratio was observed. It is considered that noise components from the digital circuit are mixed in the photoelectric conversion signal, which is a major factor.

Further, when the light receiving element array is arranged inside and the readout circuit part is arranged outside as far as the array of the plurality of photoelectric conversion element arrays located on the end side of the chip, the remaining plurality of photoelectric conversion element arrays are arranged. Of these, the light receiving section is affected by the array inside the adjacent chip, so that accurate signal reading cannot be performed.

[Problem to be Solved by the Invention] Therefore, the present inventors combine a plurality of light receiving element array units, readout circuit units, digital circuit units, analog signal processing units, and the like so that a signal with the smallest noise and a large signal can be obtained. By finding out the configurations, and further integrating some of them and arranging them at predetermined positions on the semiconductor chip, the aim was to further reduce noise.

The configuration for solving the technical problem described above includes a light receiving element array section having a plurality of light receiving elements capable of accumulating photoelectrically converted charges, and reading a signal based on the charges photoelectrically converted by the light receiving element array section. A readout circuit unit;
Is a photoelectric conversion device in which a plurality of photoelectric conversion element arrays arranged substantially in a planar manner are two-dimensionally arranged on the same substrate, and an end of the substrate among the plurality of photoelectric conversion element arrays. The photoelectric conversion element array located on the side is arranged such that the readout circuit section of the photoelectric conversion element array faces the inside of the substrate and the light receiving element array section of the photoelectric conversion element array faces the outside of the substrate. The photoelectric conversion element arrays located on the end side of the substrate are arranged on both end sides of the substrate, and the remaining photoelectric conversion element arrays are arranged so that the light receiving element array orientations intersect therebetween. It is a photoelectric conversion device characterized by being performed.

Further, a configuration for solving the technical problem described above includes a light receiving element array section having a plurality of light receiving elements capable of storing photoelectrically converted charges, and a signal based on the charges photoelectrically converted by the light receiving element array section. A photoelectric conversion device, wherein a plurality of photoelectric conversion element arrays in which a plurality of photoelectric conversion element arrays are arranged on a same substrate in a two-dimensional manner, wherein the plurality of photoelectric conversion element arrays are arranged substantially in a plane; Of the photoelectric conversion element array located on the end side of the substrate, the readout circuit section of the photoelectric conversion element array faces the inside of the substrate and the light receiving element array section of the photoelectric conversion element array faces the outside of the substrate. And a detection circuit for detecting at least one of a maximum value and a minimum value of the electric charge accumulated in the light receiving element array unit. A photoelectric conversion device according to claim.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(Description of Configuration of Photoelectric Conversion Device) FIG. 1 is a schematic top view for explaining the configuration of a photoelectric conversion device according to the present invention.

1001, 1101, 2001, 2101, 3001, 3101, 4001, and 4101 are light receiving element arrays in the photoelectric conversion element array, 1002, 11
02, 2002, 2102, 3002, 3102, 4002, and 4102 are readout circuit units of the photoelectric conversion element array. One of the light receiving element arrays and one of the readout circuit units constitute one of the photoelectric conversion element arrays. The readout circuit section includes an NMOS switch, a storage capacitor, a maximum value detector, a minimum value detector, and the like, as described later. In the photoelectric conversion element array, two lines are arranged in the horizontal direction in the drawing in the semiconductor chip, and three lines are arranged in the upper and lower rows.
A plurality of (eight in this case) photoelectric conversion element arrays are arranged in a row. The light receiving units 1001, 1101 and 3001, 3101 are arranged at the end of the chip, and the corresponding readout circuit unit 10
02, 1102 and 3002, 3102 are arranged toward the inside of the chip, and in at least the four photoelectric conversion element arrays, light from the ends is prevented from entering the readout circuit and causing malfunction. .

Two photoelectric conversion element arrays including 1002 and 1102 are connected by a read line 5010 and output signals to the analog signal processing circuit unit 5002 through lines 5009 and 5015.

Similarly, the photoelectric conversion element array including 3002 and 3102
A line 5016 is connected by a line 5017, and a line 5015 is connected through a switch 5021.

The photoelectric conversion element array including 2002, 2102 is line 5012,
It is connected at 5014 and is connected to line 5015 via switch 5020.

Similarly, the photoelectric conversion element array including 4002 and 4102
Line 5015 via switch 5020 connected at 5011, 5013
It is connected to the.

In this way, the readout line is set to a common line via the switch with reference to 5015, and the light receiving element arrays 4001, 4101,
It is a wiring that passes through almost the center of the chip sandwiched between 2001 and 2101 and reaches the analog signal processing circuit unit 5002. Then, generation of a clock for driving each photoelectric conversion element array,
The digital circuit unit and the analog signal processing circuit unit serving as I / Os are collectively arranged at a predetermined position at the end of the chip, thereby preventing generated noise from adversely affecting the readout line.

5003, 5004, 5005, 5006 are comparators for controlling the accumulation time, 5003 corresponds to 1002, 1102, 5004 corresponds to 4002, 4102, 5005 corresponds to 2002, 21
It corresponds to 02, and 5006 corresponds to 3002 and 3102.

Reference numerals 5007 and 5008 denote pad portions having a plurality of pads for electrically connecting to the outside of the chip.

(Schematic Description of Photoelectric Conversion Element Array) FIG. 2 is a circuit diagram showing one configuration of a photoelectric conversion element array which is a characteristic part of the photoelectric conversion device of the present invention. Here, one of the eight photoelectric conversion element arrays in FIG. 1 will be described as an example.

The same components as those shown in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in the figure, the photoelectric conversion element array according to the present invention is provided with the following constituent members in addition to the conventional photoelectric conversion element array shown in FIG. 17 and 18 are the maximum value detection circuits 12 _{-1 to} 12 _-n and the minimum value detection circuits 11 _{-1 to} 11 respectively.
connected to the output of _-n in synchronization with phi _t is an NMOS switch for taking out the maximum and minimum values in the subsequent stage, 19 and 20 NMOS
NMOS switches connected in series to the switches 17 and 18 for sending the maximum value and the minimum value to the output line 7;
Reference numeral 6 denotes a storage capacitor for reading out signals of the maximum value and the minimum value connected between the connection points of the NMOS switches 17 and 18 and the NMOS switches 19 and 20 and the ground.

FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion element array.

The operation up to the start of accumulation is the same as that of the conventional photoelectric conversion element array described with reference to FIGS.

When the storage operation is started, the charge that has been photoelectrically converted becomes a pixel row _1-1.
It accumulates in the ~ 1 _-n control electrode area (base). At this time, the bases and emitters of the pixel columns _1-1 to 1- _n are floating (capacitive load state), and a voltage reflecting the base potential is generated at the emitter. Also, V _max has a pixel row of 1 _-1
And 1 maximum output corresponding to the output of _-n appear, output corresponding to the minimum output of pixel row 1 _-1 to 1 _-n appears to V _min.

At the end of the accumulation, the maximum output level at that time by a transfer pulse phi _t, minimum output level, the output level of each pixel is accumulated in the respective storage capacitors 15,16,5 _-1 ~5 _-n. At the time of reading, the NMOS switches 19, 20, 4 _-1 to 4- _n are sequentially turned on by the shift register 6, and the storage capacitors 15, 16, 5
_The signals accumulated in _{-1 to} 5- _n are read out to the readout line 7. Each time φ _ck is input, the shift register 6
The switches 19, 20, 4 _-1 to 4- _n are sequentially selected. NMOS by φ _hrs just before you select this NMOS switch 19,20,4 _-1 ~4 _-n
The switch 8 is turned on to reset the charge remaining on the read line 7.

As is clear from the above, in the present embodiment, the signals of the maximum output and the minimum output of the photoelectric conversion element array at the end of the accumulation can be read out to the same readout line through the same readout circuit as each pixel, so that the readout gain And the maximum output and the minimum output of the photoelectric conversion element array can be obtained more accurately without any influence due to the mismatch of the amplifier.

FIG. 4 and FIG. 5 are block diagrams of specific photoelectric conversion devices using the present embodiment.

4 and 5, reference numeral 101 denotes the photoelectric conversion element array shown in FIG. 2, reference numeral 102 denotes a differential amplifier for _obtaining the difference between Vmax and _Vmin, and reference numeral 103 denotes an output of the differential amplifier 102 and a predetermined value. The comparator 109 compares the reference level _Vref with the reference level _Vref, and determines that the appropriate accumulation level has been reached. 109 and 111 are storage circuits for storing the minimum and maximum signals output from the Video line, respectively. 110 is the recording circuit. A differential amplifier that takes the difference between the output of the circuit 109 and the output signal of the photoelectric conversion element array output from the Video line, 112 is a differential amplifier that takes the difference between the output of the recording circuit 111 and the output of the recording circuit 109, and 104 is a microcomputer. It is. The microcomputer has a CPU core 104a, ROM 104
b, RAM 104c, and A / D converter 104d.

In the photoelectric conversion device shown in FIG. 4, first, the microcomputer 104 outputs reset signals φ _res and φ _vrs to start accumulation. Next, the inverted signal φ of the comparator 103
received a _{comp φ t} is output to stop the accumulation. Furthermore φ
_hrs and φ _ck are output and read out. At this time, the sampling signal SH is sent from the microcomputer 104 to the storage circuit 109 at the timing of the output of the minimum value, and the minimum value is stored. The output of the photoelectric conversion element array, which is subsequently output, is A / D converted by the differential amplifier 110 in the form of a difference from the minimum value. At this time, the reference potential for A / D conversion reference
Since V _r1 is set to the ground potential and V _rh is set to V _ref , A / D conversion is performed almost between the maximum value and the minimum value of the output of the photoelectric conversion element array. Since the minimum value serving as the reference is accurately read out as compared with the conventional photoelectric conversion device shown in FIG. 11, the A / D conversion is accurately performed on the contrast portion of the subject.

In the photoelectric conversion device shown in FIG. 5, the microcomputer 104 outputs sampling signals SH1 and SH2 at the timing when the maximum value and the minimum value are output from the Video line, and determines the maximum value and the minimum value of the photoelectric conversion element array. These are stored in the storage circuits 111 and 109, respectively. The output of the photoelectric conversion element array that is subsequently output is input to the A / D converter by the differential amplifier 110 in the form of a difference from the minimum value. Then A
The reference potential _Vr1 of the / D conversion is the ground potential, but _Vrh is the difference between the maximum value and the minimum value obtained by the differential amplifier 112. V
_min value and V _max terminates the accumulation at for the maximum and minimum values of the actual photoelectric conversion element array as described above does not always accurately reflect, where V _max -V _min reaches V _ref level However, the actual signal width is not always _Vref .
Therefore, by setting the actual signal width to the A / D conversion range as in the example of the photoelectric conversion device shown in FIG. 4, the A / D conversion range can be effectively used without exceeding the A / D conversion range. Conversion can be performed.

FIG. 6 is a circuit diagram showing the structure of a second embodiment of the photoelectric conversion element array which is a feature of the photoelectric conversion device of the present invention. The same components as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The feature of this embodiment is that not only the maximum value and the minimum value of the output of the photoelectric conversion element array but also the differential amplifier 26 is used, and a difference between them is taken out and read out from the same read line as the photoelectric conversion element array. It is in the place. The operation is almost the same as that of the first embodiment, but the difference between the maximum value and the minimum value is φ _t instead of the maximum value of the output of the photoelectric conversion element array.
Is stored in the storage capacitor 21 by the shift register 6
The difference is that the data is read to the read line 7 through the NMOS switch 23.

In this case, by adopting the configuration shown in the photoelectric conversion device of FIG. 7, the same effect as that of the example shown in the photoelectric conversion device of FIG. 5 can be obtained. That is, at the timing when the difference between the maximum value and the minimum value read from the Video line and the minimum value are output, the microcomputer outputs the sampling pulses SH1 and SH2.
Are output, and the respective signals are stored in the storage circuits 113 and 109. The output of the storage circuit 113 becomes the reference potential on the high potential side at the time of A / D conversion, and the output of the photoelectric conversion element array that is subsequently output is obtained by taking the difference from the output of the storage circuit 109 by the differential amplifier 110. / D converted.

Here, the example of reading the difference between the maximum value and the minimum value of the accumulation signal of the photoelectric conversion element array has been described. However, the maximum value or the minimum value and the specific bit (For example, a light-shielded bit) and reading may be performed using the same reading system. In addition, as necessary for the processing at the subsequent stage, the data may be read by adding or multiplying by a constant without being limited to the difference.

As described above, the difference between the signal obtained from the maximum value detecting means and / or the minimum value detecting means and the accumulated signal of the photoelectric conversion element is eliminated, and the electric charge accumulated in the plurality of photoelectric conversion elements is accurately reflected. Signal can be obtained.

Further, according to the photoelectric conversion device of the present invention, it is possible to eliminate a deviation between a signal calculated based on a signal obtained from the maximum value detection unit and / or the minimum value detection unit and a storage signal of the photoelectric conversion element. Thus, it is possible to obtain a signal that accurately reflects the electric charges accumulated in the plurality of photoelectric conversion elements.

(Schematic Description of Configuration of Photoelectric Conversion Element) FIG. 8 is a schematic plan view showing a configuration of a photoelectric conversion element in a photoelectric conversion device according to the present invention. Here, one bit of the photoelectric conversion element array will be described.

FIG. 8 is a block diagram of one bit of the photoelectric conversion element of the present invention.

202 is a bipolar transistor of a light receiving element serving as a sensor, 201 is a PMOS transistor for resetting its base, and 203 is a transistor for connecting its emitter to a predetermined potential and resetting the potential due to photogenerated carriers accumulated in the base. It is an NMOS transistor. The accumulation and reset of the optical signal are performed by these three transistors.

Reference numeral 204 denotes an amplifier used as means for detecting the maximum value when a plurality of 1-bit blocks are arranged, and reference numeral 205 denotes an amplifier used as means for detecting the minimum value in the same manner. An amplifier as described in FIG. 15 and FIG. The signal generated from the light receiving element passes through these amplifiers, and the maximum value and the minimum value are detected.

206 and 207 are NMOS transistors for signal transfer, respectively, and 208 and 2
09 is a capacitive load for storing the signal, and 210 and 211 are for sequentially reading the signal loads stored in the capacitive load.
An NMOS transistor 212 is a shift register for sequentially scanning the read NMOS transistor.

Here, two MOSs for signal transfer, two capacitive loads, and two MOSs for reading are connected. Of these, 207, 209,
Numeral 211 is used for dark noise correction, and 206, 208 and 211 are used for optical signal accumulation. After being output as N output and S output, dark noise is corrected via a differential amplifier or the like.

(Description of Layer Configuration of Photoelectric Conversion Element) FIGS. 9A and 9B are schematic cross-sectional views in the AA ′ line direction for the bits of the above-described photoelectric conversion element. In FIG. 9 (A), PMs for base reset are arranged in order from the right.
OS, light receiving bipolar transistor for photoelectric conversion, NMOS for resetting the emitter, amplifier for maximum value detection,
A minimum value detection amplifier, a signal transfer NMOS, and a signal storage capacitor are provided.

Further to the left, a signal storage capacitor, a readout NMOS, and a scanning shift register are continuously arranged from the right in FIG. 9B.

Here, a cross-sectional view of one photoelectric conversion element is divided into two for convenience so as not to complicate the drawings and the description.

9 (A) and 9 (B), reference numeral 301 denotes a P-type semiconductor substrate, 302 denotes a P-buried layer containing a P-type impurity,
03 is an N-buried layer containing an N-type impurity, 304 is an N ^- epitaxial layer containing an N-type impurity (N ^- epi), 305 is a P ^- region containing a small amount of a P-type impurity, and 306 is a collector resistance. N ⁺ region for lowering the collector electrode is formed by Poshirikon 307, 308 N ⁺ region is an ohmic contact layer for electrically connecting the collector electrode 307 and the N ⁺ region, 309
P is serving as the base region of the light-receiving bipolar transistor ^-
Region, via a P ⁺ region 310 containing P-type impurities,
It is connected to the wiring 331. Reference numeral 311 denotes an N ⁺ region serving as an emitter containing an N-type impurity, which is connected to a wiring via polysilicon. The PMOS for base reset includes a P ⁺ region 312-1 connected to the P ⁻ region 309 serving as a source, a polysilicon provided as a base electrode provided through the insulating film 336, and a P ⁺ region 312- serving as a drain. And 2. Reference numeral 337 denotes an element isolation region containing an N-type impurity, and is electrically connected to the N ⁺ region 306. Emitter reset NMOS is P ^- formed in region 305 N ⁺ regions 315 and 316
And a gate electrode 317 made of polysilicon provided with an insulating layer interposed therebetween. 318 is a channel stopper containing a P-type impurity. 319 is a maximum value detection amplifier, and 320 is a minimum value detection amplifier. NMO for signal transfer
S is composed of N ⁺ regions 322 and 323 formed in the P ⁻ region 321 and a gate electrode 324 made of polysilicon disposed via an insulating layer. 325 is a P-type region serving as a channel stopper containing a P-type impurity. Storage capacity P ^-
Polysilicon electrode arranged via region 321 and insulating layer 336
The readout NMOS formed by the gate electrode 327 includes N ⁺ regions 328 and 329 formed in the P ⁻ region and a gate electrode 330 made of polysilicon disposed via an insulating layer. Reference numeral 338 denotes a P-type region serving as a channel stopper containing a P-type impurity.

An insulating layer 332 is provided between the electrodes 331, and the wiring 331 and the insulating layer 332 are covered with the insulating layer 333. Reference numeral 334 denotes a light-shielding layer which is an Al layer region provided to prevent unnecessary light (especially a region other than the sensor unit) from being irradiated with unnecessary light. Windows are formed in the light shielding layer 334 so as to correspond to the light receiving portions of the sensor.

335 is an insulating layer provided on the surface of the photoelectric conversion element as a protective layer.

(Explanation of Additional Configuration of Photoelectric Conversion Element Array) Also, 1001, 1002, 200 out of the eight photoelectric conversion element arrays
1, 2002, 3001, 3002, 4001, and 4002 are the photoelectric conversion element bits for reading the optical information and the dark component reading bits, the maximum value detection bits, and the minimum value detection bits as shown in FIG. Bits and dummy bits are provided on the array.

Also, 1101, 1102, 210 of the eight photoelectric conversion element arrays
Reference numerals 1,2102, 3101, 3102, 4101, and 4102 denote dark component readout bits, maximum value detection bits, and minimum value detection bits as shown in FIG. Bits and dummy bits are provided on the array.

FIG. 10 shows 1001, 1 of the photoelectric conversion element array of the present invention.
002, 2001, 2002, 3001, 3002, 4001, 4002. 601 is a p-ch MOS transistor for base reset, 602 is a bipolar transistor for performing photoelectric conversion as a light receiving element, and 603 is an n-ch MO for emitter reset.
S transistor, 604 is a maximum value detection circuit, 605 is a minimum value detection circuit, 606 is an n-ch MOS transistor for signal transfer, 607
Is a capacitive load for storing signal charges, 608 is an n-ch MOS transistor for sequentially reading out the charges stored in the storage capacitor, and 609 is a shift register for scanning the readout MOS. Each block of 606, 607, and 608 is composed of two components, an N component for noise correction and an S component for signal accumulation, as shown in FIG. The light receiving element 602 is 601,603
After an appropriate reset operation is performed by the MOS transistor, the optical signal is stored, and the charge generated in accordance with the irradiated light is stored in the capacitor 607 through the MOS transistor 606. When accumulation is completed, shift register 60
9 starts scanning, and the charges stored in 607 are sequentially output via 608 MOS transistors. During this time, the maximum and minimum value detection circuits 604 and 605 detect and output the maximum and minimum values from the plurality of arranged pixels. The photoelectric conversion element array is provided with dark pixels for reading dark components, minimum value detection bits, maximum value detection bits, and dummy pixels, in addition to effective pixels for reading optical information.
Among them, the dark pixel is for reading out the output in the dark, which is the reference of the optical signal output of all the pixels, and the light receiving element is shielded from light. The minimum value and maximum value detection bits are 604,
This is for reading the maximum value and the minimum value detected by 605 on the same read path as the effective pixel, and the output line of the maximum value and the minimum value is connected to the storage capacitor of 607 via the transfer MOS 606. This effect is described in detail in Japanese Patent Application No. 1-301818. The maximum value and minimum value detection bits are
With the above configuration, although not related to the output of the light receiving element, the light receiving elements 601, 602, and 603 and the resetting MOS transistors are arranged on the chip in the same manner as other pixels to ensure uniformity. The dummy pixels are provided around the effective pixels and are provided to eliminate external influences on the effective pixels.

FIG. 11 shows 110 of the photoelectric conversion element array of the present invention.
1, 1102, 2101, 2102, 3101, 3102, 4101, 4102 are shown. 501 is a p-ch MOS transistor for base reset, 502 is a bipolar transistor for performing photoelectric conversion as a light receiving element, and 503 is an n-ch for emitter reset.
MOS transistor, 504 is a maximum value detection circuit, 505 is a minimum value detection circuit, 506 is an n-ch MOS transistor for signal transfer, 5
07 is a capacitance load for accumulating signal charges, 508 is an n-ch MOS transistor for sequentially reading the charges stored in the storage capacitor, and 509 is a shift register for scanning the read MOS. As shown in FIG. 8, each of the blocks 506, 507 and 508 is composed of two components: an N component for noise correction and an S component for signal accumulation. Light receiving element 502 is 501,5
After an appropriate reset operation is performed by the MOS transistor 03, the optical signal is accumulated, and charges generated in accordance with the irradiated light are transferred to the MOS transistor 506 through the MOS transistor 506.
Stored in the capacity. When accumulation is completed, shift register
509 starts scanning, and the charges stored in 507 are sequentially output via 508 MOS transistors. During this time, 504,505
The maximum / minimum value detection circuit detects and outputs the maximum value / minimum value from a plurality of arranged pixels.

The present photoelectric conversion element array is provided with dummy pixels in addition to the effective pixels for reading out optical information. Since this array is used as a pair with the array shown in FIG. 10, the dark pixel and the maximum and minimum value detection bits are not added.

(Description of Manufacturing Method) FIGS. 12 (A) to (E) and FIGS. 13 (A) to (E) are flowcharts of an embodiment of a method for manufacturing a photoelectric conversion element array according to the present invention. The method for manufacturing the photoelectric conversion element array of the present invention will be described below with reference to these drawings.

12 (A) to (E) and FIGS. 13 (A) to (E).
9A and 9B show the manufacturing method for one bit of the photoelectric conversion element shown in FIGS. 9A and 9B, respectively, and are denoted by the same reference numerals as FIGS. 9A and 9B.

In the present invention, a bipolar NPN transistor as a light receiving element, a MOS FET as a transfer reset transistor,
In addition, since it is necessary to form the maximum value / minimum value detection circuit, analog signal processing circuit, digital circuit, etc. on the same chip, each element is monolithically integrated on the Si substrate using the so-called Bi-CMOS process technology. doing.

First, as shown in FIGS. 12 (A) and 13 (A), N-type and P-type buried layers 303 and 302 are formed on a P-type Si substrate 301 by using an ion implantation technique and a diffusion technique. As is used as an impurity for the N-type buried layer, and B is used for the P-type buried layer.

Next, as shown in FIGS. 12 (B) and 13 (B), the N-type epitaxial layer 304 is formed by an epitaxial growth technique.
Is formed, and P ⁻ (P well) region 30 is formed by ion implantation of B.
5 and an N ⁺ region 306 is formed by ion implantation of P. this
The N ⁺ region 306 is formed mainly to reduce the collector resistance of the NPN transistor. Next, a field insulating film layer 336 is formed by selective oxidation. Thereafter, a P region 318 is formed by B ion implantation and an N region 337 is formed by P ion implantation. This is generally called a channel stop, which prevents a parasitic transistor from being formed in an isolation region between elements. Next, FIG. 12 (C) and FIG.
As shown in FIG. 13C, a P-type region 309 is formed by implanting B ions. This is used as the base of the NPN transistor and also as the light receiving part of the sensor.

Next, as shown in FIGS. 12 (D) and 13 (D), polysilicon is deposited and patterned to form an emitter electrode of an NPN transistor and a gate electrode 313 of a MOS transistor. Also, this polysilicon electrode
It is also used as a diffusion source for N-type diffusion, and P is used as an impurity for contacting the collector electrode 307 of the NPN transistor. Next, by ion-implanting As, N
P type regions 310, 312-1 and 312-2 are formed by implanting B ions into the type regions 315 and 318. N-type region 315,318
Are used as source / drain regions of an n-ch MOS transistor. P-type regions 309, 310, 312-2 are p-ch MO
Used as source / drain region of S transistor. The P-type region 310 is also used as a contact for a base electrode of the NPN transistor.

Next, as shown in FIGS. 12 (E) and 13 (E), an insulating film 332 is deposited, a contact hole is formed by patterning, Al is further deposited, patterned, and etched to form an Al wiring 331. To form This is used for interconnection between elements. Next, an insulating film 333 is further deposited, Al is deposited thereon, patterned, and etched to form an Al region 334. This is mainly used as a light-shielding film for preventing light from hitting other than the sensor light receiving portion. Although not shown in this figure, a contact hole is formed in the insulating film 333 to conduct with the underlying Al wiring, and the Al layer 334 used as the light shielding film is used as a second Al wiring layer. Can also. After that, PSG (phosphorus glass), SiN (silicon nitride film), etc. are formed as a sticking film on the uppermost portion, and all the steps are completed.

Although not described above, the polysilicon layer is also used as a wiring between elements or an electrode of a capacitor.

High resistance regions such as the P-type regions 305 and 321 are frequently used as resistors in analog processing circuits and the like.

Note that, here, the Al light-shielding film only shows a portion that defines the opening of the light receiving element that largely depends on the photoelectric conversion operation.
Similarly, use the same process to shield other circuits from light.
A film may be formed, or a light-shielding film of an organic material or an inorganic material may be further provided at a desired portion on the upper insulating film.
According to the embodiment described above, in addition to the characteristic operation and effect described below, the following operation and effect can be obtained.

That is, since the signal output lines from the respective photoelectric conversion element arrays are finally connected to the common signal lines that are wired so as to pass through the gaps that are the cross portions of the four central arrays, these are connected via switches. The signal output line and the common signal line can be shortened to reduce the probability of noise and reduce the CR constant to prevent signal delay and S / N ratio reduction.

[Effects of the Invention] According to the present invention, a plurality of photoelectric conversion element arrays two-dimensionally arranged monolithically, which are located on the end side of the substrate, are placed on the end side of the substrate and the light receiving element array is placed on the inside. The following effects can be obtained by monolithically arranging them in such a direction as to be a readout circuit.

(1) Interaction with a photoelectric conversion element located further inside the substrate (for example, crosstalk and stray light components) as compared with the case where a readout circuit is provided on the outside and a light receiving element is provided on the inside, which is opposite to that of the present invention. Malfunction).

In addition, the common line of the output signal from each photoelectric conversion element array is shortened, and the signal delay and the decrease in the SN ratio are reduced.

(2) Even if the arrangement of the light receiving element array is determined for distance measurement, the read circuits are densely arranged, so that the area of the semiconductor substrate is reduced and the manufacturing cost is reduced.

(3) Since the light-shielding layer of the readout circuit in the photoelectric conversion element array located at the end of the substrate can be formed integrally with the light-shielding layer of the photoelectric conversion element array located on the inner side, the degree of freedom of design increases and the manufacturing cost is reduced. The result was also reflected.

[Brief description of the drawings]

FIG. 1 is a schematic top view showing the configuration and arrangement of the photoelectric conversion device of the present invention. FIG. 2 is a circuit diagram showing a configuration of a first embodiment of a photoelectric conversion element array which is a characteristic part of the photoelectric conversion device of the present invention. FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion element of the first embodiment. FIG. 4 and FIG.
FIG. 3 is a block diagram of a specific photoelectric conversion device using the photoelectric conversion element array of the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a second embodiment of the photoelectric conversion element array which is a feature of the photoelectric conversion device of the present invention. FIG. 7 is a block diagram of a specific photoelectric conversion device using the photoelectric conversion element array of the second embodiment. FIG. 8 is a schematic block diagram of one bit showing the configuration of the photoelectric conversion element in the photoelectric conversion device according to the present invention. FIGS. 9A and 9B are schematic cross-sectional views of one bit of a photoelectric conversion element in a photoelectric conversion device according to the present invention. FIG. 10 is a schematic plan view showing a first configuration of the photoelectric conversion array in the photoelectric conversion device of the present invention. FIG. 11 is a schematic plan view showing a second configuration of the photoelectric conversion array in the photoelectric conversion device of the present invention. FIGS. 12 (A) to (E) and FIGS. 13 (A) to (E)
4 is a flowchart of a method for manufacturing a photoelectric conversion array in the photoelectric conversion device of the present invention. FIG. 14 is an equivalent circuit diagram of the photoelectric conversion element array disclosed in Japanese Patent Application No. 63-47644. FIG. 15 is a circuit diagram showing a configuration of one unit of the minimum value detection circuit. FIG. 16 is a circuit diagram showing a configuration of one unit of a maximum value detection circuit. FIG. 17 is a timing chart for explaining the operation of the photoelectric conversion element array shown in FIG. 18 and 19 are block diagrams of specific photoelectric conversion devices using a conventional photoelectric conversion element array.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/339 H01L 27/14-27/148 H01L 29/762-29/768 H04N 5/335 G03B 13 / 00-13/36

Claims (6)

(57) [Claims] A light-receiving element array section having a plurality of light-receiving elements capable of storing photoelectrically converted charges; and a readout circuit section for reading out a signal based on the charges photoelectrically converted by the light-receiving element array section. A photoelectric conversion device in which a plurality of substantially two-dimensionally arranged photoelectric conversion element arrays are two-dimensionally arranged on the same substrate, wherein an end side of the substrate among the plurality of photoelectric conversion element arrays Is arranged such that the readout circuit section of the photoelectric conversion element array faces the inside of the substrate and the light receiving element array section of the photoelectric conversion element array faces the outside of the substrate. The photoelectric conversion element arrays located on the end side of the substrate are arranged on both end sides of the substrate, and the remaining photoelectric conversion element arrays are arranged so that the light receiving element array orientations intersect therebetween. The photoelectric conversion device characterized by being. 2. A light-receiving element array section having a plurality of light-receiving elements capable of storing photoelectrically converted electric charges, and a reading circuit section for reading out a signal based on the electric charges converted by the light-receiving element array section. A photoelectric conversion device in which a plurality of substantially two-dimensionally arranged photoelectric conversion element arrays are two-dimensionally arranged on the same substrate, wherein an end side of the substrate among the plurality of photoelectric conversion element arrays Is arranged such that the readout circuit section of the photoelectric conversion element array faces the inside of the substrate and the light receiving element array section of the photoelectric conversion element array faces the outside of the substrate. The readout circuit unit includes a detection circuit that detects at least one of a maximum value and a minimum value of the electric charge accumulated in the light receiving element array unit. 3. The readout circuit section includes a storage means for storing a signal based on the photoelectrically converted signal charge, and a transfer means for transferring the signal stored in the storage means to a common output line. The photoelectric conversion device according to claim 1 or 2, wherein: 4. The photoelectric conversion device according to claim 1, wherein reset means is provided in the charge accumulation region of the light receiving element for setting the potential of the region to a predetermined potential. apparatus. 5. A part of the plurality of photoelectric conversion element arrays is disposed on both ends of the substrate, and the other part is disposed such that the light receiving element array orientations intersect therebetween. The photoelectric conversion device according to claim 2, wherein: 6. The photoelectric conversion device according to claim 2, wherein an output signal from said detection circuit is read out through a common output line for transferring a signal based on the electric charge photoelectrically converted by each light receiving element. Conversion device.