JP2836855B2 - Test circuit for programmable logic elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a test circuit for a programmable logic device (programmable logic device (hereinafter referred to as PLD)), and particularly to a memory device which can be programmed only once, such as a plastic package product, in a PLD using an EEPROM device. Related to test circuit.

[Prior art]

FIG. 3 shows a conventional test circuit of this kind. Reference numeral 1 denotes a memory-capable AND array having, for example, a 4 × 4 line configuration. At each intersection of both lines, as shown in the enlarged view, a gate of a memory element X composed of an EPROM transistor is a vertical line. (Word line WL), and the drain of the memory element X is connected to a horizontal line (bit line BL). A test word line WL 'having a memory element X' is provided outside the word line WL of the AND array 1. Reference numeral 2 denotes an AND sense amplifier for calculating a product term for each column bit line BL in the AND array 1, and reference numeral 3 denotes an OR gate for calculating the logical sum of the outputs of the four AND sense amplifiers 2.
Reference numeral 4 denotes a word line driving circuit including an AND gate and the like, which is connected to each of the word lines WL and WL '. The signal ▲ in the word line drive circuit 4 becomes “L” at the time of a test, so that all the word lines WL of the AND array 1 become “L” and the test word line WL ′
Only “H” / depending on the state of the input terminal ATi during the test.
It becomes “L”. Each of the bit lines BL is connected to a Y gate 5 respectively.
Are connected to each other via an N-channel grounding transistor 6, and a column address selection signal is applied to the gate of each of the Y gates 5 via a column address invert decoder 7 to turn on the Y gate 5. Is grounded by the transistor 6 and becomes "L" level, and the bit line BL with the Y gate 5 turned off is released from the transistor 6. When testing the product term on one bit line BL in the AND array 1, the other three bit lines BL
The output of the product term in BL needs to be “L”. For this purpose, a signal obtained by inverting the column address selection signal used in programming by the column address invert decoder 7 is used. That is, at the time of programming, one of the output lines from the decoder 7 is set to the "H" level, but at the time of the test, the opposite is true, and only one selected output line is set to the "L" level, and the other unselected Is set to “H” level. As a result, the Y gate 5 corresponding to the selected output line outputting the "L" level is turned off, and the bit line BL is set to the "H" level. On the other hand, the Y gate 5 corresponding to the non-selected output line outputting the “H” level is turned on, and the ACT signal becomes “H”, whereby the bit line BL becomes “L” via the transistor 6. Fixed to level. By the above operation, at the time of the test, the bit line BL is sequentially selected by the column address selection signal inverted by the column address invert decoder 7, and the product term thereof is detected to measure the delay time from the input terminal to the output terminal. I do.

[Problems to be solved by the invention]

However, in the above-described test circuit, the input circuit, the output circuit, the AND sense amplifier 2, the OR gate 3, etc. can be tested by using the test memory element X '. The device X itself cannot be tested. For example, the memory element X
Source-drain current Io
When n is abnormally small, the delay time when accessing the bit line BL including the memory element is delayed, but it is not possible to specify which memory element is defective. SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-described problem, and has as its object to provide a test circuit capable of testing a memory element in an AND array actually used.

[Means for Solving the Problems]

A test circuit for a PLD according to the present invention is a circuit for testing the operation or the input / output delay time of each memory element in the PLD in an unprogrammed state, wherein a word line for data writing and each are connected to an OR gate. An AND array comprising a matrix circuit of bit lines and having a memory element at the intersection of the two lines, an unselected bit line is set to L level by grounding means, and one selected bit line is released from the grounding means. Column address selecting means, word line selecting means for setting an unselected word line to L level, and setting the gate of the memory element connected to the word line to L level, and selecting the selected word line to H or L by an input signal. Level and set the gate of the memory element connected to the word line to H or L level. And means for changing.

[Action]

According to the above configuration, one bit line is selected by the column address selection means and set to “H” level,
The word line selecting means turns the non-selected (other than the test target) word line to the “L” level, turns off the memory element connected to the word line, and then sets the test target word line to the “H” level. Level or “L” level to switch the memory device under test on or off,
At this time, by measuring the delay time from the input terminal to the output terminal, it can be determined whether or not the memory element is normal.

【Example】

FIG. 1 is a block diagram showing an embodiment of a test circuit according to the present invention, and the same parts as those of the conventional example of FIG. 3 are denoted by the same reference numerals. Reference numeral 11 denotes a row decode, which generates a predetermined decode signal from a row address selection signal used at the time of programming. Reference numeral 12 denotes a NAND gate. One input receives a decode output from the row decoder 11, and the other input receives a signal from a test input terminal ATi and a power supply line of N channels. The signal is input via a pass gate 13 and a P-channel pass gate 14. The ACT signal is applied to the gates of these pass gates 13 and 14. Fifteen
Is an inverter for driving each word line WL of the AND array 1. The PLD operation, the verification and the AC test require 0 V / Vcc drive, and the programming requires 0 V / Vpp drive. As shown in the circuit configuration example in the figure, Vcc /
A feedback inverter connected to a power supply AV for Vpp voltage switching is used. Each of these inverters 15 receives a signal from a test input terminal ATi via a pass gate 16 and a signal from the NAND gate 12 via a pass gate 17. An LGK signal is applied to the gate of the pass gate 16, and an inverted signal of the LGK signal is applied to the gate of the pass gate 17. Next, the operation of the test circuit having the above configuration will be described. At the time of the test, the ACT signal is set to “H” level, the product term in one bit line BL is set to “H” level, and the product term in another bit line BL is set to “L” level, as in the conventional example. Next, after setting the LGK signal to “L”, the word lines WL other than the word line WL to be inspected are set to “L” level by the decode output from the row decoder 11 based on the row address selection signal, and While the gate of the element X is set to “L” level, the word line WL to be inspected is changed to “H” level or “L” level according to the state of the test input terminal ATi, and the memory element X to be inspected is changed. Turn on or off. By this operation, a delay time or a function operation test from the test input terminal ATi to the output terminal T through the memory element X to be inspected, the AND sense amplifier 2 and the OR gate 3 can be performed.

【The invention's effect】

As described above, according to the present invention, at the time of testing a PLD, by selecting a word line in an AND array, it is possible to measure the input / output delay time of each memory element. Defective memory elements can be detected without programming.
Until now, defective products that are detected only after programmed by the user after shipment from the manufacturer can be detected before shipment from the manufacturer, and quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the PLD test circuit of the present invention, FIG. 2 is a circuit diagram showing an example of the feedback inverter in FIG. 1, and FIG. 3 is an example of a conventional PLD test circuit. It is a block diagram. DESCRIPTION OF SYMBOLS 1 ... And array, 2 ... And sense amplifier, 3 ... OR gate, 4 ... Word line drive circuit, 5 ... Y gate, 6 ... Transistor, 7 ... Column address invert decoder, X ... Memory element , 11 ... row decoder, 12 ... NAND gate, 13, 14, 16, 17 ... pass gate, 15 ... inverter.

Claims (1)

(57) [Claims] 1. A circuit for testing an operation or an input / output delay time of a programmable logic element without programming each memory element in the programmable logic element, comprising: a word line for writing data; Consisting of a matrix circuit of bit lines connected to
An AND array having a memory element at the intersection of both lines, a column address selecting means for setting a non-selected bit line to L level by grounding means and releasing one selected bit line from the grounding means, And a word line selecting means for setting the gate of the memory element connected to the word line to the L level, and switching the selected word line to the H or L level by an input signal. Means for changing the gate of the connected memory element to an H or L level. A test circuit for a programmable logic element, comprising: