JP2836245B2 - In-chip clock synchronization method - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application fields Problems to be solved by the prior art and the invention Means to solve the problem Action Embodiment Effects of the invention [Overview] Consists of a plurality of chips In a device, a basic clock (CLK) is distributed to each chip, and in each chip, the distributed basic clock (CLK) is divided to operate as an intra-chip clock (CLK1). When synchronizing the frequency-divided clock (CLK1) in the external device based on the externally frequency-divided clock (CLK2), the reset signal (RESE) synchronized with the external frequency-divided clock (CLK2)
T) to release the clock (CLK
Regarding the synchronization method for setting 1) to a specific phase state, even if the frequency of the basic clock (CLK) is improved, the clock (CLK1) in each chip is accurately synchronized to improve the system reliability. During the supply of the reset signal (RESET), a clock having a lower frequency than the basic clock (CLK) is supplied, and after the reset signal (RESET) is released, the external clock (CLK2) is supplied. Circuit means for supplying a basic clock (CLK0) that switches to the basic clock (CLK) to each chip in synchronism is provided, and the basic clock (CLKO) is supplied to each chip by the circuit means. Each chip is reset by a reset signal (RESET) having a specific phase relationship with the basic clock (CLK0) in synchronization with the circulated external clock (CLK2), and the reset signal (RESET) is released to reset the chip. Inside After locking the (CLK1) and a particular phase states, in synchronism with the frequency-divided external clock (CLK2), the clock (CLK0) above the original base clock (CL
K) and change the clock (CLK1) in each chip to
It is configured to synchronize with the divided external clock (CLK2).

[Industrial applications]

The present invention is an apparatus including a plurality of chips, and distributes a basic clock (CLK) to each chip. In each chip, the divided basic clock (CLK) is divided to generate an intra-chip clock (CLK). CLK1)
When synchronizing the divided clock (CLK1) in each chip based on the externally divided clock (CLK2), a reset signal (RESET) synchronized with the externally divided clock (CLK2) In order to make the intra-chip clock (CLK1) a specific phase state by canceling the clock signal.

In a device composed of a plurality of chips, such as a microcomputer, a central processing unit (CPU),
Chips such as a control memory (ROM), a main storage device (MS), and an input / output control device (IOC) are mounted on, for example, a printed board, and each chip receives, for example, a 40 MHz basic clock (CLK). Supply and in each chip, for example, 2
Generates an internal clock (CLK1) divided to 0 MHz,
Build a MHz microcomputer.

In this case, the divided internal clock (CL
If K1) is out of phase, the system will not operate.

Therefore, usually, outside the chip, the basic clock (CLK) is divided to generate an external clock (CLK2),
A reset signal (RESE) synchronized with the external clock (CLK2)
T), the reset signal (RESET) is input to the reset terminal of each chip, and the reset signal (RESET) is released to set the clock (CLK1) in the chip to a specific phase state. Clock in each chip (CLK1)
Synchronization is performed.

However, with the recent speedup of the basic clock (CLK),
In a system in which a reset signal (RESET) is generated based on an external clock (CLK2) generated by dividing the basic clock (CLK) and the internal clock (CLK1) of each chip is set to a specific phase state, Since it has become difficult to hold the clock (CLK2) for a certain period of time and set up the internal clock (CLK1) to a specific phase state,
It is difficult to accurately synchronize the clock (CLK1) in each chip, and even if the frequency of the basic clock (CLK) increases, the reset method can accurately synchronize the clock (CLK1) in each chip. Is becoming necessary.

[Problems to be solved by conventional technology and invention]

FIGS. 3A and 3B are diagrams for explaining a conventional method of synchronizing clocks in a chip. FIG. 3A shows a configuration example of a device including a plurality of chips, and FIG. 3B shows a configuration example of a conventional synchronization circuit. And (c) shows an operation time chart of the conventional synchronous operation.

As described above, a microcomputer or the like constructed by mounting a plurality of chips on a printed circuit board includes a central processing unit (CPU), a main storage device (MS), and a control storage device (MS) as shown in FIG. ROM), an input / output control unit (IOC) and a plurality of chips are connected via a bus.
A basic clock (CLK) of 40 MHz is distributed to each chip, and the frequency of the basic clock (CLK) is divided in each chip.
An internal clock (CLK1) is generated, and operation is performed based on the generated internal clock (CLK1).

In this case, if the phase of the internal clock (CLK1) of each chip does not match, the microcomputer does not function. Therefore, as shown in FIG. A clock (CLK2) is generated, and a reset signal (RESET) synchronized with the external clock (CLK2) is input to each chip, for example, a reset terminal (RST) of a central processing unit (CPU).
By canceling T), the phase of the frequency-divided internal clock (CLK1) in the central processing unit (CPU) is set to a specific phase state, for example, to the “0” level as shown in FIG. By doing so, it is synchronized with the divided external clock (CLK2),
A divided internal clock (CLK1) can be generated.

For this purpose, a setup time (S) for holding the reset signal (RESET) for a predetermined time (H) and then setting up the phase of the internal clock (CLK1) to a specific phase state is required. (B) At the timing shown in the figure, it is necessary to secure the hold time (H) and the setup time (S) within one cycle of the basic clock (CLK). However, as described above, for example, when the speed is increased to 40 MHz, a sufficient hold time (H) and a sufficient setup time (S) can be secured during 25 ns, which is the period of one cycle. It has become difficult.

Accordingly, there is a problem that the phase of the clock (CLK1) in the chip of the central processing unit (CPU) cannot be accurately reset to a specific phase state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and is an apparatus including a plurality of chips, in which a basic clock (CLK) is distributed to each chip, and the divided basic clock (CLK) is divided in each chip. In a system used as a clock (CLK1) in a chip, when a frequency-divided clock (CLK1) in each chip is synchronized based on an externally divided clock (CLK2), frequency division is performed externally. By releasing the reset signal (RESET) synchronized with the generated clock (CLK2), when the in-chip clock (CLK1) is brought into a specific phase state, even if the frequency of the basic clock (CLK) is improved, Another object of the present invention is to provide an intra-chip synchronization method that synchronizes a clock (CLK1) in each chip to improve system reliability.

[Means for solving the problem]

FIGS. 1A and 1B are diagrams for explaining the principle of the present invention, wherein FIG. 1A shows a principle configuration diagram, and FIG. 1B shows an operation time chart.

The above-mentioned problem is solved by the internal / external synchronization method configured as follows.

An apparatus comprising a plurality of chips, wherein a basic clock (CLK) is distributed to each chip, and each chip operates by dividing the distributed basic clock (CLK) to generate an intra-chip clock (CLK1). When the divided clock (CLK1) in each chip is synchronized based on the externally divided clock (CLK2), the reset signal synchronized with the externally divided clock (CLK2) By releasing the (RESET) signal, the internal clock (CLK1) is brought into a specific phase state by a synchronization method. While the reset signal (RESET) is being supplied, a clock having a lower frequency than the basic clock (CLK) is used. Circuit means 1 for supplying to each chip a basic clock (CLK0) that switches to the basic clock (CLK) in synchronization with the external clock (CLK2) after the reset signal (RESET) is released. 0, the basic clock (CLK0) is supplied to each chip by the circuit means 10 and is synchronized with the frequency-divided external clock (CLK2), and has a specific phase relationship with the basic clock (CLK0). Resetting each chip by a reset signal (RESET), and releasing the reset signal (RESET) to set the clock (CLK1) in the chip to a specific phase state. Then, the divided external clock (CLK2) ), The clock (CLK0) is switched to the original basic clock (CLK), and the clock (CLK1) in each chip is synchronized with the divided external clock (CLK2). I do.

[Action]

First, in a device including a plurality of chips, a basic clock (CLK) is distributed to each chip. In each chip, the distributed basic clock (CLK) is distributed to generate an intra-chip clock (CLK1). When the divided clock CLK1 in each chip is synchronized based on the externally divided clock (CLK2), the reset signal (Sync.) Is synchronized with the externally divided clock (CLK2). When the internal clock (CLK1) synchronized with the frequency-divided external clock (CLK2) is obtained by releasing the internal clock (CLK1) by releasing the RESET), the internal clock (CLK1) is brought into a specific phase state. In the present invention, the reset signal (RE
During the supply of the reset signal (RESE), a clock having a lower frequency than the basic clock (CLK), for example, a clock having the same frequency as the divided external clock is supplied.
T) is released, and after the clock (CLK1) in the chip is brought into a specific phase state, the basic clock (CLK0) that switches to the basic clock (CLK) is synchronized with the external clock (CLK2). It is intended to be supplied to a chip.

Therefore, at the timing when the reset signal (RESET) is released, since a clock whose frequency is lower than the basic clock (CLK) is supplied, the time (H) for holding the release of the reset signal (RESET), and And a clock (CLK1) divided by the release signal in the chip.
Can be set to a specific phase state, for example, a '0' state, and a sufficient time (S) can be taken, and the clock (CLK1) in the chip can be stably and accurately phase-aligned, and There is an effect that the internal clock (CLK1) can be synchronized with the divided external clock (CLK2).

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, (a) shows a configuration example of a synchronization circuit, and (b) () Shows an operation time chart at the time of synchronization.

In the present invention, a reset signal (RESET) synchronized with the external clock (CLK2) is generated based on an external clock (CLK2) obtained by externally dividing the basic clock (CLK) and supplied to each chip. During the reset period, the frequency of the basic clock (CLK) supplied to each chip is set to a low frequency, for example, a clock (CLK0) having a divided frequency, and at least after the reset signal (RESET) is released, The present invention provides a circuit means for switching the frequency of the clock (CLK0) to the original basic clock (CLK) after holding the phase of the clock (CLK1) inside each chip in a specific state, for example, the '0' state. It is a necessary means to implement. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the intra-clock synchronization method of the present invention will be described with reference to FIG. 2 while referring to FIG.

First, the basic clock (CLK) is divided by a D-type flip-flop (FF1) 1 to generate an external clock (CLK2).

The generated external clock (CLK2 *) is used as a shift clock, and D-type flip-flops (FF2) 2, (FF3) 3, (FF
4) The reset 1 signal input to the reset terminal (R) is input to the clock terminal (CK) of the shift register consisting of 4 and turned on at a certain timing.

Then, the reset 1 signal is shifted in synchronization with the external clock (CLK2 *), and FF2 Q, FF3 Q, and FF4 Q are output as shown in the time chart of FIG.

D-type flip-flop (FF3) 3 of the shift register
The negative signal (FF3 Q *) of each of the above-mentioned chips, in this embodiment, the central processing unit (CPU) 7 is reset signal (R
ESET).

Then, a logical product circuit (AND) 5 calculates the NOT signal (FF4 Q *) of the D-type flip-flop (FF4) 4 of the shift register and the D-type flip-flop (FF1) 1 (CLK2). By doing so, the D-type flip-flop (FF
4) During the period until 4 is turned on, (b) the frequency lower than the basic clock (CLK) as shown in FIG.
Specifically, the same clock signal as the frequency-divided external clock (CLK2) is output to the OR circuit (OR) 6.

In the OR circuit (OR) 6, the basic clock (CLK)
And a signal (basic clock: CLK0) obtained by logically ORing the external clock (CLK2) with the external clock (CLK2) is generated.
PU) 7 as an external clock.

In the central processing unit (CPU) 7, the external clock (CLK0) is frequency-divided by an internal frequency dividing circuit (not shown) to generate an internal clock (CLK1).

Therefore, during the period until the reset signal (RESET) is released, the frequency of the basic clock (CLK0) is divided.
When the reset signal (RESET) is released, the phase state of the internal clock (CLK1) of the central processing unit (CPU) is set up to a specific state, for example, '0' level.

In the present invention, the reset signal (RESET) is held in synchronization with the input basic clock (CLK0) (this hold period is indicated by “H”), and the internal clock (CLK1) is set to the “0” level. (This setup period is indicated by "S".) As shown in FIG. 3 (b), as shown in FIG. 3 (b), a period twice as long as the conventional method shown in FIG. 3 (for example, 50 ns). Can be used for stable setup.

At the timing when the D-type flip-flop (FF4) 4 is turned “on” after the setup is completed, the logical product condition of the logical product circuit (AND) 5 is released, and as a result, the logical sum circuit (OR) Since the output signal of (6) switches from a clock having a lower frequency than the previous basic clock (CLK) to the original basic clock (CLK), in the frequency dividing circuit of the central processing unit (CPU), an external clock (CLK) is used. CLK
In synchronization with 2), an internal clock (CLK1) obtained by dividing the basic clock (CLK) can be obtained.

As described above, according to the present invention, the reset signal (RESET) signal synchronized with the external clock (CLK2) is generated based on the external clock (CLK2) obtained by externally dividing the basic clock (CLK). During the reset period, the frequency of the basic clock (CLK) supplied to each chip is set low, for example, as a clock (CLK0) having a divided frequency, and after the reset signal (RESET) is released. At least, the phase of the clock (CLK1) inside each chip is held in a specific state, for example, a '0' state (setup)
After that, the frequency of the clock (CLK0) is switched to the original basic clock (CLK).

〔The invention's effect〕

As described above in detail, the intra-chip clock synchronization method of the present invention is an apparatus including a plurality of chips, and distributes a basic clock (CLK) to each chip. In a device that uses the divided basic clock (CLK) by dividing, the divided clock (CLK1) in each chip is externally divided (CLK2)
When the synchronization is performed on the basis of the above, the reset signal (RESET) synchronized with the externally divided clock (CLK2) is released to take a synchronization method of setting the clock (CLK1) in the chip to a specific phase state. The reset signal (RESE
T), a clock lower in frequency than the basic clock (CLK) is supplied. After the reset signal (RESET) is released, the basic clock (CLK) is synchronized with the external clock (CLK2). ), The basic clock (CLK
0) is provided to each chip, and the basic clock (CLK0) is supplied to each chip by the circuit means, and the basic clock (CLK2) is synchronized with the divided external clock (CLK2). CLK0), each chip is reset by a reset signal (RESET) having a specific phase relationship, the reset signal (RESET) is released, and the clock (C
LK1) in a specific phase state, and in synchronization with the frequency-divided external clock (CLK2), the clock (CLK0) is switched to the original basic clock (CLK), and the clock (CLK) in each chip is changed. CLK1) to the divided external clock (CL
Since the clock is synchronized with K2), even if the frequency of the basic clock (CLK) increases, the clock in the chip is stably and accurately synchronized, and the reliability of the device is improved. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a conventional method of synchronizing clocks in a chip. In the drawing, 1 to 4 are D-type flip-flops (FF1 to FF4), 5 is a logical product circuit (AND), 6 is a logical sum circuit (OR), CLK is a basic clock, CLK0 is a basic clock input to each chip, CLK1 indicates the divided internal clock in each chip, CLK2 indicates the divided external clock, and RESET indicates the reset signal sent to each chip.

Claims (1)

(57) [Claims] An apparatus comprising a plurality of chips, wherein a basic clock (CLK) is distributed to each chip, and each chip divides the distributed basic clock (CLK) to generate an intra-chip clock. In the device operating as (CLK1), when synchronizing the divided clock (CLK1) in each chip based on the externally divided clock (CLK2), the externally divided clock (CLK2) ) Is released to release the reset signal (RESET) in synchronization with the internal clock (CLK1) in a specific phase state. While the reset signal (RESET) is being supplied, the basic clock (CLK ) Is supplied, and after the reset signal (RESET) is released, the basic clock (CL) is synchronized with the frequency-divided external clock (CLK2).
Circuit means (10) for supplying a basic clock (CLK0) to be switched to K) to each chip, and supplying said basic clock (CLK0) to each chip by said circuit means (10). External clock (CLK2)
Resets each chip by a reset signal (RESET) having a specific phase relationship with the basic clock (CLK0), releases the reset signal (RESET), and specifies the clock (CLK1) in the chip Then, in synchronization with the frequency-divided external clock (CLK2), the clock (CLK0) is switched to the original basic clock (CLK), and the clock (CLK1) in each chip is An in-chip clock synchronization method, which synchronizes with a frequency-divided external clock (CLK2).