JP2836233B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2836233B2 JP2836233B2 JP2274585A JP27458590A JP2836233B2 JP 2836233 B2 JP2836233 B2 JP 2836233B2 JP 2274585 A JP2274585 A JP 2274585A JP 27458590 A JP27458590 A JP 27458590A JP 2836233 B2 JP2836233 B2 JP 2836233B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- oscillation
- circuit device
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に半導体チッ
プのレイアウト構造に関する。The present invention relates to a semiconductor integrated circuit device, and more particularly to a layout structure of a semiconductor chip.
通常この種の半導体集積回路は、トランジスタ・抵
抗，コンデンサ等を含む内部回路と、回路端子をパッケ
ージの外部に引き出す為に半導体チップの外周近傍に配
置されたボンディングパッド等から成る。Usually, this type of semiconductor integrated circuit includes an internal circuit including a transistor, a resistor, a capacitor, and the like, and bonding pads and the like arranged near the outer periphery of the semiconductor chip for drawing circuit terminals out of the package.
特に従来のコルピック型などの発振器を含有する半導
体集積回路は、第３図に示すように、内部の発振回路よ
り引き出されるピン間にはインダクタンス，コンダクタ
ンス，抵抗等の部品が接続されこれらが一体となって発
振器を構成する為、発振器から引き出されるボンディン
グパッド１及び３の配置は隣り合うように成されてい
た。In particular, in a conventional semiconductor integrated circuit including a Colpic oscillator or the like, as shown in FIG. 3, components such as inductance, conductance, and resistance are connected between pins drawn from an internal oscillation circuit, and these components are integrally formed. In order to constitute the oscillator, the bonding pads 1 and 3 drawn from the oscillator are arranged adjacent to each other.
数10MHz以下の比較的低周波数帯域での発振において
は、隣り合うピン間のアイソレーションはプラスチック
・モールド型パッケージで約25dB以上確保できる為、こ
の周波数帯域での発振を目的とした従来の発振器を内蔵
した半導体集積回路は、発振器内部に発生し、異常発振
を起こす原因となる発振信号のもれによる正帰還を防ぐ
為の特別な配慮は必要なかった。When oscillating in a relatively low frequency band of several tens of MHz or less, isolation between adjacent pins can be secured by about 25 dB or more with a plastic mold type package. The built-in semiconductor integrated circuit did not require any special consideration to prevent positive feedback due to leakage of an oscillation signal which is generated inside the oscillator and causes abnormal oscillation.
上述した従来の半導体チップに搭載されている発振用
回路の通常のレイアウトでは、回路構成上，発振回路の
ピン引き出しは隣り合うことが多くなっている。In the usual layout of the oscillation circuit mounted on the conventional semiconductor chip described above, it is often the case that the pins of the oscillation circuit are adjacent to each other due to the circuit configuration.
モールド・パッケージの場合、隣り合うピンのアイソ
レーションは数10MHzまでの比較的低周波においては25d
B以上はとれるが、数100MHz以上の高周波になるとこれ
が15dB程度まで劣化してしまう。For molded packages, isolation of adjacent pins is 25d at relatively low frequencies up to tens of MHz.
B or more can be obtained, but at high frequencies of several hundred MHz or more, this deteriorates to about 15 dB.
従って、数100MHz以上で動作する発振回路が前記のよ
うにピンの引き出しが行なわれた場合、信号のもれが正
帰還により自励発振を促すこととなる。特にこの発振周
波数がLocal周波数に近いと、正周波数近傍に妨害信号
が多数現れることになり、TVチューナの場合、画像信
号，音声信号とも乱れてしまうという欠点がある。Therefore, when the oscillation circuit operating at several hundred MHz or more pulls out the pins as described above, a signal leak promotes self-excited oscillation by positive feedback. In particular, when the oscillation frequency is close to the local frequency, many interference signals appear near the positive frequency, and in the case of a TV tuner, there is a disadvantage that both the image signal and the audio signal are disturbed.
本発明の目的は、高周波における各ピン間の信号もれ
を軽減できる半導体集積回路装置に関する。An object of the present invention relates to a semiconductor integrated circuit device that can reduce signal leakage between pins at high frequencies.
本発明の半導体集積回路装置は、発振回路を内蔵して
いる半導体集積回路装置であって、前記発振回路より外
部に引き出すボンディングパッド間に前記発振回路の動
作に影響しないボンディングパッドが少なくとも１つシ
ールド用として配置されることを特徴とする。A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a built-in oscillation circuit, wherein at least one bonding pad which does not affect the operation of the oscillation circuit is shielded between bonding pads led out from the oscillation circuit. It is characterized by being arranged for use.
次に本発明について図面を参照して説明する。第１図
は本発明の一実施例を示す回路図である。同図に示すよ
うに、発振用トランジスタ４は、ベースがバイアスされ
ると同時にボンディングパッド１に引き出されている。
コレクタはボンディングパッド３と、抵抗を介して電源
に接続されている。抵抗５は電流制限用として設けら
れ、コンデンサ６はバイパス用である。Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in the figure, the oscillation transistor 4 is drawn out to the bonding pad 1 at the same time when the base is biased.
The collector is connected to the bonding pad 3 and a power supply via a resistor. The resistor 5 is provided for current limitation, and the capacitor 6 is for bypass.
発振回路自体はボンディングパッド１と２だけ外部に
引き出せば動作させることができるが、正帰還を抑える
為に、GNDに接続したボンディングパッド２を配してい
る。本実施例では一層配線を想定している為、ボンディ
ングパッド２は、ボンディングパッド1,3の外側をまわ
る。The oscillation circuit itself can be operated by pulling out only the bonding pads 1 and 2 to the outside, but the bonding pad 2 connected to GND is arranged to suppress the positive feedback. In this embodiment, since a single-layer wiring is assumed, the bonding pad 2 goes around the outside of the bonding pads 1 and 3.
この配置により、アイソレーションはボンディングパ
ッド２がない時に比し約10dB改善される。With this arrangement, the isolation is improved by about 10 dB compared to the case where the bonding pad 2 is not provided.
第２図は本発明の第２の実施例を示す回路図である。
本実施例では、ボンディングパッド８がVCCと接続され
ており、ボンディングパッド2,3の間に挿入されてい
る。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
In this embodiment, the bonding pad 8 is connected to Vcc and is inserted between the bonding pads 2 and 3.
本実施例は二層配線を想定している為、GND,VCC配線
は、発振用トランジスタのコレクタ・ベース配線上を交
叉している。Since the present embodiment assumes a two-layer wiring, the GND and VCC wirings cross over the collector / base wiring of the oscillation transistor.
このような構成であればコレクタ・ベース間にボンデ
ィングパッドが２個装入されている為、第１の実施例よ
りさらにアイソレーションは改善され、挿入パッドがな
い時に比して約15dB改善される。With such a configuration, since two bonding pads are inserted between the collector and the base, the isolation is further improved as compared with the first embodiment, and is improved by about 15 dB compared to the case where there is no insertion pad. .
以上説明したように、本発明は、高周波発振回路より
外部に引き出されるボンディングパッドは、特に正帰還
がかかりやすいもの同志を隣り合わせることなく、間に
１つ又はそれ以上の電源又は接地用ボンディングパッド
を有する為、低周波ばかりでなく高周波においても各ピ
ン間の信号のもれが軽減される。As described above, according to the present invention, one or more power supply or ground bonding pads are provided between the bonding pads drawn out from the high-frequency oscillation circuit without adjoining ones that are particularly likely to be subjected to positive feedback. Therefore, signal leakage between pins is reduced not only at low frequencies but also at high frequencies.
間に１ピン接地ピンを挿入した場合、1GHzで約10dB,2
ピン挿入した場合約15dBアイソレーションは改善され
る。When 1 pin ground pin is inserted between them, about 10dB, 2 at 1GHz
Approximately 15dB isolation is improved when pins are inserted.
この効果により、具体的にはダウンコンバータのロー
カル回路に適用した場合、自励発振による妨害信号が消
去される為、TV信号の歪が改善される。By this effect, specifically when applied to a local circuit of a down-converter, a disturbing signal due to self-excited oscillation is eliminated, so that distortion of a TV signal is improved.
又、モールドパッケージの場合、吸湿等によるアイソ
レーションが変化する可能性があるが、これによる発振
回路への影響を小さくすることにより、信頼度を高める
効果もある。In the case of a molded package, the isolation may change due to moisture absorption or the like. However, by reducing the influence on the oscillation circuit, there is also an effect of increasing the reliability.
第１図は本発明の第１の実施例を示す回路図、第２図は
本発明の第２の実施例を示す回路図、第３図は従来の回
路レイアウトを示す回路図である。 １〜３……ボンディングパッド、４……発振用トランジ
スタ、５……電流制限用抵抗、６……バイパスコンデン
サ、７……抵抗、８……ボンディングパッド。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional circuit layout. 1-3 bonding pads, 4 oscillation transistors, 5 current limiting resistors, 6 bypass capacitors, 7 resistors, 8 bonding pads.
Claims (2)
置であって、前記発振回路より外部に引き出すボンディ
ングパッド間に前記発振回路の動作に影響しないボンデ
ィングパッドが少なくとも１つシールド用として配置さ
れることを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a built-in oscillation circuit, wherein at least one bonding pad that does not affect the operation of the oscillation circuit is disposed between the bonding pads drawn out of the oscillation circuit for shielding. A semiconductor integrated circuit device.
又は電源間のボンディングパッドであることを特徴とす
る請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein said shield bonding pad is a bonding pad between a ground and a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274585A JP2836233B2 (en) | 1990-10-12 | 1990-10-12 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274585A JP2836233B2 (en) | 1990-10-12 | 1990-10-12 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04150066A JPH04150066A (en) | 1992-05-22 |
| JP2836233B2 true JP2836233B2 (en) | 1998-12-14 |
Family
ID=17543796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2274585A Expired - Fee Related JP2836233B2 (en) | 1990-10-12 | 1990-10-12 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2836233B2 (en) |
-
1990
- 1990-10-12 JP JP2274585A patent/JP2836233B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04150066A (en) | 1992-05-22 |
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