JP2834939B2 - Power amplifier protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a power amplifier for supplying an audio signal to a speaker when an output terminal is grounded.

[0002]

2. Description of the Related Art Conventionally, a power IC has been used for amplifying a final stage of audio equipment. A pair of output transistors Q1 and Q2 connected in series as shown in FIG. Is provided. The middle point between the output transistors Q1 and Q2 is the output terminal OU.
T, which is connected to the speaker SP via an external output capacitor COUT. Therefore, the output transistors Q1, Q
By driving 2 complementarily, an AC audio signal can be supplied to the speaker SP.

In an audio device using such a power IC, if the electrical connection is incorrect, the midpoint output terminal OU
T may be connected to ground (ground fault). If such a ground fault at the output midpoint occurs during the operation of the amplifier, the transistor Q1 on the power supply side of the output stage will be destroyed. That is, in a normal amplifier, the potential of the output terminal OUT is fed back. When the potential of the output terminal OUT becomes 0 potential, a DC feedback about this occurs, and the amplifier returns the potential of the output terminal OUT to the original potential. Attempt to turn on transistor Q1 as much as possible to return. When such a direct current feedback acts, a large current flows from the power supply Vcc to the output terminal in the transistor Q1, and the transistor Q1 is destroyed. Therefore, it is necessary to provide a protection circuit for such a case.

[0004] On the other hand, in the process from IC design to completion, there is a breadboard (B / B) circuit design. This is to create a designed circuit using discrete components such as independent transistors, and to confirm this operation.

Therefore, the present inventor has created a circuit as shown in FIG. 3 on a breadboard and checked the operation. That is, a circuit in which the resistor R1 and the diodes D1 and D2 are connected in series is created between the power source + B and the ground, and a voltage equivalent to 2V _BE is created below the resistor R1. Note that the resistance R1 is set to a large resistance value and the amount of current is set small. Then, the lower side of the resistor R1 is connected to the base of the NPN transistor Q3 for detection. This transistor Q
The emitter of No. 3 is connected to the output terminal OUT via a diode D3. On the other hand, the collector of the transistor Q3 is connected to the power supply + B via the resistor R2. The lower side of the resistor R2 is the output of the detection result, and the switch SW1 is turned on and off by the potential at this point.

In such a circuit, when the output terminal OUT is grounded and the potential becomes zero, a peak current flows through the transistor Q1 instantaneously.
Is 0 V, the emitter of the transistor Q3 becomes V _BE . Since the base of the transistor Q3 is at 2V _BE , the transistor Q3 is turned on and the current flowing through R2 causes the lower potential of R2 to drop, thereby turning off the switch SW1. Thus, with such a circuit, it is possible to prevent the transistor Q1 from being destroyed when the output terminal OUT is grounded.

In the drawing, Rw is the resistance of a wire (for example, a gold wire) for connecting each element.

[0008]

However, if the above-described circuit of FIG. 3 is realized as it is on an IC, a circuit as shown in FIG. 4 is obtained. As described above, since no wires are used for connection between the elements on the IC, these connections have almost zero resistance. On the other hand, the output of the IC is performed by wire connection to the frame via the pad. Therefore, the pad P1 for the power supply + B and the frame F1 for the power supply,
The output pad P2 and the output frame F2 are connected by wires, and the ground pad P3 and the ground frame F3 are connected by wires. The other circuit configurations are exactly the same as those in FIG.

A case where an output frame is grounded in such a circuit will be described. In this case, since the potential of the output frame F2 becomes 0, a current flows toward the output frame F2 via the output transistor Q1. Since the current when this ground fault occurs flows instantaneously as a peak current, the current Icp flowing here and the pad P
2 and the resistance R due to the wire present between the frame f2
A voltage drop corresponding to _w occurs. Here, the resistance R _W of the wire is generally considered to be around 60 mΩ, and the current Icp at the time of a ground fault flowing through the transistor Q1 in the power IC that increases the output is considered to be 5 A or more. Therefore, the potential of the output pad P2 is 60 × 10 ⁻³ × 5 = 〜
0.3V.

Therefore, the emitter-side potential of the transistor Q3 is set to 1.0V by adding a voltage drop of 0.7V to the diode D3.
Becomes On the other hand, the base potential of the transistor Q3 is 2V _BE
(1.4 V), the potential difference between the base and the emitter is only 0.4 V. Therefore, the transistor Q3 cannot be turned on due to a ground fault of the output frame F2, and a current of 5 A continues to flow through the transistor Q1, which is destroyed.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a protection circuit in a power IC that can reliably turn off an output transistor when an output frame is grounded.

[0012]

According to the present invention, there is provided an integrated circuit in which a midpoint between a power-supply-side output transistor and a ground-side output transistor is connected to an output frame via an output pad. A power amplifier protection circuit for protecting the side output transistor,
A dummy pad wire-connected to the output frame;
The semiconductor device is characterized by comprising: a zero potential detecting means for detecting the zero potential of the dummy pad; and a switch for turning off the power supply side output transistor when the zero potential is detected by the zero potential detecting means.

[0013]

As described above, in the present invention, the dummy pad connected to the output frame wire is provided. Therefore, when the output frame becomes zero potential, this dummy pad immediately becomes zero potential. Therefore, the dummy pad 0
Since the switch is turned off by the zero-potential detecting means for detecting the potential, the power-supply-side output transistor can be turned off instantaneously when a ground fault occurs. Therefore, the destruction of the power supply side output transistor can be reliably prevented.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an embodiment, and the same members as those of the conventional example are denoted by the same reference numerals and description thereof will be omitted. As described above, in the circuit of this embodiment, the dummy pad P4 is separately provided, and the dummy pad P4 is connected to the frame F via the wire.
2 connected. The dummy pad P4 is connected to the emitter of the transistor Q3 via the diode D3.

Therefore, when the potential of the output frame F2 becomes 0 due to the ground fault of the output frame F2, a peak current of about 5 A flows through the transistor Q1 and the pad P
2 is the peak current times the resistance of the wire, that is, 0.
It is about 3V. However, the dummy pad P4 is
Originally, no current flows, and the potential instantaneously becomes zero due to the ground fault of the output frame F2. And pad P4 is 0
When the potential becomes the potential, the emitter side potential of the transistor Q3 becomes 1
The voltage becomes higher by V _BE , that is, 0.7 V. On the other hand, since the base potential of the transistor Q3 is maintained at 2V _BE , that is, 1.4V by the diodes D1 and D2, the transistor Q3 is turned on.

When the transistor Q3 is turned on, the switch SW1 operates to forcibly turn off the output transistor Q1. Therefore, a peak current of about 5 A flows instantaneously to the output transistor Q1 at the time of the ground fault of the output frame F2, but the transistor Q1 is quickly turned on to turn off the transistor Q1. Therefore, the destruction of the transistor Q1 can be effectively prevented. Note that the switch SW1 can be configured by, for example, an NPN transistor. That is, the transistor is normally turned on by supplying a power supply voltage to the transistor, and when the transistor Q3 is turned on, the transistor is turned off according to the voltage drop in the resistor R2, the base current supply to the transistor Q1 is cut off, and the transistor Q1 is turned off. do it.

On the other hand, the base of the transistor Q3 is connected to a resistor R1, a diode D1 and a diode D1 connected between the power supply and the ground.
2 are connected to the lower side of the resistor R1 of the series circuit. Therefore, the base of the transistor Q3 is normally at a voltage of 2V _BE . The output frame F2 oscillates around a half of the power supply voltage, and is sufficiently higher than the ground potential. Therefore, the emitter-side potential of the transistor Q3 is higher than the output-side voltage by V _BE, and the transistor Q3 does not turn on.

As described above, in this embodiment, the dummy pad P4 is provided, and this pad is connected to the output frame F2 so that the zero potential of the output frame F2 can be detected in the IC chip. Therefore, an effective protection circuit can be formed only by adding a very simple member.

[0019]

As described above, according to the power amplifier protection circuit of the present invention, the ground fault of the output frame can be effectively detected by adding the dummy pad connected to the output frame by wire. The destruction can be prevented by turning off the output transistor accordingly.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an overall configuration of an embodiment.

FIG. 2 is a circuit diagram illustrating a configuration of a conventional output stage.

FIG. 3 is a circuit diagram showing a circuit example of a related technique using a breadboard.

FIG. 4 is a circuit diagram showing a circuit example on an IC corresponding to FIG. 3;

[Explanation of symbols]

 F2 Output frame P4 Dummy pad Q3 Detection transistor

Claims (1)

(57) [Claims] 1. A power amplifier for protecting a power supply side output transistor when an output frame ground fault occurs in an integrated circuit in which an intermediate point between a power supply side output transistor and a ground side output transistor is connected to an output frame via an output pad. A dummy pad wire-connected to the output frame; zero potential detection means for detecting zero potential of the dummy pad; and a power supply side output transistor when the zero potential detection means detects the zero potential. Means for turning off a power amplifier, and a protection circuit for a power amplifier.