JP2834364B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D-RAM (Dyna).
mic Random Access Memory)
Memory cells in ROM (Read Only Memory)
ry).

[0002]

2. Description of the Related Art FIG. 19 shows an example of a memory cell array (hereinafter referred to as a memory block) 42 of a conventional D-RAM and its driving circuit. This memory block 4
2 has a sense amplifier 37, a first dummy cell 36, a second dummy cell 36, and a memory cell 34.
In the figure, 47 and 48 indicate a pair of bit lines, and 43 indicates a set of bit lines. In FIG. 19, the arrangement of the bit lines and the memory cells is a conventionally known folded bit line system, but the contents described below do not change even in a conventionally known open bit line system.

A first terminal connected to the memory cell transistor 34a side of the capacitor 34b is a data storage node, and the other second terminal 25 has a voltage of 1/2 V of the reference potential.
Set to cc.

In such a configuration, the sense amplifier 3
7, a sense amplifier drive circuit 45 is connected. The first dummy cell 36 is arranged at a portion where the first dummy word line 28 and the bit line 48 intersect, and the second dummy cell 36 is arranged at the second dummy word line 29.
And bit line 47 intersect. The first dummy word line 28 and the second dummy word line 29 receive an output signal from the dummy word line control circuit 27, and the word lines 30, 31, 32, 33,. Output signal. In addition, a column decode circuit 24, a timing pulse generation circuit 22, a bit line precharge signal generation circuit 44, and a write circuit 49 are provided as drive circuits. The operation of the above circuit element will be described below.

The timing pulse generation circuit 22 has R
AS (Row Address Strobe) signal 1
6 (active high), the timing pulse generating circuit 22 receives the RAS signal 16, and the column pulse decoding circuit 24, the sense amplifier driving circuit 45, the bit line precharge signal generating circuit 44,
Dummy word line control circuit 27 and row decode circuit 2
3 is controlled as follows.

[0006] The column decode circuit 24 outputs the column address signal 1
2 and a pulse signal from the timing pulse generation circuit 22 to decode the externally input column address, and at an appropriate timing, change the column address selection signal 46 corresponding to the externally input column address to "H" level. (= High level).

The row decode circuit 23 receives the row address signal 17 and the pulse signal from the timing pulse generation circuit 22 and decodes the row address. At an appropriate timing, the word line 30 corresponding to the row address, 3
One of 1, 32, 33,... Is selectively activated. In this example, the word lines 30, 32,... Are indicated by reference numeral 20 and the lowest row address RA0 given to the dummy word line control circuit 27 is at the "L" level (= low level =).
0 "), and the word lines 31, 33,... Are set to the" H "level (=" 1 ") when the lowest row address signal RA0 is" H "level.
Is to be selected at the time.

The sense amplifier driving circuit 45 receives a pulse signal from the timing pulse generating circuit 22 and receives an NMOS transistor 37a constituting the sense amplifier 37.
37a and the PMOS transistors 37b and 37b are driven as follows. That is, at an appropriate timing, the NMOS sense amplifier drive signal 13 applied to the NMOS transistors 37a, 37a falls from the 1/2 Vcc level to the "L" level, and the PMOS sense amplifier drive signal 14 applied to the PMOS transistors 37b, 37b changes to 1 level. It rises from the / 2Vcc level to the "H" level.

The dummy word line control circuit 27 receives the pulse signal from the timing pulse generation circuit 22 and the above-described lowest row address signal RA0 (20), and sets the lowest row address RA0 to RA0 = "L". At the level, the second
And the first dummy word line 28 rises when RA0 = "H" level.
When the first dummy word line 28 rises, the first
When the dummy cell 36 is selected and the second dummy word line 29 is activated, the second dummy cell 36 is selected. Here, the first and second dummy cells 36,
Specifically, as shown in FIG. 20, the selection of 36 is performed such that the dummy cell 36 is connected to the bit line 48 (or the bit line 47) to which the memory cell transistor 34a is not connected.

The first dummy cell 36 has the following role. That is, the noise generated on the bit line 47 through the parasitic capacitance between the gate and the source of the memory cell transistor 34a of the memory cell 34 connected to the one bit line 47 due to the rising of the word line 30 (or 32). , A second dummy word line 29 connected to a second dummy cell 36 connected to the other bit line 48
Has the role of canceling by launching

Similarly, the second dummy cell 36 has a parasitic capacitance between the gate and the source of the memory cell transistor 34a of the memory cell 34 connected to the bit line 48 when the word line 31 (or 33) rises. Through
Noise generated on the bit line 48 is transferred to the first dummy cell 36 connected to the first dummy cell 36 connected to the bit line 47.
It has a role of canceling by raising the word line 28.

Bit line precharge signal generation circuit 44
Receives the pulse signal from the timing pulse generation circuit 22 and raises the bit line precharge signal 15 to "H" level in an appropriate period, thereby pre-charging the bit lines 47 and 48 to 1/2 Vcc level. While charging, the 1/2 Vcc level is written to the capacitors 36b, 36b of the first and second dummy cells 36, 36.

The write circuit 49 includes an inverter and a NOR.
When a write enable signal (write enable signal, hereinafter referred to as WE signal, active low) 21 and input data 19 are provided,
Writing is performed on bit lines 47 and 48 selected by a column address signal 46 output from the column decode circuit 24. That is, when the “L” level WE signal 21 is given, the input data 19 is set to “H” level via the first I / O line (common data line) 50 and the second I / O line 51. If there is, "H" level and "L" level are written to the selected bit lines 47 and 48, respectively, and the input data 1
If 9 is at "L" level, the selected bit lines 47, 4
8 is written with the “L” level and the “H” level, respectively.

Next, the operation timing of the whole circuit will be described with reference to FIG. However, in the illustrated example, the word line 3
This shows a case where 0 is selected. At this time, the lowest row address signal RA0 is at RA0 = “L” level, and the dummy word line 29 rises. FIG.
In the waveforms of the bit lines 47 and 48 shown in (e) and (f), the solid line shows the case where the data of the selected memory cell 34 is at the “L” level, and the broken line shows the data of the selected memory cell 34. At the “H” level.
When the RAS signal 16 becomes active at the timing shown in FIG. 21, the bit line precharge signal 15 then falls (see FIG. 21 (b)), and subsequently, FIG.
As shown in (d), the word line 30 and the second dummy word line 29 rise.

Next, the NMOS sense amplifier drive signal 13
Falls (see FIG. 21 (h)), and the PMOS sense amplifier drive signal 14 subsequently falls. The data “1” (“H”) of the selected memory cell 34
In the case of (level), the potential of the bit line 47 rises by ΔV1 and the data of the selected memory cell 34 becomes “0” (“
L ”level), the potential of the bit line 47 is the same
Just descend. At this time, the change in the bit line potential ΔV1
Is determined by the capacity division between the bit line and the memory cell, and as is well known, ΔV1 = (１ ／) · Vcc · {CB · CS / (CB + CS)} (1)

Here, CS is the memory cell capacity, and CB is the bit line capacity. At this time, the potential of the bit line 48 connected to the bit line 47 and the common sense amplifier 37 remains at the 1/2 Vcc potential and serves as a reference (see FIG. 16).

The data write operation is performed from the time when the WE signal 21 shown in FIG. 21 (i) falls to the "L" level to the time when it rises to the "H" level. As shown, if the input data 19 applied to the write circuit 49 is at "H" level, the bit line 4
7 and 48 become “H” level and “L” level, respectively, as indicated by the alternate long and short dash line.
Is written with "H" level data.

[0018]

By the way, if the memory cell of the D-RAM as described above can be used as a ROM, a semiconductor memory device having both a ROM and a RAM as one chip can be replaced with a conventional D-RAM. There is an advantage that it can be manufactured by almost the same manufacturing process.

However, when the memory cell of the D-RAM is
At present, a semiconductor memory device that can be used as M has not been realized yet.

The present invention has been made in view of such a situation, and a completely new type of semiconductor memory in which a memory cell of a D-RAM can be used as a ROM, and the ROM and the RAM are combined into one chip. It is intended to provide a device.

Another object of the present invention is to allow a ROM memory cell and a RAM memory cell to coexist on the same bit line.
An object of the present invention is to provide a semiconductor memory device capable of performing exactly the same read operation on a memory cell.

[0022]

According to the present invention, there is provided a semiconductor memory device having a plurality of bit lines and a plurality of word lines, wherein the first terminal is a data storage node,
A capacitor having a second terminal at a first reference potential and a gate are connected to the word line, one of a source and a drain is connected to the bit line, and the other of the source and the drain is connected to the first of the capacitor. A first memory cell having a switching transistor connected to one terminal, and a gate not electrically connected to the bit line regardless of selection or non-selection of the switching transistor connected to the word line and the word line Second with capacitor
A memory cell, whereby the above object is achieved.

Preferably, the source and the drain of the switching transistor of the second memory cell are always kept off regardless of whether the word line connected to the gate is selected or not.

Also, preferably, instead of providing a switching transistor which is not always conducting, the switching transistor is omitted.

Preferably, a source and a drain of the switching transistor of the second memory cell are not electrically connected to the first terminal of the capacitor.

Preferably, a source and a drain of the switching transistor of the second memory cell are not electrically connected to the bit line.

Preferably, a precharge means for precharging the bit line connected to the first memory cell or the second memory cell to a second reference potential irrelevant to the first reference potential; Initialization means for initializing the data storage node of the capacitor of one memory cell to a third reference potential different from the second reference potential, and performing a read operation after the initialization by the initialization means is performed. In the method, the bit line potential changes when the first memory cell is selected and the bit line potential does not change when the second memory cell is selected. Preferably, there is provided a bit line potential changing means for causing a potential change of about half the potential change of the bit line by the first memory cell to the bit line.

Preferably, a protection means is provided for protecting a region where the first memory cells and the second memory cells are mixed from being written with external input data.

Preferably, the first memory cell and the second memory cell are mixed, and only the first area protected from writing of external input data by the protection means and the first memory cell are present. Then, the writable second region and the writable second region are mixed and formed on the same substrate.

Preferably, the first region is RO
The area is M, and the second area is a RAM area.

[0031]

The semiconductor memory device of the present invention has a plurality of
In a semiconductor memory device having a bit line and a plurality of word lines,
And the first terminal is a data storage node and the second terminal is
The capacitor which is the first reference potential and the gate are connected to the word.
Line and one of the source and drain is
And the other of the source and the drain is
A switching device connected to the first terminal of the capacitor;
A first memory cell having a transistor and the first memory
The third menu, in which the capacitor is omitted compared to the cell,
And the above-mentioned purpose is achieved.
Is done.

The semiconductor memory device of the present invention has a plurality of
In a semiconductor memory device having a bit line and a plurality of word lines,
And the first terminal is a data storage node and the second terminal is
The capacitor which is the first reference potential and the gate are connected to the word.
Line and one of the source and drain is
And the other of the source and the drain is
A switching device connected to the first terminal of the capacitor;
A first memory cell having a transistor and the first memory
Compared with cells, the capacitance of the capacitor is small and electrically zero.
And a third memory cell and equivalent arrangements, for precharging the bit line to which the first memory cell or said third memory cell is connected to the second reference potential independent of the first reference potential pre Charging means; and initialization means for initializing the data storage node of the capacitor of the first memory cell to a third reference potential different from the second reference potential, wherein initialization by the initialization means is performed. Then, in the read operation, by selecting the word line, the bit line potential changes when the first memory cell is selected, and the bit line potential does not change when the third memory cell is selected. >, Thereby achieving the above object.

The semiconductor memory device of the present invention has a plurality of
In a semiconductor memory device having a bit line and a plurality of word lines,
And the first terminal is a data storage node and the second terminal is
The capacitor which is the first reference potential and the gate are connected to the word.
Line and one of the source and drain is
And the other of the source and the drain is
A switching device connected to the first terminal of the capacitor;
A first memory cell having a transistor and the first memory
Compared with cells, the capacitance of the capacitor is small and electrically zero.
And a third memory cell and equivalent arrangements, Bei bit line potential changing means for causing the said bit line to about half of the potential change of the potential change of the bit line according to said first memory cell
As a result, the above object is achieved.

Further , the semiconductor memory device of the present invention has a plurality of
In a semiconductor memory device having a bit line and a plurality of word lines,
And the first terminal is a data storage node and the second terminal is
The capacitor which is the first reference potential and the gate are connected to the word.
Line and one of the source and drain is
And the other of the source and the drain is
A switching device connected to the first terminal of the capacitor;
A first memory cell having a transistor and the first memory
Compared with cells, the capacitance of the capacitor is small and electrically zero.
And a third memory cell and equivalent arrangements, contact a protection means for protecting the area where the first memory cell and said third memory cells are mixed from writing external input data
Thus, the above object is achieved.

Preferably, the first memory cell and the third memory cell are mixed, and a third region protected from writing by the protection means and only the first memory cell are present, and the writing is not performed. A possible fourth region and a possible fourth region are mixedly formed on the same substrate.

Preferably, the third region is RO
The M area and the fourth area are a RAM area.

Preferably, each area is stored in the ROM
The area and the RAM area can be arbitrarily selected.

[0039]

The data storage node of the first memory cell is initialized by the initialization means with reference to FIGS.
Initialize to a third reference potential different from the reference potential, and then
The operation will be described with reference to the semiconductor memory device according to claim 6 which performs a read operation.

Here, for example, the power supply potential Vcc may be used as the second reference potential, the GND potential (ground potential) may be used as the third reference potential, and the first reference potential may be the second reference potential and the third reference potential. Although it can be selected independently of the reference potential, in most cases, 1/2 Vcc which is an intermediate level between the second reference potential and the third reference potential is used in many cases.

Also, for example, the bit line potential changing means includes a switching transistor and a capacitor as in the first memory cell, and receives a bit line precharge signal to apply a 1/2 Vcc potential to the data storage node. Conventionally known writable dummy cells may be used (see FIG. 12C).

First, the data storage node of the first memory cell is initialized to the third reference potential GND potential. This initialization operation is performed, for example, by reading data in a normal D-RAM.
Just like the write operation of 0 "(GND potential),
This can be executed by writing data “0” to the first memory cell (see FIG. 12A). In addition, the above data
The write operation of “0” does not need to be selectively performed only on the first memory cell, and the data “0” may be written on all the first memory cells and all the second memory cells (FIG. 12). (B)).

Next, the bit line connected to the first memory cell or the second memory cell is precharged to the second reference potential by the precharge means. At the same time, 1/2 Vcc potential is written to the data storage node of the dummy cell (see FIG. 12C).

In this state, assuming that the first memory cell is selected by the word line, the data storage node of the first memory cell is electrically connected to the bit line. By the capacitance division between the bit line and the capacitor of the first memory cell, an intermediate potential between the precharge potential of the bit line, ie, the second reference potential, and the write potential of the data storage node of the first memory cell, ie, the third reference potential, is obtained. Potential.

At this time, the change in bit line potential ΔV2
Is determined by the divided capacity of the bit line and the memory cell, and ΔV2 = Vcc · {CB · CS / (CB + CS)} (2) Here, CS is the memory cell capacity, and CB is the bit line capacity (see FIG. 14A).

Further, assuming that the second memory cell is selected by the word line, in this case, the data storage node of the capacitor of the second memory cell and the bit line are not electrically connected. Therefore, the potential of the bit line remains at the precharge potential, that is, the second reference potential (see FIG. 14B).

As described above, according to the above configuration, the potential of the bit line differs between when the first memory cell is selected and when the second memory cell is selected. Therefore, in the subsequent read operation, the data of the first memory cell is determined as one of “1” and “0”, and the data of the second memory cell is determined as the other data of “1” and “0”. (Hereinafter, the data of the second memory cell is set to data “0” and the data of the second memory cell is set to data “1”).

It is also assumed that a dummy cell is selected simultaneously with the selection of the first memory cell or the second memory cell.
At this time, the potential change of the bit line to which the dummy cell is connected is ΔV2 / 2 since 1/2 Vcc potential has been written to the data storage node of the dummy cell. Therefore, by amplifying the potential difference (see FIG. 14D) between the bit line to which the first memory cell or the second memory cell is connected and the bit line (reference bit line) to which the dummy cell is connected. , The first memory cell and the second
Discrimination of data with the memory cell can be realized.

The first memory cell and the second memory cell as described above can be separately formed in a manufacturing process. Specifically, for example, if an NMOS transistor is used as a switching transistor and a conventionally known stacked capacitor is used as a capacitor, the presence or absence of a contact hole connecting the diffusion node of the NMOS transistor and the lower electrode of the stacked capacitor is determined by the presence or absence of a contact hole. The first memory cell and the second memory cell can be separately formed (see FIG. 17). The presence / absence of the contact hole, that is, data "1" and "0" can be programmed by a contact hole mask in the same manner as a conventionally known mask ROM.

Therefore, according to the semiconductor memory device of the present invention, by a manufacturing process similar to that of a conventionally known D-RAM,
The data of the memory cell can be determined to be "1" or "0". That is, according to the above configuration, the memory cells of the D-RAM can be used as the ROM.

In such a semiconductor memory device, if writing of external input data is prohibited (write protection) in a region where the first memory cell and the second memory cell are mixed, the first means is used by the initialization means. The second reference potential written to the data storage node of the memory cell does not change. Therefore, during the operation of the semiconductor memory device, the ROM data is held in a non-volatile manner without being destroyed.

As described above, the first memory cell and the second memory cell are mixed, and the area where writing is prohibited, that is, the ROM area, and only the first memory cell is present and writing is possible. If the region, that is, the RAM region is formed on the same substrate, the ROM region and the R region
A semiconductor memory in which the AM area is mixed can be realized. This image is shown in FIG.

The comparison between the read operation of the ROM and the read operation of the RAM will be described below. Now, a first memory cell in which data "0" (GND potential) has been written as external input data, and a first memory cell in which data "1" (Vcc potential) has been written as external input data. (See FIG. 13B). FIG. 15 shows the potential change of the bit line when the first memory cell in which data “0” is written as the external input data is selected.

At this time, the distinction between data "0" and data "1" can be realized by using the dummy cell shown in FIG. 12C (see FIG. 15). As is clear from comparison between FIG. 15 and FIG. 14, data “0” is used as external input data.
And the potential change of the bit line when the first memory cell (see FIG. 12A) in which data "0" is written as initialization data is selected. The potential changes are equal.

Data "1" is used as external input data.
The potential change of the bit line when the first memory cell (see FIG. 13 (b)) in which is written is selected, and the potential change of the bit line when the second memory cell (see FIG. 12 (b)) is selected. equal. In other words, the RAM memory cell (see FIG. 13A) into which the data "0" is written and the data "
A ROM memory cell of "0" (see FIG. 12A) is equivalent in a read operation, and a RAM memory cell in which data "1" is written (see FIG. 13B) and a data of "1" A ROM memory cell (see FIG. 12B) is equivalent in a read operation.

Therefore, the read operation of the ROM and the read operation of the RAM can be executed in exactly the same manner without distinction between the ROM and the RAM. This means that even when ROM and RAM are mixed on the same bit line, ROM and RA
Since this means that it is not necessary to change the read operation for M, there is a great merit that ROM and RAM can be mixed on the same bit line without complicating the configuration of the semiconductor memory device.

Further, as shown in FIG. 15, the bit line connected to the first memory cell or the second memory cell is connected to the dummy memory cell.
The potential difference from the bit line to which the cell is connected is ΔV2 / 2, which is apparent from a comparison between the above equations (1) and (2), as shown in FIG. The potential difference between the line 47 and the bit line 48 is equal to ΔV1. Therefore, in the semiconductor memory device of the present invention, if a memory cell having the same capacitor capacity as that of the conventional D-RAM is used, the conventional D-RAM can be used.
As much as the read potential difference to the bit line is obtained.
This is the same manufacturing technology as the conventional D-RAM,
There is a great merit in that a memory in which M and RAM are mixed can be manufactured.

In the above configuration, the data storage node of the capacitor of the second memory cell is not connected to the bit line, and the first memory is replaced with the first memory cell .
Compared to memory cells, the capacitance of the capacitor is smaller and electrically
The use of the third memory cell having a configuration equivalent to zero is electrically equivalent. That is, the second memory cell and the third memory cell are substantially equivalent in that the charge cannot be sufficiently stored in the data storage node or the charge is not sufficiently transmitted from the data storage node to the bit line.

Similarly, the structure of the semiconductor memory device described in claim 6 is substantially equivalent to the structure of the semiconductor memory device described in claim 12 . Claims 2 to 1
The configuration of the semiconductor memory device described in claim 0 is substantially equivalent to the configuration of the semiconductor memory device described in claim 1.

[0060]

Embodiments of the present invention will be described below.

(Embodiment 1) The semiconductor memory device of Embodiment 1 shown in FIG. 1 is a semiconductor memory device using the memory cell of the conventional D-RAM shown in FIG. 19 as a ROM.

FIG. 2 shows an example of a specific arrangement pattern of memory cells in the semiconductor memory device of FIG. FIG.
1 or the circuit configuration of FIG. 1, the timing pulse generation circuit 22, the multiplexer 18,
The portion excluding the pseudo RAS signal generation circuit 39, the timer circuit 40, the row address counter 38, and the Vcc rise detection circuit 41 can be considered as one memory block 42.

As described above, in the semiconductor memory device of the first embodiment, the first memory cell 34 and the second memory cell 35 are arranged corresponding to the ROM data to be programmed. Here, data “0” is written in the address where the first memory cell 34 is arranged, and data “1” is written in the address where the second memory cell 35 is arranged. Is written. Further, this memory block shows a case where all the memory cells are used as a ROM in which the first memory cells 34 and the second memory cells 35 are mixed. Therefore, a write protect signal (write protection signal) 219 given to the input terminal of the write circuit 49 of the first embodiment.
Is fixed at the “H” level, and is protected from data writing, that is, new data is not written. Therefore, according to the memory block 42, data can be held in a nonvolatile manner.

As described above, the semiconductor memory device of the first embodiment uses the memory cell of the conventional D-RAM shown in FIG. 19 as a ROM, and therefore most of the circuit elements shown in FIG. 1 are shown in FIG. The circuit elements are common to those of the D-RAM, and the same circuit elements are assigned the same reference numerals and overlapping explanations are omitted, and different parts will be mainly described below.

First, in the semiconductor memory device of the first embodiment, the first memory cell 34 has a memory cell transistor 34a and a capacitor 34b similar to the above-mentioned conventional example. The second memory cell 35 has a similar memory cell transistor 35a.
The transistor 35a and the capacitor 35b are not electrically connected, which is different from the above-described conventional example.

The second terminal 25 of the capacitor 34b of the first memory cell 34 has a voltage of 1/2 Vc as in the prior art.
The cell plate has a common potential of c. Similarly,
The second terminal of the capacitor 35b of the second memory cell 35 is also a common cell plate having a potential of 1/2 Vcc.

Hereinafter, the first reference potential is set to 1/2 Vcc potential, the second reference potential is set to Vcc potential, and the third reference potential is set to GND potential (ground potential). Here, the first reference potential can be selected independently of the second reference potential and the third reference potential. However, in the first embodiment, in order to reduce the potential difference between both ends of the insulating film of the capacitors 34b and 35b, the potential 1 is an intermediate potential between Vcc and GND.
/ 2Vcc.

In addition, in this semiconductor memory device, the data storage node of the first memory cell 34 connected to the bit line 47 (or the data storage node of the first memory cell 34 connected to the bit line 48) An initialization means for initializing to a third reference potential is provided, and a read operation is performed after the initialization processing is automatically performed.

In addition, the first dummy cell 3 of the present embodiment
The sixth and second dummy cells 36 have not only the role of canceling the noise described in the conventional circuit but also the following role.

That is, the first memory cell 34 (or 3
When 4) is selected, the bit line 47 is output from the memory cell.
(Or 48), and the charge amount which is exactly intermediate between the charge amount read from the memory cell to the bit line 47 (or 48) when the second memory cell 35 (or 35) is selected. The amount is set to the bit line 48
(Or 47) also has the role of reading. In other words,
The paired bit lines 48 (or 47) serve as references for the bit lines 47 (or 48) to which the memory cells are connected.

The structure and operation of the initialization means are as follows. When the power is turned on, the Vcc rise detection circuit 41 detects the rise of Vcc, and
To output an "H" level signal. When the initialization processing is completed, an initialization completion signal 108 is input to the Vcc rising detection circuit 41 from the row address counter 38. When the initialization completion signal 108 is input, a signal An “L” level signal is output to the line 101.

The signal line 101 is connected to two multiplexers 18, 18. Multiplexers 18, 1
In the signal 8, an “L” level signal is output from the Vcc rising detection circuit 41 to the signal line 101, and the signal line 101 outputs “L”.
When the signal falls to the L level, the external input RAS is input to the signal line 105 connected to the timing pulse generation circuit 22.
The signal 16 is output. Also, the lowest row address signal RA0 (2) is connected to the signal line 106 connected to the row decode circuit 23.
0) is output.

On the other hand, when the signal line 101 rises to the “H” level, the multiplexers 18 and 18 output the signal line 10.
5 to the pseudo R signal supplied from the pseudo RAS signal generation circuit 39.
An AS signal 103 is output. Also, a row address signal 1 given from the row address counter 38 to the signal line 106
04 is output.

A timer circuit 40 is connected to the pseudo RAS signal generation circuit 39. When the signal line 101 is raised to the “H” level, the timer circuit 40 supplies the pseudo RAS signal generation circuit 39 with the pulse signal 1 having a constant frequency.
02 is output. Upon receiving the pulse 102 signal, the pseudo RAS signal generation circuit 39 generates the pseudo RAS
The signal 103 is output. Then, the pseudo RAS signal 103 is supplied to the signal line 105 via the multiplexer 18 as described above.

The pulse signal 102 is also supplied to a row address counter 38. When receiving the pulse signal 102, the row address counter 38 increments the held row address by one. Then, a row address signal 104 is output to the signal line 106 via the multiplexer 18 at regular intervals. Then, when the increment is completed for all the row addresses, the initialization completion signal 108 is output to the Vcc rising detection circuit 41. The row address counter 38 resets the row address to 0 when the signal line 101 rises to "H" level.

The signal line 101 is also connected to the column address decode circuit 24. The column address decode circuit 24 operates when the signal line 101 falls to the "L" level. The operation is the same as that of the column address decoding circuit 24 of the circuit. On the other hand, when the signal line 101 is raised to the "H" level, the column address decode circuit 24 outputs the word lines 30, 31, 32, 33,.
All the column address selection signals 46 are raised to "H" level before any one of them rises. Thus, all the bit lines 47 and 48 are connected to the first I / O line 50 and the second I / O line 51.

The write circuit 49 of the first embodiment has a NAND gate 49a and inverters 49b and 49c connected to the input side and output side of the NAND gate 49a, respectively, in addition to the above-described conventional circuit configuration. Also,
The other input terminal of NAND gate 49a is connected to the output side of NAND gate 49b.
Inverters 49e and 49f are connected to the input side of 9b, respectively. This writing circuit 49 functions as a part of the initialization means. The operation of the write circuit 49 will be described below.

The signal line 10 is connected to the input side of the inverter 49b.
1 is connected, and the write circuit 49 takes a predetermined logical product, and when the signal line 101 is at the “H” level, the write circuit 49 outputs “H” level or “L” according to the value of the lowest row address signal RA0. "Level" is written to the bit lines 47 and 48 via the I / O lines 50 and 51. That is, when RA0 = “L” level, “L” level is written to the bit line 47 and “H” level is written to the bit line 48, respectively. Meanwhile, RA
When 0 = "H", the "H" level is applied to the bit line 47,
"L" level is written to the bit lines 48, respectively.

When RA0 = “L” level, the word line 30 or 32 rises to “H” level, so that “L” level is written to the selected memory cell. On the other hand, when RA0 = “H” level, the word line 31 or 33 is raised to “H” level.
The “L” level is similarly written to the selected memory cell. Next, the specific timing of the initialization operation by the initialization means having the above circuit configuration will be described with reference to FIG. However, in the illustrated example, the word line 30 (first word line) is used.
Is the lowest row address (see FIG. 3 (j)) and the word line 31
(The second word line) is the lowest row address + 1 (FIG. 3)
(K)).

When the power is turned on and the rising of Vcc is detected at the timing shown in FIG. 3A, the Vcc rising detecting circuit 41 raises the signal line 101 to "H" level at the timing shown in FIG. increase. Signal line 101
Rises to the “H” level, the timer circuit 40
From the pulse signal 102 having the waveform shown in FIG.
AS signal generation circuit 39 is provided. Then, pseudo RAS signal generating circuit 39 receiving this pulse signal 102
Supplies a pseudo RAS signal 103 having the waveform shown in FIG. Multiplexer 18
Is applied to the timing pulse generating circuit 22 via the signal line 105 when the signal line 101 is at "H" level.
Give 03. When the signal line 101 rises to the "H" level, the row address counter 38 resets the row address to 0 (see FIG. 3F).

The other multiplexer 18 has the signal line 1
When 01 is at the “H” level, a row address 104 is provided from the row address counter 38 that has received the pulse signal 102 from the timer circuit 40. FIG. 3E shows that the multiplexer 18 supplies the dummy word line control circuit 27 at this time.
Shows the lowest row address signal RA0 (20) applied to the line. FIG. 3F shows a state where the row address is incremented by the row address counter 38.

When the increment operation for all the row addresses is completed, the row address counter 38 outputs an initialization completion signal 108 having a waveform shown in FIG. The Vcc rise detection circuit 41 receives the rise of the initialization completion signal 108 and the fall of the pseudo RAS signal 103 at the time when the initialization of the highest address is completed (FIG. 3).
(G), (d) and (a)), the signal line 101 is “L”.
The level is lowered to the level (see FIG. 3B), and the initialization operation is completed.

In the initialization operation, when the pseudo RAS signal 103 is given from the multiplexer 18 to the timing pulse generation circuit 22 as described above, the timing pulse generation circuit 22
5, bit line precharge signal generation circuit 44, dummy
A pulse signal for control is output to the word line control circuit 27, the column decode circuit 23, and the row decode circuit 24.

As a result, FIGS. 3 (h), (i),
At the timings shown in (j), (k), (l), (m), and (n), the first dummy word line 28, the second dummy word line 29, the first word line 30, Second word line 31, first I / O line 50, second I / O line 5
1. The column address selection signal 46 rises to "H" level, and the initialization operation is performed.

Here, FIGS. 3 (j) and 3 (k) and FIG.
As can be seen by comparing (o) and (p), prior to the rise of the word lines 30 and 31, the bit lines 47 and 48 via the first and second I / O lines 50 and 51. The level of is almost fixed. Therefore, irrespective of the data of the memory cell immediately after the rise of Vcc, the data of the "L" level (= GND potential) is written to the data storage node of the capacitor 34b of the first memory cell 34.

Next, the read operation of the semiconductor memory device of the first embodiment will be described with reference to FIG. However, in the illustrated example, the word line 30 or the word line 32 is selected (see FIG. 4C), and the lowest row address signal RA0 is RA0.
= “L” level (= “0”), and the second dummy word line 29 is selected from the two dummy word lines.
By the selection of the second dummy word line 29, the potential of the reference bit line 48 becomes as shown in FIG.

In this case, first, if the first memory cell 34 is selected by selecting the word line 30, the bit line 4
The potentials of 7 and 48 are as shown by the solid lines in FIGS. That is, the “L” level is read to the bit line 47 to which the first memory cell 34 is connected.

On the other hand, when the second memory cell 35 is selected by selecting the word line 32 (see FIG. 4C),
The potentials of the bit lines 47 and 48 are as shown by broken lines in FIGS. That is, in this case, the “H” level is read to the bit line 47 to which the memory cell 35 is connected.

FIGS. 4 (a), (b), (g),
(H) shows an internal RAS signal 16, a bit line precharge signal 15, and a PMOS sense amplifier drive signal 14, respectively.
5 shows waveforms during a rewrite operation of the NMOS sense amplifier drive signal 13.

The above-described initialization operation and the subsequent read operation will be briefly described. First, the bit line precharge signal generation circuit 44 connects the bit line to which the first memory cell 34 or the second memory cell 35 is connected. 4
7 or 48 is precharged to the second reference potential Vcc. In this state, assuming that the word line 30 is raised to the “H” level and the first memory cell 34 is selected, the data storage node of the capacitor 34 b of the first memory cell 34 and the bit line 47 or 48 Are electrically connected, the bit line 47 or 48 is connected to the bit line 47 or 48 and the capacitor 34 of the first memory cell 34.
b, the precharge potential of the bit line 47 or 48, that is, the _Vcc potential and the first memory cell 3
The potential is a potential intermediate between the write potential of the data storage node of the fourth capacitor 35b, that is, the third reference potential which is the GND potential. The change ΔV2 in the bit line potential at this time is
The value is represented by the above equation (2).

Assume that the second memory cell 35 is selected by the word line 32. In this case,
Since the data storage node of the capacitor 35b of the second memory cell 35 is not substantially electrically connected to the bit line 47 or 48, the potential of the bit line 47 or 48 becomes the precharge potential, that is, the second reference potential. The potential remains at the Vcc potential.

As described above, according to the configuration of the first embodiment, the potential of the bit line 47 or 48 is different between the case where the first memory cell 34 is selected and the case where the second memory cell 35 is selected. different. Therefore, it is possible to determine the data of the first memory cell as data “0” and the data of the second memory cell as data “1” by a subsequent read operation.

Further, by selecting the second dummy word line 29, the potential of the reference bit line 48 is changed as shown in FIG.
It becomes as shown in. Therefore, by amplifying the potential difference between the bit line 47 and the reference bit line 48, FIG.
As shown in (e) and (f), reading of data “1” and “0” is executed.

The first memory cells 34, 34 as described above
And the second memory cells 35 and 35 can be separately formed in the manufacturing process. More specifically, as described in the above-mentioned section of the operation, the masks can be separately formed by patterning on a mask. Therefore, according to the semiconductor memory device of the present invention,
The data of the memory cell can be determined to be “1” or “0” by a manufacturing process similar to a conventionally known D-RAM. That is, according to the above configuration, DR
The AM memory cell can be used as a ROM.

In this embodiment, the first memory cell 34
And the ROM area where the second memory cell 35 is mixed,
In the write circuit 49, the write protect signal 21
9 is fixed at the “H” level. Therefore, the WE signal (active low) is generated by an external write command.
Becomes "L" level (write execution state), the input data 20 from outside is not written to the data lines 50 and 51. Thereby, the second reference potential (GND potential) written to the data storage node of the capacitor 34b of the first memory cell 34 by the initialization means does not change. Therefore, during the operation of the semiconductor memory device, R
The OM data is held in a non-volatile manner without being destroyed.

Here, in the above-mentioned conventional semiconductor memory device, the WE signal 21 input to the write circuit 49 is "
This is a write enable signal that turns ON at L level.
This is a write command input from outside, that is, a signal generated by an external circuit.

On the other hand, in the write circuit 49 in the semiconductor memory device of the first embodiment, as shown in FIG.
In addition to the signal 21, a write protect signal 219 is input. If the write protect signal 219 supplied to the inverter 49f is at the "L" level,
As in the conventional example, the WE signal 21 is written at the "L" level, but when the write protect signal 219 is at the "H" level, the WE signal 21 is at the "L" level, that is, when the external write command is input. Even if there is no writing. However, when the signal line 101 is raised to the “H” level, that is, at the time of initialization, writing is performed.

Therefore, according to the write circuit 49, since the write is effectively protected (write protected), the level of the memory cell 34 written at the time of initialization can be protected. Therefore, when the CPU goes out of control, the ROM
Even if an erroneous write instruction is given to the address of the area, writing is not performed. That is,
Even in such a case, the data is effectively protected.

In the illustrated example, the second memory cell 35
Memory cell transistor 34a and capacitor 35b
Is originally not electrically connected, but the present invention can be similarly applied to a circuit electrically equivalent to this. That is, a circuit configuration may be adopted in which a capacitor 35b having a relatively small capacity or substantially zero can be connected to the memory cell transistor 35a, and the first bidirectional terminal of the memory cell transistor 35b and the second 2 may be configured such that the two bidirectional terminals are not always electrically connected regardless of the potential of the control terminal. The first bidirectional terminal of the memory cell transistor 35b and the bit line 47 (or 48) May be configured to have a circuit configuration that is not electrically connected. Further, the memory cell transistor 35a is connected to the second memory cell 35.
Alternatively, a circuit configuration without the capacitor 35b may be adopted.

In the first embodiment, one set of data lines 50 and 51 is illustrated as shown in FIG. 1, but two or more sets of a plurality of data line pairs such as a data bus are used. Can also be used. 5 and 6 and FIG. 1 to be described later.
Reference numeral 1 illustrates a semiconductor memory device having such data lines.

FIG. 5A shows the overall configuration of a memory chip 200 having four memory blocks 201, 202, 203, and 204, and FIG. 5B shows one of the memory blocks in an enlarged manner. I have. Further, FIG. 6 shows FIG.
The details are shown.

In the illustrated example, there are four sets of bit line pairs having a pair of bit lines 47 and 48, which form one column address. In such a circuit configuration, a row address is supplied to the row decode circuit 13 from the row address buffers 130, 130... And a column address is supplied to the column decode circuit 24 from the column address buffers 140, 140. If you specify a column address,
The exchange of 4-bit data is performed via a plurality of sets of data lines 150.

(Embodiment 2) FIG. 7 shows Embodiment 2 of the semiconductor memory device of the present invention. In the second embodiment, the memory chip 2
00 into four memory blocks 201, 202, 203,
204, of which the memory block 20
Reference numerals 1 and 203 have a first memory cell 34 and a second memory cell 35, and memory blocks 202 and 204 have only the memory cell 34 as in the above-described conventional example.

Therefore, the memory chip 20 of the second embodiment
0, the memory block 20 serving as the ROM area
In Nos. 1 and 203, writing is impossible except for a writing operation at the time of initialization processing. This is the memory
In blocks 201 and 203, this is realized by fixing the write protect signal 219 to “H” level.
On the other hand, the memory block 20 serving as a RAM area
In 2, 204, writing is possible. this is,
In the memory blocks 202 and 204, this is realized by fixing the write protect signal 219 to “L” level.

According to the second embodiment, the memory chip 200
It is possible to freely select and arrange a ROM area and a RAM area for each memory block in the memory. Therefore,
There is an advantage that a semiconductor memory device in which ROM and RAM are freely arranged in memory block units can be realized.

(Embodiment 3) FIG. 8 shows Embodiment 3 of the semiconductor memory device of the present invention. In the third embodiment, the areas of the memory chip are designated by the row addresses RA5, RA6, RA7, (0), (1), (2), (3), (4), (5)
(6) and (7) are configured to be divided into eight memory blocks. Here, each area (0), (1),
Regarding (2), (3), (4), (5), (6), and (7), any area may be a ROM area or a RAM area. In the third embodiment, as an example, the area (0 ),
(6) and (7) are ROM areas, and areas (1) to (5)
Is a RAM area.

Since such an area setting is performed, it is necessary to perform write protection for the areas (0), (6) and (7), and to enable writing for the areas (1) to (5). There is a need to. Therefore, in the third embodiment,
As shown in FIG. 8, a second row decode circuit 230 is provided, and the output of the second row decode circuit 230 is supplied to the input terminal of the write circuit as a write protect signal 219. The second row decode circuit 230 uses the row addresses RA5, RA6, RA7 to read (0),
When (6) and (7) are selected, the "H" level is set, and the RAM areas (1), (2), (3), (4) and (5) are set by the row addresses RA5, RA6 and RA7. When it is selected, it outputs “L” level to the write protect signal terminal 219 of the write circuit. According to such a configuration, "H" (= "1") and "L" (= ") of the write protect signal 219 for the row addresses RA5, RA6, RA7.
0 ”) state is set as shown in FIG. 8, and a ROM area, that is, a write protection area, and a RAM area, that is, a writable area can be set.

Parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

(Embodiment 4) FIG. 9 shows Embodiment 4 of the semiconductor memory device of the present invention. In the fourth embodiment, the area of the memory chip is designated by (0) in FIG.
(1), (2), (3), (4), (5), (6),
(7) A configuration is adopted in which the memory block is divided into eight memory blocks.

In the fourth embodiment, as in the third embodiment, any area can be a ROM area or a RAM area. However, in the fourth embodiment, the areas (0), ( 6) and (7) are ROM areas, and area (1)
(5) is a RAM area.

In the fourth embodiment, the column decode circuit 2
4 has 256 column decode signals 46 (= 2
⁸ ) These column decode signals 46 are obtained by decoding a total of eight column addresses CA0 to CA7. That is, by this decoding, one column decode signal 4
6 is selected.

Memory chip areas (0), (1),
(2), (3), (4), (5), (6), (7)
It is divided by the upper three column addresses CA5, 6, and 7 among the column addresses CA0 to CA7. Further, in the fourth embodiment, a second column decoding circuit 240 having a circuit configuration similar to that of the second row decoding circuit 230 of the third embodiment is provided, and the output of the second column decoding circuit 240 is provided. To the write circuit input terminal.
9 is given. More specifically, the second
Of the column decode circuit 240, the column addresses CA5, 6, 7
When (0), (6), and (7) in the ROM area are selected, the "H" level is changed to the column address CA5, 6,.
7, (1), (2), (3),
When (4) and (5) are selected, the “L” level is output to the write protect signal terminal 219 of the write circuit.

Therefore, also in the fourth embodiment, the write protect signals 219 for the column addresses CA5, CA6 and CA7 are set.
The "H" (= "1") and "L" (= "0") states are set as shown in FIG. 9, and a write protection area and a writable area can be set.

(Embodiment 5) FIG. 10 shows Embodiment 5 of the semiconductor memory device of the present invention. According to the semiconductor memory device of the fifth embodiment, the memory block is divided into the ROM area and the RAM by the row address (word line) by the circuit configuration shown in FIG.
It can be divided into areas. Therefore, in the fifth embodiment, the word lines 30, 31, 32, 33
.. Are provided with a designating means 300 for designating write prohibition / write enable for each. This designating means 300 is NM
It is formed by the OS transistor 301 and the switch means 302, and the designation operation is performed as follows.

That is, for example, in a word line (row address) to be a RAM area, the switch means 302 of the specifying means 300 is made conductive (low impedance) in the manufacturing process. Then, the word line is selected and "
When the node 303 rises to the "H" level, the node 303 is pulled down to the "L" level via the specifying means 300. Therefore, the "L" level write protect signal 219 is input to the input terminal of the write circuit, and writing is enabled. That is, writing is enabled by the WE signal 21 applied to the other input terminal of the writing circuit, and a RAM area is realized.

On the other hand, in a word line to be used as a ROM area,
In the manufacturing process, the switch means 30 of the designating means 300
2 is made non-conductive (high impedance). Therefore,
Even if the word line is selected from this state and raised to the “H” level, the node 303 is held at the “H” level by the pull-up element (pull-up resistor) 304. Therefore, the write protect signal 219 at this time is
Becomes "H" level, and the write disable state is maintained regardless of the value of the WE signal 21 applied to the other input terminal of the write circuit. Therefore, the data written in the memory cell 34 during the initial processing is held in a nonvolatile manner,
Region is realized.

The conduction and non-conduction of the switch means 302 can be easily formed in the manufacturing process depending on the connection / non-connection of the wiring or the presence / absence of the contact, and this formation can be programmed by patterning the wiring or contact mask. .

(Embodiment 6) FIG. 11 shows a sixth embodiment of the semiconductor memory device of the present invention. According to the semiconductor memory device of the sixth embodiment, the ROM area and the R area are provided for each column address unit formed by four bit line pairs consisting of a pair of bit lines 47 and 48.
It is possible to freely arrange the AM area.

In the sixth embodiment, a data address is also stored in a column address which is a ROM area where write protection is performed.
Data is written up to the bus 50A. That is, the write protect signal applied to the input terminal of the write circuit is fixed at "L" level. The data bus 50A has a pair of data lines 50, 51, and 5 respectively.
It is formed by four sets of data lines having 0 ', 51', 50 ", 51", 50 "', 51"'. That is,
This data bus 50A is a 4-bit data bus.

However, in the sixth embodiment, as shown in FIG.
4 is input.

Therefore, in the sixth embodiment, the write protection setting means 400 having the NMOS transistor 401, the switch means 402, the AND gate 403, etc. is provided in order to realize the ROM area by performing the write protection. The operation will be described below.

At the column address to be set in the RAM area, the switch means 402 is turned off (high impedance) in the manufacturing process. In this state, the switch means 4
An “H” level signal is always input to one input terminal of the AND gate 403 connected to the 02 side. Therefore,
If the column address selection signal 46 applied to the other input terminal of the AND gate 403 is at "H" level, the output of the AND gate 403, that is, the write protection setting means 4
The output of 00 becomes an "H" level column decode signal 46 '.

Therefore, in this column address, bit line 4
7, 48 and the data bus 50A are connected, become writable, and a RAM area is realized.

On the other hand, at the row address to be set in the ROM area, the switch means 402 is made conductive (low impedance) in the manufacturing process. In this state, when the WE signal 21 input to the column decode circuit 24 is at “H” level, “H” is applied to one input terminal of the AND gate 403.
A level signal is provided. Therefore, in this case, AN
Even when the column address selection signal 46 input to the other input terminal of the D gate 403 is at "H" level, the output of the write protection setting means 400 is the "L" level column decode signal 46 '. That is, it is turned off.

Therefore, at this column address, WE signal 2
When 1 goes to the "H" level, the bit lines 47 and 48 are not connected to the data bus 50A.
The write data on 0A is not transmitted to the bit lines 47 and 48. Therefore, the data written during the initialization processing is protected, and a ROM area is realized.

The conduction and non-conduction of the switch means 402 are determined in the manufacturing process depending on the connection / disconnection of the wiring, the presence / absence of the contact, and the like, and the formation can be programmed by patterning the mask of the wiring or the contact.

[0127]

According to the semiconductor memory device of the present invention described above,
The first memory cell and the second memory cell can be separately formed in a manufacturing process. Therefore, according to the semiconductor memory device of the present invention, the data of the memory cell is set to "1" or "0" by a manufacturing process similar to that of a conventionally known D-RAM.
Can be determined. That is, according to the above configuration, the memory cells of the D-RAM can be used as the ROM.

Further, according to the semiconductor memory device of the present invention, the second reference potential written to the data storage node of the first memory cell by the initialization means does not change. Therefore, during the operation of the semiconductor memory device, the ROM data is held non-volatile without being destroyed.

According to the semiconductor memory device of the present invention, there is an advantage that a memory chip in which a ROM area and a RAM area are mixed can be formed on the same chip. That is, there is an advantage that this type of semiconductor memory device, which has been difficult in the past, can be realized.

Further, the semiconductor memory device of the present invention has a ROM
And RAM read operations can be performed exactly the same,
RO on the same bit line without complicating the circuit configuration
M and RAM can coexist.

Further, in the semiconductor memory device of the present invention, if the capacity of the memory cell capacitor is made the same as that of the conventional D-RAM, the same read voltage to the bit line as that of the conventional D-RAM can be obtained. A memory in which a ROM and a RAM are mixed can be manufactured by the same manufacturing technology as a conventional D-RAM.

[0132] In particular, according to the semiconductor memory device according to claim 17 wherein, it is possible to realize a semiconductor memory device ROM and RAM areas are mixed arranged in various patterns.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing Embodiment 1 of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a memory block of the semiconductor memory device according to the first embodiment;

FIG. 3 is a timing chart illustrating initialization processing of the semiconductor memory device according to the first embodiment.

FIG. 4 is a timing chart illustrating the operation of the semiconductor memory device according to the first embodiment.

FIG. 5 is a configuration diagram of a memory chip and a schematic diagram showing details of a memory block showing a modification of the semiconductor memory device of the first embodiment;

FIG. 6 is a circuit diagram illustrating further details of a memory block.

FIG. 7 is a configuration diagram of a memory chip showing a second embodiment of the semiconductor memory device of the present invention;

FIG. 8 is a circuit diagram showing a third embodiment of the semiconductor memory device of the present invention.

FIG. 9 is a circuit diagram showing a fourth embodiment of the semiconductor memory device of the present invention.

FIG. 10 is a circuit diagram showing a fifth embodiment of the semiconductor memory device of the present invention.

FIG. 11 is a circuit diagram showing a sixth embodiment of the semiconductor memory device of the present invention.

FIG. 12 is an operation explanatory diagram showing potentials of a first memory cell, a second memory cell, and a dummy cell in an initialization operation of the semiconductor memory device of the present invention.

FIG. 13 shows a potential change of a bit line when a first memory cell to which data “0” is written as external input data is selected and a potential change of a bit line when data “0” is written; FIG.

FIG. 14 is a graph showing a change in bit line potential in the semiconductor memory device of the present invention.

FIG. 15 is a graph showing a potential change of a bit when a first memory cell in which “0” is written as external input data is selected.

FIG. 16 is a graph showing a change in bit line potential in a conventional example.

FIG. 17 is a cross-sectional view illustrating a structure of a first memory cell and a second memory cell.

FIG. 18 is a schematic view showing one image of the semiconductor memory device of the present invention.

FIG. 19 is a circuit diagram showing a conventional example of a semiconductor memory device.

FIG. 20 is an explanatory diagram showing a dummy cell selecting operation in the semiconductor memory device of FIG. 19;

FIG. 21 is a timing chart showing the operation of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 12 column address signal 13 NMOS sense amplifier drive signal 14 PMOS sense amplifier drive signal 15 bit line precharge signal 16 RAS signal 17 row address signal including RA0 18 multiplexer 19 input data 20 RA0 (least significant bit of row address) 21 WE ( Write enable) signal 22 timing pulse generating circuit 23 row decoding circuit 24 column decoding circuit 25 1/2 Vcc potential 26 Vcc potential 27 dummy word line control circuit 28 first dummy word line 29 second dummy word line Reference Signs List 30 first word line 31 second word line 32 third word line 33 fourth word line 34 first memory cell 34a memory cell transistor of first memory cell 34b capacitor of first memory cell 35 Second memory cell 35a Memory cell transistor of second memory cell 35b Capacitor of second memory cell 36 Dummy cell 37 Sense amplifier 38 Row address counter 39 Pseudo RAS signal generation circuit 40 Timer circuit 41 Vcc rise detection circuit 42 Memory block 44 Bit line precharge signal generation circuit 45 Sense amplifier drive circuit 46 Column address selection signal 47 First bit line 48 Second bit line 49 Write circuit 49a NAND gate 50 First I / O line 51 Second I / O Line 101 Signal line 102 Pulse signal 103 Pseudo RAS signal generation circuit 104 Row address signal 108 Initialization completion signal 200 Memory chip 201, 202, 203, 204 Memory block 219 Write protect signal 300 Designating means 400 Line Protection setting means

Claims (17)

(57) [Claims] 1. A semiconductor memory device having a plurality of bit lines and a plurality of word lines, wherein a first terminal is a data storage node, and a second terminal is connected to a capacitor having a first reference potential and a gate connected to the word line. A first memory cell having a switching transistor having one of a source and a drain connected to the bit line and the other of the source and the drain connected to the first terminal of the capacitor; A semiconductor memory device comprising: a switching transistor connected to the word line; and a second memory cell having a capacitor that is not electrically connected to the bit line regardless of whether the word line is selected or not. 2. The switching of the second memory cell.
Regardless of whether the source and drain of the transistor are selected or not selected in the word line connected to the gate,
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is not always conductive. 3. The semiconductor memory device according to claim 1, wherein said switching transistor is omitted in place of providing a switching transistor which is not always conductive. 4. The switching of the second memory cell.
2. The semiconductor memory device according to claim 1, wherein a source and a drain of the transistor are not electrically connected to the first terminal of the capacitor. 5. The switching of the second memory cell.
2. The semiconductor memory device according to claim 1, wherein a source and a drain of the transistor are not electrically connected to the bit line. 6. A precharge means for precharging the bit line connected to the first memory cell or the second memory cell to a second reference potential irrelevant to the first reference potential, and the first memory cell Initialization means for initializing the data storage node of the capacitor to a third reference potential different from the second reference potential, and after the initialization by the initialization means, When the first memory cell is selected by selecting the word line, the bit line potential changes, and
2. The semiconductor memory device according to claim 1, wherein the bit line potential does not change when a memory cell is selected. 7. The semiconductor memory device according to claim 6, further comprising bit line potential changing means for causing a potential change of said bit line by about half of a potential change of said bit line by said first memory cell. 8. The semiconductor memory device according to claim 1, further comprising protection means for protecting an area where said first memory cell and said second memory cell are mixed from being written to external input data. 9. The method according to claim 1, wherein the first memory cell and the second memory cell are mixed, and a first area protected from writing of external input data by the protection means and only the first memory cell are present. 9. The semiconductor memory device according to claim 8, wherein said second region capable of being formed is mixed on the same substrate. 10. The semiconductor memory device according to claim 9, wherein said first area is a ROM area and said second area is a RAM area. 11. A semiconductor device having a plurality of bit lines and a plurality of word lines.
A first terminal is a data storage node, and a second terminal is a first terminal.
A capacitor at a sub-potential and a gate connected to the word line
And one of the source and drain is connected to the bit line.
And the other of the source and the drain is connected to the capacitor.
A switching transformer connected to the first terminal of the capacitor;
A first memory cell having a transistor, and a configuration in which a capacitor is omitted as compared with the first memory cell .
The semiconductor memory device having a third memory cells. 12. It has a plurality of bit lines and a plurality of word lines.
A first terminal is a data storage node, and a second terminal is a first terminal.
A capacitor at a sub-potential and a gate connected to the word line
And one of the source and drain is connected to the bit line.
And the other of the source and the drain is connected to the capacitor.
A switching transformer connected to the first terminal of the capacitor;
A first memory cell having a transistor and a capacitor having a smaller capacitance than the first memory cell;
And a third memory cell having a configuration equivalent to zero.
For example, a precharge means for precharging the <br/> bit line to which the first memory cell or said third memory cell is connected to the second reference potential independent of the said first reference potential, said first memory and a initializing means for initializing a different third reference potential to the data storage node of the capacitor of the cell and the second reference potential, the initialization is performed by the initialization means, in a read operation, the selection of the word line, the first bit line potential changes when the selected memory cell, the semiconductor memory device as the bit line potential does not change when selecting the third memory cell. 13. A semiconductor device having a plurality of bit lines and a plurality of word lines.
A first terminal is a data storage node, and a second terminal is a first terminal.
A capacitor at a sub-potential and a gate connected to the word line
And one of the source and drain is connected to the bit line.
And the other of the source and the drain is connected to the capacitor.
A switching transformer connected to the first terminal of the capacitor;
A first memory cell having a transistor and a capacitor having a smaller capacitance than the first memory cell;
And a third memory cell having a configuration equivalent to zero.
For example, a semiconductor memory device having a bit line potential change means for creating an approximately half of the potential change of the potential change of the bit line according to said first memory cell to the bit line. 14. A semiconductor device having a plurality of bit lines and a plurality of word lines.
A first terminal is a data storage node, and a second terminal is a first terminal.
A capacitor at a sub-potential and a gate connected to the word line
And one of the source and drain is connected to the bit line.
And the other of the source and the drain is connected to the capacitor.
A switching transformer connected to the first terminal of the capacitor;
A first memory cell having a transistor and a capacitor having a smaller capacitance than the first memory cell;
And a third memory cell having a configuration equivalent to zero.
For example, a semiconductor memory device having a protection means for protecting the area where the first memory cell and said third memory cells are mixed from writing external input data. 15. A method according to claim 15, wherein the first memory cell and the third memory cell are mixed, and a third area protected from writing by the protection means and only the first memory cell are present.
15. The semiconductor memory device according to claim 14 , wherein a writable fourth region is formed on the same substrate. 16. The semiconductor memory device according to claim 15 , wherein said third area is a ROM area and said fourth area is a RAM area. 17. A semiconductor memory device comprising a plurality of regions, the semiconductor memory device of selectable claim 10 or claim 16, wherein optionally in each region and the ROM region and the RAM region.