JP2833899B2 - Semiconductor read-only memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor read-only memory, and more particularly to a read-only memory for selecting a NAND type memory cell.

[0002]

2. Description of the Related Art Conventionally, as shown in FIGS. 3 and 5, a memory cell is turned on by a gate voltage "H" and turned off by a "L".
The enhancement transistors (transistors 307a, 307c, 308a, 308c in FIG. 3, FIG.
Transistors 507a, 507c, 508a, 508
c) and a memory block 307, 308, 507, 508 consisting of a depletion transistor (transistors 307b, 308b in FIG. 3, and transistors 507b, 508b in FIG. 5) which are always in the ON state.
It has a D-type memory cell configuration.

Further, the same data output signal lines 315,
When a plurality of NAND type memory cells (memory cell blocks 307, 308, 507, 508) are connected to 515, the enhancement transistor 313,
At 314, 513 and 514, a memory cell block is selected.

In FIG. 3, there are lines of input signals 301 to 305, there are eight inverters having one of them as an input, and further, memory cell block selection signals 311 and 312 are obtained through the inverters. This line is connected to the gates of the enhancement transistors 313 and 314, respectively, and the others are gate inputs to the memory blocks 307 and 308. Further, the data output signal line 315
Are connected to the memory blocks 307 and 308 via the transistors 313 and 314, respectively.

In FIG. 5, six inverters and six two-input NAND gates 516 are added to the circuit of FIG. Others are the same as FIG.

Next, the operation will be described. First, with the “H” signal applied to the gates of all memory cells,
Since all of the enhancement transistors are turned on and the depletion transistor is always on, a current flows through the NAND cell. In this state, when only the gate of the selected memory cell is set to “L”, if the selected memory cell is an enhancement transistor, it is turned off, and no current flows. Also, if it is a depletion transistor, O
The current continues to flow without FF. By sensing this difference, the output of the semiconductor read-only memory is determined.

In FIG. 3, the "H" signal is always applied to the gate of the memory cell unless it is selected, causing the gate oxide film of the cell to be destroyed.

Therefore, in order to reduce the stress applied to the gates of the memory cells, the voltage applied to the gates of all the memory cells in the unselected memory cell block is set to "L" in FIG. It has a circuit configuration that reduces the stress applied to the gate.

FIG. 4 shows the operation waveform of FIG. 3, and FIG. 6 shows the operation waveform of FIG.

Referring to FIG. 4, first, word lines 309b, 3
10b is “L”, all other word lines are “H”, and the memory block selection signal line 311 is “H”, 312
Is "L", the memory cell 307b is selected, and the word lines 309c, 31 which become "L" from that state are selected.
0c, the memory block selection signal lines 311 and 31
2 shows a waveform when 2 is inverted and the selection is switched to the memory cell 308c.

Here, a power supply (VCC) level 401,
A GND level 402 and a semiconductor read-only memory output 403 are also shown.

In FIG. 6, when the memory cell selection signal line 511 is at "H" and 512 is at "L",
7 is selected, and the word lines 510a to 510c connected to the unselected memory cell block 508 are set to "L", and the line 509 is selected in the selected block 507.
Only b is “L”. When the memory block selection signals 511 and 512 are inverted from this state, the memory cell block 508 is selected, and all the word lines connected to the block 507 become "L", and the memory block 5
All the word lines connected to 08 become “H” except for the word line 508 c connected to the selected cell.

Here, a power supply (VCC) level 601,
Each of the GND levels 602 fluctuates. That is, noise occurs.

[0014]

In the conventional case as shown in FIG. 3, the "H" signal, that is, the voltage of the power supply VCC is always applied unless the gate of the memory cell is selected. There is a problem that stress continues to be applied to the gate of the memory cell and the gate oxide film of the memory cell is broken.

In FIG. 5, the stress applied to the gates of the memory cells as shown in FIG. 3 is reduced by setting all the word lines connected to the unselected memory cell blocks to "L". The charge and discharge of a large number of word lines when the cell block switches causes noise, which causes this noise to circulate to other circuits, particularly sensitive sense amplifiers, causing malfunctions,
There is a problem in that the signal goes around the input system and the input level is deteriorated.

It is an object of the present invention to provide a semiconductor read-only memory which solves the above-mentioned problems and does not cause a gate breakdown and does not generate noise.

[0017]

According to the structure of the semiconductor read-only memory of the present invention, at least two types of depletion transistors having different thresholds are used as memory cells. And means for setting a word line connected to the transistor gate of the memory cell to a negative potential and setting the other word lines to 0V.

[0018]

FIG. 1 is a circuit diagram showing a semiconductor read-only memory according to an embodiment of the present invention.

In FIG. 1, the dedicated memory of this embodiment is
Between the memory blocks 107 and 108 and the inverter,
Step-down circuits 116 are interposed. Other parts are the same as those in FIG.

As shown in FIG. 1, the threshold value is adjusted by the step-down circuit 116, the gate is turned on when the gate potential is 0 V, and the gate potential is turned on when the gate potential is negative.
The depletion transistor 107a which becomes the FF,
107c, 108a, 108c and the depletion transistor 1 which is always ON because the threshold value is sufficiently negative.
07b and 108b constitute a NAND memory cell. Further, in this selection circuit, the memory cells 107a, 107c, 108a, 108c whose thresholds have been adjusted
A negative potential is required in order to utilize the fact that the gate potential is turned on when the gate potential is 0 V and turned off when the gate potential is negative. Therefore, a step-down circuit 116 is provided.

In this embodiment, when the gate voltage of all the memory cells is set to 0 V, all the NAND cells are turned on, and a current flows. Assuming that only the gate voltage of the memory cell selected in this state is a negative potential, the memory cell becomes the depletion transistor 10 whose threshold has been adjusted.
If it is 7a, 107c, 108a, 108c, it is turned off, no current flows, and the depletion transistors 107b, 108b whose thresholds are sufficiently negative potential
Then, the current flows in the ON state. This current is
By sensing the difference between flowing and not flowing, the output of the semiconductor read-only memory is determined.

FIG. 2 shows waveforms in a case where the memory cell of FIG. 1 is replaced with the transistor 107c from the transistor 107b.

First, the word lines having a negative potential are the output signal lines 109b and 110b, and the memory cell block selection signal 1
11 is “H”, the signal line 112 is at 0 V, and the memory cell block 107 is selected, and the word line having a negative potential is changed from the signal lines 109 b and 110 b to the signal line 109.
c, 110c, the memory block selection signals 111,
By inverting 112, the selected memory cell is replaced with the memory block 108.

The case where the one-conductivity-type transistor is used as a memory cell has been described above. However, similar effects can be obtained by using an anti-conductivity-type transistor as another embodiment.

FIG. 2 shows a power supply (VCC) level 201, a GND level 202, a semiconductor read-only memory output 203, and a negative output level of the step-down circuit 116.

N in the read-only memory of this embodiment
The cell selection circuit of the AND type memory cell turns on when the gate voltage applied to the memory cell is 0 V, and turns on when the gate potential is negative.
Depression with threshold adjusted to be FF
Always ON since transistor and threshold voltage are sufficiently negative
The depletion transistor in the state is used for a memory cell, the potential of a word line connected to the gate of the selected memory cell is set to a negative potential, and all other word lines are set to 0V.

[0027]

As described above, according to the present invention, the word line level becomes 0 V except for the word line connected to the selected memory cell. Gate destruction does not occur because stress is not applied to the gate of the memory cell, thereby increasing reliability. In FIG. 5, noise due to charging and discharging of a word line when a selected memory cell block is switched is also selected. By setting all the word lines connected to other than the memory cells to “0” V, the occurrence does not occur. Therefore, malfunctions of the sense amplifier caused by noise wraparound due to charge / discharge of the word lines, deterioration of the address input level, and the like are caused. This has the effect that no longer occurs.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor read-only memory according to one embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of FIG.

FIG. 3 is a circuit diagram showing an example of a conventional memory cell selection circuit.

FIG. 4 is a waveform chart showing the operation of FIG.

FIG. 5 is a circuit diagram showing another example of a conventional memory cell selection circuit.

FIG. 6 is a waveform chart showing the operation of FIG.

[Explanation of symbols]

101-105, 301-305, 501-505
Input signals 106, 306, 506 Inverters 107, 108, 307, 308, 507, 508
Memory blocks 107a, 107c, 108a, 108c Depletion transistors 107b, 108b, 307b, 308b, 507b, which are turned on at a gate voltage of 0 V and turned off at a negative potential.
508b Depletion transistors 109a-109c, 110a-110c, 309a-
309c, 310a to 310c, 509a to 509c,
510a to 510c Memory cell selection signal lines (word lines) 111, 112, 311, 312, 511, 512
Memory cell block selection signal line 116 step-down circuit 115 data output signal line 307a, 307c, 308a, 308c, 507a,
507c, 508a, 508c, 113, 114, 31
3,314,513,514 Enhancement transistor 516 2NAND gate 201,401,601 Power supply (VCC) level 202,402,602 GND level 203,403,603 Semiconductor read-only memory output

Claims (2)

(57) [Claims] 1. When at least two types of depletion transistors having different thresholds are used as memory cells and the memory cell is selected, a word line connected to a transistor gate of the selected memory cell is negatively charged. Potential and the other word lines at 0V
A semiconductor read-only memory, characterized by comprising means for: 2. The semiconductor read-only memory according to claim 1, wherein the memory cell comprises a series body of three transistors.