JPH0620474A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To eliminate the same number of bus lines as a pit width by discriminating whether data in the high level or in the low level should be written in a memory cell or write should be inhibited. CONSTITUTION:The threshold level of an inverter I1 is set to 3/4 of a supply voltage VCC, and that of an inverter I2 is set to 1/4 VCC. When a line phiDATA is in the high level ( VCC)/the low level ( 0V), nodal points N1 and N2 go to the low level/the high level, and an output nodal point N3 of a NOR gate NR1 goes to the high level, and data on the line phiDATA is transmitted to complementary signal lines D and D*. As the result, data is written in a selected cell in a memory cell array 100. Meanwhile, when the line phiDATA is in the intermediate level ( 1/2VCC), the nodal point N1 goes to the high level, and the nodal point N2 goes to the low level, and therefore, the nodal point N3 of the NOR gate NR1 goes to the low level to set the write inhibiting state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit having a write mask function or a write per bit function, which does not write a specific bit during a write operation.

[0002]

2. Description of the Related Art A conventional semiconductor memory circuit having a function of not writing only a specific bit during a write operation (hereinafter referred to as a write mask function) has a data bus φDATA, a write timing giving φWE and a write as shown in FIG. It was controlled by φMSK *, which gives information on whether to mask or not. (In the following description, * indicates that the active level of the signal is set to a low level and corresponds to an overbar.) FIGS. 3 and 4 are timing charts showing the operation of FIG.

FIG. 3 is a timing chart when the write mask is not performed. At this time, since φMSK * remains high, when φWE becomes high, the write switch N
W becomes a high level, the data on φDATA is transmitted to the complementary signal lines D and D *, and the complementary signal lines D and D * have opposite phases. Writing to the selected cell in the memory cell array 200 is performed by the complementary signal lines D and D * having opposite phases.

On the other hand, FIG. 4 is a timing chart for write masking. At this time, φMSK * becomes low level. Then, φWE becomes high level, but since the write switch NW remains at low level, the data of φDATA is not transmitted to the complementary signal lines D and D *, and the complementary signal lines D and D * are not transmitted.
Both keep high levels. Therefore, no data is written to the selected memory cell and the previous data is retained.

This write mask function is often used in a multi-bit width memory IC, and it is possible to specify whether to write for each bit. When the multi-bit width memory IC has a write mask function, the layout of the memory chip is as shown in FIG. 5, because the characteristics of the memory IC deteriorate if the circuit of FIG. 2 is not near the memory cell array. Become. FIG. 5 is a chip layout of an 8-bit width memory IC. 5, a1 to a8 are the same circuits as shown in FIG. 2, and b is a write control circuit.

The bus line C is assigned to φWE in FIG. 2, the bus line d is assigned to φDATA, and the bus line e is assigned to φMSK *. Since φDATA and φMSK * are required for each bit, the bit width (8 bits in the example of FIG. 5)
Bus line is required.

[0007]

In the above-mentioned conventional semiconductor memory circuit, two types of bus lines having the same number as the bit width are required in the chip. Further, as shown in FIG. 5, this bus line often extends along the long side of the chip, and therefore the length of the short side of the chip increases.
For an IC such as a semiconductor memory, which is often a relatively rectangular chip, an increase in the short side causes a problem that the chip area is significantly increased.

This means that the bit width is 16 or 32.
In the case of a multi-bit product such as the above, the increase in the short side, and thus the increase in the chip area, becomes significantly large.

[0009]

SUMMARY OF THE INVENTION A gist of the present invention is to provide a memory cell array composed of a plurality of addressable memory cells, and to write data supplied from the outside into the addressed memory cells. In a semiconductor memory device having a write inhibit function capable of selectively inhibiting the writing of data to the addressed memory cell. Is set to one of a first voltage level, a second voltage level, and a third voltage level indicating write inhibition corresponding to the logic level of the data supplied from the data generating circuit and the memory cell array. Providing a determination means for determining the voltage level and writing data or prohibiting data writing A.

[0010]

When data is supplied from the outside, the data generation circuit determines the logic level of the data and whether or not the write is prohibited, and sets the data signal to one of the first to third voltage levels. The discriminating means writes or prohibits data according to the voltage level of the data signal.

[0011]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The inverters I1 and I2 are designed by shifting the threshold levels. Normally, the threshold level of the gate of the inverter or the like is set to half of the power supply voltage (VCC), but in the present embodiment, the threshold level of the inverter I1 is 3
/ 4 VCC, and the threshold level of the inverter I2 is set to 1/4 VCC.

When φDATA is at a high level (≈VCC) / low level (≈0V), both nodes N1 and N2 are at a low level / high level, so the output node N3 of the NOR gate NR1 is at a high level and φWE is at a high level. Then, the node N4 becomes high level, and the data on φDATA is transmitted to the complementary signal lines D and D *. As a result, data is written in the selected cell in the memory cell array 100.

On the other hand, φDATA is at an intermediate level (≈1 / 2
At the time of (VCC), the node N1 is at a high level and the node N2 is at a low level, so that the output node N3 of the NOR gate N1 is at a low level and the write inhibit state is set. Note that the wiring N3
Is input to the 3-input NAND gate ND1 in order to prevent the through current of the NAND gate ND1 due to φDATA becoming 1/2 VCC when the write is prohibited. φD
The operation of setting ATA to the high level, the low level, and the intermediate level may be performed by using φMSK * in the write control circuit b of FIG.

FIG. 9 is a circuit diagram showing the data signal generating circuit 900 in the write control circuit b. The data on the external terminal DIN for fetching the write data is transmitted to φDATA via the data-in buffer 901. That is,
SW1 to 3 are CMOS switches, CP2 is wiring φDAT
The parasitic capacitance of A, CP2 ', is the capacitance that was intentionally added,
The capacitance value is CP2 '= CP2. Since φMSK * is high level when writing is not prohibited, CM
The OS switches SW1 and SW2 are on, and the CMOS switch SW3 is cut off. Therefore, the DIN data is transmitted to φDATA, and the node N8 is charged to the level opposite to φDATA.

On the other hand, when write is prohibited, φMSK * becomes low level, the CMOS switches SW1 and SW2 are cut off, and the CMOS switch SW3 is turned on. Therefore, the charges of the capacitors CP2 and CP2 ′ are divided, and φDATA becomes 1
It becomes the level of / 2VCC.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment, φD is used when writing low level data.
ATA is set to a low level (≈0 V), and when writing high level data, φDATA is set to a high level (≈VCC-Δ). Then, when writing is prohibited, φDATA is raised to the VCC level or higher. When φDATA becomes higher than the VCC level, the output N5 of the comparator C1 becomes low level, and writing is prohibited.

The circuit for generating φDATA is made by using φMSK * in the write control circuit b in FIG.
FIG. 7 shows an example of a circuit that generates φDATA at this time.
FIG. 7 shows a data generation circuit 700, in which the data of the external terminal DIN for fetching the write data is transmitted to φDATA via the data-in buffer 701. Alternatively, Q1 is an N-channel transistor, CP1 is a capacitor, and DL is a delay element. ΦMSK * when writing is not prohibited
= Since this is a high level, the write data from DIN is transmitted to φDATA.

FIG. 8 is a timing chart when writing is prohibited.
Shown in. When φMSK * goes low, φDATA goes to the level of VCC-VTN regardless of the level of node N7. Here, VTN is the threshold voltage of the N-channel transistor Q1. After the constant delay determined by the delay element DL, the node N6 becomes high level, and therefore the capacitance CP1
Due to this coupling, φDATA rises to a potential higher than the VCC level, and the write inhibit state is transmitted to the circuit shown in FIG.

When φMSK * returns to a high level, φDAT
A becomes a value according to the node N7.

[0020]

As described above, according to the present invention, high-level data is written to a memory cell, low-level data is written, or three levels of potential of a bus carrying write data are used. Since it is determined whether or not the write operation to the memory cell is prohibited, there is an effect that the same number of bus lines as the bit width can be reduced and the chip size can be reduced accordingly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a timing chart showing an operation of a conventional example.

FIG. 4 is a timing chart showing an operation of a conventional example.

FIG. 5 is a layout diagram showing a chip layout of a conventional example.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a data generation circuit in a second embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the second embodiment.

FIG. 9 is a circuit diagram showing a data generating circuit in the first embodiment of the present invention.

[Explanation of symbols]

 I1, I2 Inverter D, D * Data bus a1 to a8 Circuit block c, d, e Signal line b Write control circuit block C1 Comparator Q1 N channel transistor CP1, CP2, CP2 'Capacitance N1 to N8, NW Node 100 , 200 Memory cell array 700, 800 Data generation circuit DL delay element SW1 to 3 CMOS switch

Claims (1)

[Claims] 1. A memory cell array composed of a plurality of addressable memory cells, and a data generation circuit for generating a data signal representing the data in order to write externally supplied data to the addressed memory cells. In the semiconductor memory device having a write inhibit function capable of selectively inhibiting the writing of data to the addressed memory cell, the data generation circuit corresponds to the logic level of the data supplied from the outside. The first voltage level, the second voltage level, or the third voltage level indicating write inhibition is set, and the voltage level of the data signal is determined between the data generation circuit and the memory cell array to write or write data. A semiconductor memory device, comprising: a determination unit for executing data write inhibition.