JP2832919B2 - Display device using field emission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using a field emission cathode known as a cold cathode.

[0002]

2. Description of the Related Art An electric field applied to a metal or semiconductor surface is 10
^At about ⁹ [V / m], electrons pass through the barrier due to the tunnel effect, and electrons are emitted in a vacuum even at room temperature. This is called field emission, and a cathode that emits electrons based on this principle is called a field emission cathode (hereinafter referred to as FEC).
It is called). In recent years, it has become possible to make use of semiconductor processing technology to produce a surface-emission type field emission cathode composed of micron-sized field emission cathodes. Irradiation of electrons emitted from the respective emitters onto a phosphor screen is expected as an element constituting a flat display device or various electronic devices.

One method of manufacturing such a field emission device is a rotary oblique deposition method developed by Spindt (US Pat. No. 37).
89471), and another method is based on a selective etching method for a silicon single crystal plate. The former has a feature that the cathode chip material can be almost freely selected, and the latter has a feature that the current semiconductor fine processing can be applied as it is.

FIGS. 12A and 12B show FECs manufactured by the SPINDT method. F in FIG.
In the EC, a thin-film conductor layer 101 serving as a cathode electrode is formed by vapor deposition on a substrate 100 made of glass or the like, and Si doped with impurities is formed thereon to form a resistance layer 1.
02 is formed, and the insulating layer 103 is further formed of SiO ₂ .
Are formed. Then, the gate electrode layer 10 is formed thereon.
4 Nb is deposited. Holes 114 are provided in the insulating layer 103 and the gate electrode layer 104. Mo, which is an emitter material, is deposited on the hole 114 side of such a substrate by forward evaporation to form a cone-shaped emitter 115 on the resistance layer 102. Are formed.

[0005] Such an FEC is a cone-shaped emitter 1.
Since the distance between the gate electrode layer 104 and the gate electrode layer 104 can be made submicron,
By applying a voltage of only several tens of volts between 04,
Electrons can be emitted from the emitter 115.

FIG. 12B shows an FEC having a triode structure.
In this example, another insulating layer 107 is provided on the gate electrode layer 104, and a second gate electrode 108 is stacked thereon. The second gate electrode 108 plays a role for focusing the electrons extracted from the emitter.

A display device can be formed by using the FEC as shown in FIGS. 12A and 12B. For example, a display device using FIG. 12B is configured as shown in FIG. That is, the anode substrate 116 to which the phosphor material is attached is disposed above the substrate on which a large number of the FECs are formed in an array. Then, the control voltage V _G1 with respect to the first gate 104, a voltage V _G2 for the focusing operation to the second gate 108, and by applying the anode voltage V _A, the phosphor by electrons emitted from the emitter 115 Can emit light, and a display device can be obtained.

[0008]

Generally, in a display device, a data holding circuit (memory) is provided for each pixel.
If, for example, the memory data is applied to the gate electrode as a control voltage to enable so-called static display, a drive voltage much lower than that of dynamic display and sufficient luminance can be obtained.
It is considered suitable. In particular, in a display device based on the FEC, a static display is required also in view of the fact that a higher voltage is required to increase the luminance.

Conventionally, a TFT-LCD (thin film transistor type LCD) and a PDP (plasma display) have been known as having a memory function for each pixel of a display element. Therefore, in a display device using the above-described FEC, it is conceivable to add a memory function to each pixel by combining, for example, a TFT method. However, this actually makes the manufacturing process too complicated and is not practical. There is a problem that is not.

When it is desired to execute gradation display in a display device using the FEC, for example, it is conceivable to provide data obtained by PWM-modulating image data and control the light emission period. It is required to add a memory function and hold PWM modulation data.

[0011]

SUMMARY OF THE INVENTION In view of the above problems, the present invention makes it possible to easily add a memory function to each pixel even in a display device using FEC. It is intended to provide a technology that enables the following.

For this reason, a display device using a field emission device has a plurality of field emission devices (FEC) each having a cathode, a control electrode (first gate), and a focusing electrode (second gate). Performs a field emission on an anode electrode to form one pixel, a cathode, a control electrode (first gate), and a focusing electrode (second gate)
A switching element portion formed by using a field emission device having a field emission operation from the cathode to the focusing electrode according to the voltage applied to the control electrode, and any one of the cathode, the control electrode and the focusing electrode A data holding portion having a capacitor portion formed by sandwiching a dielectric material therebetween, wherein one unit of data holding portion is provided for a pixel portion constituting one pixel, and The data held in the capacitor section in the data holding section is supplied to the control electrode in the field emission element. Also, the cathode and the cathode of the field emission device in the pixel section
The cathode of the switch element part is formed at almost the same height.
You. Similarly, the control electrode and the control electrode of the field emission device in the pixel portion are switched.
Of the control electrode of the switch element part and the field emission element of the pixel part.
The focusing electrode and the focusing electrode of the switch element are almost the same.
It is formed at one height position.

The capacitor section is configured to hold a voltage value corresponding to the gradation of image data.

[0014]

In a so-called triode-structure FEC, electrons emitted from the cathode in response to the application of a voltage to the control electrode (first gate) are made to fly to the focusing electrode (second gate), and current is applied between the cathode and the focusing electrode. Can flow. For example, FIG.
As shown in FIG. 1A, the voltage V between the first gate and the cathode
_{When G1} exceeds a certain threshold voltage _VTH , the second gate current Ia flows. The second gate as shown in FIG. 11 (b) - voltage V _G2 voltage V ₁ of the inter-cathode ~V
₂ , the second gate current Ia
Flows.

By utilizing these characteristics, an electronic circuit using an FEC element as a switch element can be constructed. Therefore, a switching element can be formed by providing an FEC other than the pixel portion, for example, by using the FEC.

Further, if a dielectric layer is sandwiched between any two of the cathode, the first gate and the second gate, a capacitor can be formed. Therefore, a data holding section can be formed by the switch element and the capacitor section, and it can be easily provided for each pixel.

Further, since a voltage value corresponding to the applied image data is held in the capacitor section,
For example, if the image data is PWM-modulated according to the gradation, a voltage value corresponding to the gradation is stored.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 9 shows a schematic configuration of a display device using FEC. In the display device 1, image data for display is supplied to the memory 2, and the image data is read from the memory 2 under the control of the timing controller 3 and supplied to the shift register 6.

Image data for one horizontal line is supplied from the shift register 6 to the data driver 5 based on a timing signal from the timing controller 3, and a voltage based on the image data for one horizontal line is applied to the gate line G.
It will be applied to ₁ ~G _m.

[0020] The gate G ₁ ~G _m is formed in a state where the second gate G _S are stacked via an insulating portion of the first gate G _F and the focusing electrode as each control electrode, image data will be applied to the first gate G _F. Then, the second in each of the gate lines G _{1 to} G _m
Voltage from the second gate power supply VG ₂ is applied to the gate.

The timing controller 3 controls the scan driver 4 so that the scan operation is performed in the vertical direction. That is, this scan side driver 4
It will sequentially applied scan voltage to the cathode C ₁ -C _n is.

[0022] Each of the cathode C ₁ -C _n, common cathode CC, scan cathode SC, are three clear electrode CL is formed in a state of being lined. Then, the scan driver 4 applies the drive voltages V _S and V _CL to the scan cathode SC and the clear electrode CL at predetermined timings shown in FIG. Common cathode CC of the cathode C ₁ -C _n is grounded.

In the display area, for example, cathodes C _{1 to} C _n composed of a common cathode CC, a first scan cathode SC, and a clear electrode CL are arranged in a horizontal line direction on a glass substrate. The FEC array as described in FIG. 13 is formed. Furthermore, the first gate G at the top the gate lines G ₁ ~G _m
F, the second gate G _S is placed.

In this figure, a large number of holes 21 are formed at the intersections of the gates G _{1 to} G _m and the cathodes C _{1 to} C _n , respectively. On the other hand, an FEC array is formed as shown in FIG. That is, the number of FEC array in a portion comprising the intersection of the gate G ₁ ~G _m and cathode C ₁ -C _n form a single pixel (pixel unit 20).

A _N indicated by a dashed line represents the cathodes C ₁ -C
₂ shows an anode disposed above _n and gates G _{1 to} G _m , and a phosphor is applied to each pixel. And
When a voltage is applied on the basis of the image data to the first gate G _F, electrons from FEC intersections become pixels of the cathode being driven by the vertical scanning at that time (C ₁ -C _n) to the anode A _N Is emitted to excite the phosphor, and a display operation is performed.

Further, in the display device 1 of this embodiment, the memory unit 3 is shown as a hatched portion corresponding to each pixel unit 20.
0 is formed. Driving the pixel unit 20 described above, i.e. the voltage applied to the first gate G _F is the memory section 3
0 based on the held data,
Voltage based on the applied image data to the gate lines G ₁ ~G _m is first provided to the memory unit 30 in the present embodiment, data stored in the memory unit 30 is applied to the first gate G _F Will be. That is, static display is realized.

Hereinafter, the configurations of the pixel section 20 and the memory section 30 which are the main parts of this embodiment will be described. FIG. 1 shows the vicinity of a certain pixel portion in FIG. 9 (the cathodes C ₂ and C ₃ and the gate G).
₂ and G ₃ ) are shown in an enlarged state. The cathodes C ₂ and C ₃ shown in the lowermost layer in this drawing are arranged with a clear electrode CL, a common cathode CC and a scan cathode SC, respectively, and gates G ₂ and G ₃ are located above them. G ₁ ~G _m) and the first gate G _F as described above and the insulating portion Z1 second gate G
Formed from _S.

Attention is now directed to the pixel portion 20 at the intersection of the cathode C ₃ and the gate G _2. The second gate G _S of the gate G ₂ is not directly connected to the portion of the pixel portion 20.
A portion forming the upper surface side of the memory unit 30 via the resistance units R ₂ and R ₃ is connected to the pixel unit 20 to form the upper surface unit. The second gate G _S sites of the memory unit 30 corresponding to the cathode C ₃ and the intersection of the pixel portion 20 of the gate G ₂ is connected from the second gate G _S of the gate G ₃ via the resistor portion R ₁ ing. And, for such a memory unit 30 FE beneath the second gate G _S
A C array is formed, and its portion is defined by element portions Q ₁ and Q
₂ , Q ₃ , and Q _{4 and} function as switch elements.

A portion indicated by reference numeral 31 in the figure is a capacitor portion for holding data. This capacitor unit 31
Dielectric layer between the gate G _S and the cathode are formed by being tight-holding. 32, 33, 34, 3
5, 36, and 37, 3 shown in FIGS.
Reference numerals 8 and 39 denote conductor layers formed below the second gate G _S , and R ₄ denotes a resistor.

FIGS. 2 to 7 show cross-sectional views of the pixel section 20 and the memory section 30 as AA section to FF section.

First, in the BB sectional view of FIG. 3, the lowermost layer is the common cathode CC. In the upper layer, a portion corresponding to the pixel portion 20 is a resistive layer R ₄ And the emitter cone 22 and the common cathode CC are electrically connected. Emitter cones 22 in the pixel section 20, FEC elements are formed by the first gate G _F and second gate G _S, field emission operation is performed with respect to the anode A _N shown in FIG.

In a portion corresponding to the memory portion 30, a conductor portion 39 is provided on the common cathode CC, and an upper layer
A dielectric layer is formed, between the common cathode CC and the second gate G _S is the capacitor section 31. Further, the second gate G _S forming the capacitor section 31 is connected to the conductor layer 32.
It is connected to the first gate G _F and second gate G _S in the pixel portion 20 by. Therefore, the field emission operation of the pixel unit 20 is controlled according to the voltage supplied from the capacitor unit 31.

[0033] In the portion corresponding to the element Q _1, E in FIG. 6
As shown in the -E cross-sectional view, the scan cathode SC is disposed at the lowermost layer, and the emitter cone 41 is formed on the upper surface thereof with the conductor layer 37 interposed therebetween. The emitter cone 41, the first gate G _F , and the second gate G
_The element portion Q ₁ (FEC) is formed by _S.

[0034] not provided hole in the element Q ₁ in the second gate G _S, by the second gate G _S acts as the anode, the emitted electrons from the emitter cone 41 second
The current reaches the gate G _S , so that a current flows between the second gate G _S and the scan cathode SC.

The second gate G _S of the element portion Q ₁ is electrically connected to the second gate G _S of the adjacent gate G ₃ by the resistor R ₁ . Then, the first gate G _F of the element Q ₁ (which is connected by or conductor layer) are successively from the gate line (G _2), thus the image data to be output to the gate (G ₁ ~G _m) It will be applied to the first gate G _F of the element Q _1.

In a portion corresponding to the element portion Q ₂ , FIG.
-D, the lowermost layer is a common cathode C
C, and an emitter cone 42 is formed on the upper surface with the conductor layer 38 interposed therebetween. The emitter cone 42, the first gate G _F , and the second gate G _S form an element portion Q ₂ (FEC).

[0037] not provided hole in the element portion Q ₂ even second gate G _S, by the second gate G _S acts as the anode, the emitted electrons from the emitter cone 42 second
The current reaches the gate G _S , so that a current flows between the second gate G _S and the common cathode CC. Also been second gate G _S electrically connected to the gate G ₂ by the second gate G _S of the element Q ₂ is the resistance portion R _2.

The portion corresponding to the element section Q ₃ also in FIG. 4 C-
Although located on the common cathode CC as shown in the C sectional view, the conductor layer 33 is formed on the upper surface of the insulating layer Z3,
An emitter cone 43 is formed thereon. The emitter cone 43, the first gate G _F , and the second gate G _S form an element portion Q ₃ (FEC).

[0039] By still the element Q ₂ second gate G _S acts as an anode, electrons emitted from the emitter cones 43 reach the second gate G _S. Therefore, only in FIG. 4, a current flows between the second gate G _S and the conductor layer 33. The second gate G _S of the gate G ₂ by the second gate G _S is the resistance portion R ₃ of the element portion Q ₃
Is electrically connected to

The part corresponding to the element part Q ₄ is indicated by F- in FIG.
It is located on the clear electrode CL as shown as a sectional view F,
A conductor layer 39 is formed on the upper surface via an insulating layer Z3, and an emitter cone 44 is formed on the conductor layer 39. The emitter cone 44 and the first gate G
_An element portion Q ₄ (FEC) is formed by _F and the second gate G _S.

Further, the emitter cone 44 by the first gate G _F is connected to the clear electrode CL by a conductor layer 36, thus the voltage applied to the clear electrode CL of the element Q ₄
Is controlled. And this element part Q ₄
But by the second gate G _S acts as an anode,
Electrons emitted from the emitter cone 44 are supplied to the second gate G
_{Reach S.} Therefore, only in FIG. 7, a current flows between the second gate G _S and the conductor layer 39.

Element parts Q ₁ , Q ₂ , Q ₃ , capacitor part 3
1, and the connection state of the active element Q ₄ are indicated by A-A sectional view of FIG.

The conductive layer 39 serving as the lower layer of the dielectric layer of the capacitor portion 31 so that the conductor layer 39 which emitter cones 44 are formed in the element Q ₄ are seen from Figure 2, as in FIG. 7
And is electrically connected to the common cathode CC. For the thus element Q _4, second gate G _S by the voltage applied to the clear electrode CL - becomes a current flows that between the common cathode CC.

[0044] The conductive layer 33 emitter cones 43 of the element portion Q ₃ is formed as shown in FIG. 4 is continuous to the second gate G _S of the condenser section 31 as can be seen from Figure 2. For the thus element Q _3, a current flows between the field emission operation from the emitter cones 43 of the second gate of the second gate G _S and the capacitor portion 31 of the element portion Q _3.

[0045] Further, the second gate G _S of the first gate G _F of the following element Q ₃ of FIG. 2, element Q ₂ is conductive layer 34
Second gate G _S of which is connected, also, the first gate G _F of the element Q _2, element Q ₁ is connected by a conductor layer 35 by.

FIG. 8 shows an equivalent circuit of the pixel section 20 and the memory section 30 having such a structure. In addition, the parts corresponding to FIGS. 1 to 7 are indicated by the reference numerals of the respective parts. That is, in the memory unit 30 is in the data holding operation is performed by charging and discharging are controlled to the capacitor unit 31 by the switching operation of the element Q ₁ to Q _4, held in the capacitor 31 The pixel unit 20 is driven based on the data (voltage value).

The operation of the memory unit 30 is shown in FIGS.
1 will be described. First a high clearing voltage V _CL than the voltage V _TH (see FIG. 11) is applied to the first gate G _F cl electrode CL of the element Q ₄ as shown in FIG. 10,
The element Q ₄ and the electron emitting state.

[0048] At this time, if you have a sufficient potential to the second gate G _S of the active element Q ₄ attracts electrons, the current flows between the common cathode CC from the second gate G _S of the element portion Q ₄ That is, the potential of the capacitor unit 31 decreases. When the potential of the capacitor portion 31 reaches the electron releasable potential V ₁ (see FIG. 11), stops the emission of electrons from the emitter cone 44 of the active element Q _4, discharge of the capacitor 31 is stopped. In this state, the stored data in the capacitor unit 31 is cleared.

At the next timing, as shown in FIG. 10, the applied voltage V _S of the scan cathode SC is set to the ground potential or the applied voltage V _S ≦ V _G2 −V _TH, and further to the applied voltage V _D according to the image data. A pulse width (that is, PWM-modulated image data) corresponding to the luminance of the image data is applied to the first gate G _F of the gates (G _{1 to} G _m ) (voltage V _D
Is V _D ≧ V _TH ).

[0050] That electrons from the first gate G _F becomes the applied enough, therefore the emitter cone 41 of the element Q ₁ in the application period of the voltage V _D (H-level period) of the voltage V _D is element Q ₁ Release is made.

[0051] Thus a current flows through the resistor portion R _1, lowers the potential of the first gate G _F of the element Q ₂ by the voltage drop. Therefore it would stop electron emission operation of the element portion Q _2. (The state in which scanning is not applied, namely scan voltage V _S is at the H level, the electron-emitting operation of the element portion Q ₁ is in the stopped state, one the element section Q ₂ has an electron emission operation state. )

[0052] When the scan period (scan voltage V _S is L level period) the electron-emitting element portion Q ₂ to stops, will be the potential of the first gate G _F of the element portion Q ₃ increases, the element section Q ₃ Becomes an electron emission state. The clear voltage V is the first gate G _F in the element unit Q ₄ in this period
_CL is not applied, i.e. element Q ₄ are electron emission operation is stopped.

Accordingly, the period during which the element section Q ₃ is in the electron emission state is a charging period for the capacitor section 31.
Then, the charging operation period is set by the pulse width of the data voltage V _D. In other words, the charge on the H-level period of the data voltage V _D is performed.

Therefore, for example, in order that the data voltage V _D is expressed in four stages of gradations, the pulse width becomes P between Wa to Wd.
Assuming that the WM modulation is performed, the charging voltage V _C of the capacitor unit 31 has different values such as Va to Vd according to the pulse widths (Wa to Wd) of the data voltage V _D as shown in FIG. Become.

[0055] hold the potential of the capacitor 31 i.e. becomes the gate potential of the pixel section 20, the amount of electrons corresponding to the gate potential is emitted from the emitter cone 22 with respect to the anode A _N. Accordingly, the displayed pixels are expressed in gradation (luminance) according to the hold potential of the capacitor unit 31.

In this embodiment configured as described above, the memory section 30 is provided corresponding to the pixel section 20 to enable a static display, and the light emitting operation is performed by the memory data (the hold potential of the capacitor section 31). since the light emission period from the application period of the image data V _D by being made longer, it is possible to obtain a sufficient luminance at much lower driving voltage than the dynamic display. Further, since the driving voltage can be set low, the life of the phosphor can be extended.
And since this memory unit is configured using FEC,
It can be manufactured simultaneously in the FEC manufacturing process.

By the way, as shown also in the hold potential V _C of FIG.
When the electron emission of the FED is started, a very small current flows between the gate and the cathode of the FED, so that the capacitor unit 11 is gradually discharged.

If the parameters of each field emission element are set so that this discharge is completed within the scan period of one screen, ie, the period until the next data is written to the pixel portion, the clear electrode CL and the element portion Q ₄ is no longer necessary to perform memory clear (discharge of the capacitor 31) is used to be further simplified configuration clear electrode CL and element Q ₄ as required.

In the embodiment, the memory unit 30 is FE
Although an example in which four C elements are used has been described, four groups of an array having a plurality of FECs may be configured to have similar functions.

[0060]

As described above, in the display device using the field emission device of the present invention, a field emission device (FEC) having a cathode, a control electrode and a focusing electrode for each pixel portion.
A switch element portion formed by using a field emission operation from a cathode to a focusing electrode in accordance with a voltage applied to a control electrode, and a dielectric material between any one of a cathode, a control electrode and a focusing electrode. And a capacitor portion formed so as to be sandwiched therebetween, so that the data held in the data holding portion is supplied to the control electrode in the field emission element of the pixel portion. With this configuration, static display is possible, sufficient luminance can be obtained with a low drive voltage, and the life of the phosphor can be extended by setting the drive voltage low. The data holding unit is configured using the FEC, and the FEC of the pixel unit and the FE of the memory unit are used.
In C, the cathode, control electrode and focusing electrode are respectively
Since they are formed at approximately the same height (that is, at the same layer),
In the FEC manufacturing process, the pixel section and the data holding section
It can be manufactured in a process and at the same time , and the effect of not complicating the manufacturing process is exhibited.

Further, the capacitor section is connected to the cathode
Dielectric is sandwiched between any two of the electrode and focusing electrode
By being formed, the placement efficiency is high and the micro size
It is easy to correspond to the pixel part of
The necessary electrical connection is realized as it is. Further, there is also an effect that the gradation can be easily controlled by holding the potential corresponding to the gradation of the image data in the capacitor section.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a configuration of a main part of an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of a main part of the embodiment.

FIG. 3 is a BB cross-sectional view of a main part of the embodiment.

FIG. 4 is a cross-sectional view taken along line CC of a main part of the embodiment.

FIG. 5 is a sectional view taken along the line DD of the main part of the embodiment.

FIG. 6 is an EE sectional view of a main part of the embodiment.

FIG. 7 is a sectional view taken along line FF of a main part of the embodiment.

FIG. 8 is an equivalent circuit diagram of a main part of the embodiment.

FIG. 9 is an explanatory diagram of a schematic configuration of a display device according to an embodiment.

FIG. 10 is an explanatory diagram of an operation of a main part of the embodiment.

FIG. 11 is an explanatory diagram of a second gate current characteristic of the FEC in the example.

FIG. 12 is an explanatory diagram of an FEC array.

FIG. 13 is an explanatory diagram of a display device using an FEC array.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Memory 3 Timing controller 4 Scan side driver 5 Data side driver 6 Shift register 20 Pixel part 21 Hole 22, 41, 42, 43, 44 Emitter cone 30 Memory part 31 Capacitor part 32, 33, 34, 35, 36 , 37, 38, 39 conductive layers R _1, R _2, R ₃ resistance layer Z1, Z2, Z3 insulating layer _{Q 1, Q 2, Q 3} , Q 4 element G ₁ ~G _m gate lines G _F first gate G _S second gate C ₁ -C _n cathode CC common cathode SC scan cathode CL clear electrode A _n anode

Claims (3)

(57) [Claims] 1. A field emission device having a cathode and the control electrode and the focusing electrode by a plurality group unit, and a pixel portion for forming one pixel by each field emission device performs field emission to the anode electrode, the 1 Cathode to drive the pixel part forming the pixel
Field emission device consisting of a control electrode and a focusing electrode
It provided as the element portion, the cathode and the control electrode of the switching element, or focusing
Formed by sandwiching a dielectric between any two of the electrodes
Display signal applied by the capacitor part
And at least the switch
A part of the field emission device that forms the device portion has its cathode
The electrodes of the field emission element portion of the pixel portion forming one pixel
A control electrode of a field emission device which is configured to conduct with a control electrode and constitutes the switch element portion
And a focusing electrode, which is focused with a control electrode constituting the pixel portion.
The electrodes are formed on the same film formation layer.
A display device using a field emission element characterized Rukoto. 2. The switching device according to claim 1, wherein the switching element comprises a cathode,
Electrodes and two or more switch elements with focusing electrodes.
One of them is to discharge the capacitor part.
2. The switch element according to claim 1, wherein
6. A display device using the field emission device according to 5. 3. The capacitor unit according to claim 1, wherein a voltage value corresponding to a gradation of image data is held in said capacitor unit.
A display device using the field emission device according to claim 2.