JP2831727B2 - Hardware resource allocation support system - Google Patents

Description

The present invention relates to a hardware resource allocation support system in a CAD system that supports hardware architecture design.

(Prior Art) Architectural design is the process of generating a register transfer level configuration of hardware that implements a given specification, and typically evolves the specification into more basic operations between hardware resources, The scheduling considering the execution order of the operation is performed. In addition, resources for constructing a computing unit, a storage element, and a transfer path necessary for executing the operation are performed. here,
The above-mentioned scheduling and resource allocation are not completely independent tasks, but are closely related to each other. For example, when two operations A and B are executed by the same computing unit, these operations cannot be executed simultaneously, and it takes at least two steps to execute.
On the other hand, if one operation unit is assigned to each operation, the execution step of the operation becomes 1, but two operation units are required. In general, the more resources are shared in order to reduce the amount of resources, the greater the number of execution steps of the operation. The more resources that are required to increase the parallelism in order to reduce the number of execution steps of the operation, the required amount of resources is Increase. Generally, when resources are shared, the number of the resources is reduced, but a multiplexer is required for inputting the resources.

While considering the trade-off between the speed (the number of execution steps of the operation) and the amount of resources as described above, the designer creates a specification description in order to design a hardware configuration with the least amount of resources and the degree of parallelism as high as possible. Try.

However, conventionally, when hardware resources are allocated as described above, effective resources are not necessarily allocated due to the fact that the effect of the result on scheduling and the like depends on the experience and intuition of the designer. There was a problem that was not done.

In particular, as the scale of the hardware to be designed increases, the number of combinations for performing the above-mentioned sharing becomes enormous, and appropriate resource allocation is performed from such an enormous number of combinations. There is a limit to making choices based on experience and intuition, and there is a major difficulty here.

(Problems to be Solved by the Invention) As described above, in the conventional architectural design, there is a problem that effective resource allocation is not always performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the related art, and an object of the present invention is to enable a designer to estimate whether the allocation of hardware resources to be performed is appropriate. Accordingly, it is an object of the present invention to provide a hardware resource allocation support system which enables optimization of the number of execution steps and resource amount of an operation.

[Configuration of the invention]

According to a first aspect of the present invention, there is provided a hardware resource allocation support system according to the present invention, wherein scheduling information storage means, evaluation information storage means, and scheduling information storage means are stored in the evaluation information storage means. Means for copying to means,
Resource allocation designating means for instructing hardware resource allocation, and correcting information in the evaluation information storage means in accordance with an instruction from the resource allocation designating means, and attempting a resource allocation operation on the information in the evaluation information storage means. With respect to the resource allocation trial means and the resource allocation result by the resource allocation trial means, regarding the change factors other than the hardware to be allocated, that is, the number of steps and other hardware resources, etc. A change element evaluation means for evaluating the degree of change of the change element.

According to a second aspect of the present invention, there is provided a hardware resource allocation support system, comprising: a scheduling information storage unit; a hardware resource storage unit; Resource allocation executing means for performing resource allocation processing, evaluation information storage means, copying means for copying information from the scheduling information storage means to the evaluation information storage means, and resource allocation designating means for instructing hardware resource allocation Resource allocation trial means for correcting information in the evaluation information storage means in accordance with an instruction from the resource allocation designating means and attempting a resource allocation operation on the information in the evaluation information storage means; Changes in the result of resource allocation by other than the target hardware A change element evaluation means for evaluating the degree of change of the change element in accordance with the resource allocation of the hardware to be allocated with respect to the element, that is, the number of steps, other hardware resources, and the like, and an evaluation of the change element evaluation means are determined. Execution determination means for giving the allocation execution instruction to the resource allocation execution means in accordance with the determination result.

(Operation) According to the present invention, the resource allocation operation is attempted by copying the information in the scheduling information storage means and modifying the information in accordance with an instruction from the resource allocation designating means. With respect to the allocation result, the degree of change of the above-mentioned change element accompanying the resource allocation of the hardware to be allocated is evaluated with respect to the change elements other than the hardware to be allocated, that is, the number of steps and other hardware resources. Therefore, by using the evaluation, the designer can estimate the influence on the number of steps and the amount of hardware resources due to the resource allocation to be performed by the designer. This allows
Effective resource allocation is possible even in a large-scale system.

In addition, by evaluating various resource allocation methods, it can be used to find an optimal resource allocation method.

According to the second aspect of the present invention, the information in the scheduling information storage means is copied, and when there is an assignment display from the resource assignment designating means, a resource assignment operation is attempted by correcting the information in accordance with the instruction, With respect to the result, the degree of change of the above-mentioned change element accompanying the resource allocation of the allocated hardware is evaluated with respect to the change elements other than the hardware to be allocated, that is, the number of steps and other hardware resources, and the evaluation is performed. It is determined whether or not the system is worthy of performing the allocation, and an allocation execution command is given to the resource allocation executing means according to the determination result. The system is designed to run, so designers can experiment with different assignments while maintaining a certain direction. Work can proceed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a hardware resource allocation support system according to one embodiment of the present invention.

The scheduling information storage unit 11 stores the operations executed at each scheduled step in a format as shown in FIG. This information is obtained as a result of, for example, analyzing an algorithm-level description representing hardware operation specifications and performing ASAP scheduling. This operation list table is an operation list,
Each list is configured as "(operation id, type, operation unit id, input 1, input 2, output)". Here, the type indicates whether the operation is addition, subtraction, multiplication, or division.

The hardware resource storage unit 12 stores the arithmetic unit assignment result in the third
It is stored in a format as shown in the figure. Each list in the chart shown in FIG. 3 is configured as "(list of operation unit ids, types, and corresponding operation ids)".

The information shown in FIG. 2 and FIG. 3 is given as an initial value an assignment that does not take into account the assignment of arithmetic units at all, that is, an assignment when each operation is executed by an independent arithmetic unit.

The control information display unit 13 displays the contents of the scheduling information storage unit 11 on a display in the form of a data flow graph. The result of displaying the data of FIG.
It is shown in FIG. As shown in FIG. 3B, the nodes of the graph represent operations, the operation id is shown above the nodes, the step numbers to which the operations belong and the arithmetic unit that executes the operations are shown on the left and right of the nodes.
The id is displayed. The edges connecting the nodes are indicated by the input / output variable names of the nodes. A dotted line across the edge represents a step break.

The data path display unit 14 is a scheduling information storage unit 11
The data path that realizes the operation stored in the data path is displayed. The result of displaying the data of FIGS. 2 and 3 is shown in FIG. In FIG. 5, O1 to O7 are arithmetic units, and r1 to r6 are registers. The line connecting these represents a transfer path.
Here, sharing of registers and transfer paths is not considered, but the data path display unit 14 allows the designer to grasp the outline of the data path.

The hardware resource assignment designation unit 15 is for designating, by a command, an operation that the designer wants to execute by the same arithmetic unit. The designer looks at the display on the control information display unit 13 or the data path display unit 14 while watching the display. I can do that.

Here, the cost evaluator 16 obtains an increase d in the number of operation execution steps when the command input through the hardware resource allocation designator 15 is executed.

The execution determination unit 17 calculates the value d obtained by the cost evaluation unit 16
Is determined to execute the command only when d ≦ D is satisfied. Here, D is a constant given in advance, and can be arbitrarily set by a designer. For example, if D = 1 is set, it is determined to be “executed” only when d = 1 or 0.

The allocation execution unit 18 executes the command based on the determination result of the execution determination unit 17, and executes the scheduling information storage unit 1.
1. Modify the contents of the hardware resource storage unit 12.

In the above configuration, the scheduling information storage unit 1
1. Consider a case where the information shown in FIGS. 2 and 3 is stored in the hardware resource storage unit 12. Now, the designer
While referring to the data flow graph of FIG. 4 or the data path of FIG. 5, it is assumed that the operator to be shared is designated by the command of FIG. The command on the first line in FIG. 6 is id
The operator of “1,2,4,6,7” is shared, and the command on the second line indicates that the operator of id “3,5” is shared. That is, the command in FIG. 6 indicates that an arithmetic unit is constituted by only two ALUs for performing addition and subtraction and ALUs for performing operation.

The cost evaluation unit 16 obtains the increase d of the number of operation execution steps when the command is executed according to the flow of FIG. In other words, the operation is moved so that resource competition by the same arithmetic unit does not occur, and an increase in the number of execution steps is estimated.

In FIG. 7, first, in S701, the contents of the scheduling information storage unit 11 are copied, and thereafter, the processes in S702 and thereafter are performed on the copy information.

In S702, the computing unit assignment unit 16 replaces the computing unit id in the computation list in the scheduling information storage unit 11 having the computing unit id designated by the two commands with the smallest designated computing unit id. . As a result, as shown in FIG. 8, the arithmetic unit id of the list performing the addition / subtraction is “1”, and the arithmetic unit id of the list performing the multiplication is “3”.

Next, in S703, when i = 1, n = N = the total number of steps and Z = φ. Here, i is the step to be processed, N is the total number of steps before the scheduling by this flow, n is the total number of steps after the scheduling, Z
Represents a set of movement target lists.

Then, in S704, a termination condition (i <N) is determined.

In this S704, when i = 1, the result is Yes, so that S70
In step i, in step i, a list having the same operation unit id is obtained for each operation type, the union thereof is set to X, and a set of lists having Z as an input (therefore, the list of lists to be absolutely moved) (Set) is Y.

 Here, when i = 1, X = {(1, +, 1, a, b, f), (2, −, 1, b, c, g)}, Y = φ, Z = φ .

Next, in S706, it is determined whether or not there is a list to be moved (XorY） φ).
Proceed to 707.

In this S707, among the elements of X other than Y,
Of the lists having the operation unit id used in the closest step after step i + 1, the list whose output is referred to most is determined for each operation type, and the set is set to X0.

Here, X0 = {(2, −, 1, b, c, g)} is obtained (since the number of references in step 2 of g> the number of references in step 2 of f).

In the next S708, Z is obtained and moved to step i + 1.

 That is, Z = (X−X0) orY = {(1, +, 1, a, b, f)} moves to step 2.

Next, in S709, i = i + 1 = 2, and the process returns to S704.

When i = 2, in S705, X = {(1, +, 1, a, b, f) (4, +, 1, f, g, i)} Y = {(4, +, 1,1) f, g, i)｝, and in S707, X0 = {(1, +, 1, a, b, f)} is obtained. In S707, when there is only one element other than Y in X, the element is set to X0.

 As a result, in S708, Z = (4, +, 1, f, g, i) moves to step 3.

 Similarly, when i = 3, in S705, X = ｛(4, +, 1, f, g, i), (6, −, 1, i, j, k), (7, +, 1, j, e, l)｝, Y = (6, −, 1, i, j, k).

Then, in step S707, since step i + 1 does not exist, the smallest one of the operation ids is set to X0.

 Therefore, X0 = (4, +, 1, f, g, i).

Thereby, in S708, Z = {(6, −, 1, i, j, k), (7, +, 1, j, e, l)} moves to a new step 4. Then, in step S707, if step i + 1 does not exist, it is newly created and n = n + 1 = 4.

Then, in S705 when i = 4, X = {(6, −, 1, i, j, k), (7, +, 1, j, e, l)}, and in S707, X0 = (6, −, 1, i, j, k) Accordingly, in S708, Z = {(7, +, 1, j, e, l)} moves, a new step 5 is generated, and n = n + 1 =
5 is assumed.

Thereafter, i = i + 1 = 6 is set in S709, and the determination is No in S704.
And it moves to S710.

In this step S710, the increment d of the number of steps is calculated as d = n−
Determined by N.

 Here, d = n−N = 5−3 = 2.

Therefore, the execution determination unit 17 determines that the command in FIG. 6 is not to be executed because d ≦ D = 1 is not established, and
For example, a message such as this command is not excuted since d = 2> D is displayed on the display and transmitted to the designer.

Further, the assignment execution unit 18 is not activated by the judgment of the execution judgment unit 17, and the contents of the scheduling information storage unit 11 and the hardware resource storage unit 12 remain as shown in FIGS.

Next, it is assumed that the designer looks at the above message, tries another allocation, and designates a computing unit to be shared by the command of FIG. This command indicates that a total of three arithmetic units of ALU for performing addition, subtraction, and multiplication are used.

Upon receiving the command, the cost evaluator 16 copies the contents of the scheduling information storage unit 11, and after executing S702 in FIG. 7, the contents of the copy are as shown in FIG. Here, in each step of FIG. 10, there is no list having the same computing unit id, so that X = φ, Y = φ, and S704, 70
Since only the loop consisting of 5,706,709 is repeated, the content of the above copy remains the same in FIG. 10, and n does not change. Therefore, in S710, d = 0 is obtained.

As a result, in the execution determination unit 17, d ≦ D is satisfied,
The assignment execution unit 18 is activated.

The allocation executing unit 18 first stores the copy in the scheduling information storage unit 11. As a result, the contents of the scheduling information storage unit 11 are as shown in FIG.

Further, the allocation execution unit 18 deletes, in the hardware resource storage unit 12, the list having the operation unit id specified by the command except for the list having the minimum operation unit id, and deletes the list in the list. Modify the element of the corresponding operation id list. This flow is shown in FIG.

In FIG. 11, first, for one input assignment designation command, the arithmetic unit designated by this command is assigned.
Let the set of ids be M. According to the command on the first line in FIG. 9, M = {1, 4, 7} is obtained in S111.

In S112, M is determined as the minimum value m of the element, and M0 = M
− {M}, and a set M0 including elements other than m in M is obtained.

 Here, m = 1 and M0 = {4,7}.

Next, in S113, in the hardware resource storage unit 12, the set L of the list having the element of M0 as the operation unit id is set.
Ask for.

 Here, L = {(4, (+), (4)), (7, (+), (7))} is obtained.

Then, in S114, a set T of types in L,
Let O be a set of operation ids corresponding to each of them.

 Here, T = {+}, O = {4,7} is obtained.

In S115, the hardware resource storage unit 12 obtains a list 1 having m as a computing unit id.

 1 = (1, (+), (1)).

Then, in S116, the element of T is added to the type of l,
Is added to the list of the operation ids of the above so as not to allow duplication.

Thus, 1 = (1, (+), (1, 4, 7)), and the element of L is deleted from the hardware resource storage unit 12 in S117. When similar processing is performed for the commands on the second and third lines, the contents of the hardware resource storage unit 12 are finally as shown in FIG.

The results displayed by the control information display unit 13 and the data path display unit 14 are shown in FIGS. 13 and 14.
In this case, although the number of arithmetic units is three, the number of steps remains three, and it can be seen that it can be realized with the shortest steps.

As described above, according to the present embodiment, the designer can automatically know the effect of the designation on the scheduling (the increase in the number of steps) by the system when executing the operation unit assignment. Therefore, the designer can design the architecture in consideration of the trade-off between the speed and the amount of hardware resources.

Further, according to the configuration in which the evaluation means and the assignment execution means are combined as in the present embodiment, the system executes only the assignment that is expected to be effective by the designer, so that the system meets the intention of the designer and achieves efficiency. It is possible to generate a general hardware configuration. In addition, it is possible to find an optimal resource allocation method by evaluating various resource allocation methods using the present invention.

Note that the present invention is not limited to the above embodiment.

In the above embodiment, the scheduling storage unit 11
Although the hardware resource storage unit 12 and the hardware resource storage unit 12 have a separate configuration, a method of integrating such information may be considered.

For example, the following is conceivable in which information on the type of an arithmetic unit is added to the scheduling information in the format shown in FIG.

Here, the operation list is assumed to be composed of ((operation id, operation type), (operation unit id, operation unit type), operand list). From FIG. 15, for example, the ALU of the operation unit id1
It can be seen that the addition, subtraction of id1,2,4 is performed.

From this table, not only the scheduling, but also the type and number of arithmetic units can be known (however, the search efficiency is not very good). Therefore, only the table has the same information as the scheduling storage unit 11 and the hardware resource storage unit 12. Will be.

Further, for example, when considering register allocation, a register id register name is paired with a variable name (a, (10R
1)) can be memorized.

Further, in the above-described embodiment, the parameter D in the cost evaluation unit and the execution determination unit is constant. However, the parameter D may be changed for each instruction of the designer.

Further, in the above-described embodiment, the case of the operation unit assignment has been described.
Other resource allocations may be used. In these cases, it is conceivable that the cost evaluator evaluates the amount of hardware resources such as an increase in the amount of multiplexers due to register sharing and an increase in the amount of drivers due to bus generation.

It is also conceivable that the hardware resource allocation designation unit can designate the cancellation of sharing once performed. In this case, it is conceivable that the cost evaluation unit evaluates an increase in the resource amount due to the release of the sharing and a decrease in the number of steps due to the release of the sharing.

In addition, it goes without saying that a plurality of evaluation criteria may be provided in this cost evaluation unit.

〔The invention's effect〕

As described above, according to the present invention, the resource allocation operation is attempted by copying the information of the scheduling information storage means and correcting the information according to the instruction from the resource allocation designating means. With respect to the result of resource allocation, the degree of change of the above-mentioned change element accompanying the resource allocation of the hardware to be allocated is evaluated with respect to the change elements other than the hardware to be allocated, that is, the number of steps and other hardware resources. Therefore, by using the evaluation, the designer can estimate the influence on the number of steps and the amount of hardware resources due to the resource allocation to be performed by the designer. This enables effective resource allocation even in a large-scale system.

Further, by evaluating various resource allocation methods, the method can be used for finding an optimal resource allocation method.

According to the second aspect of the present invention, the information in the scheduling information storage is copied, and when an allocation instruction is issued from the resource allocation specifying means, the resource allocation operation is attempted by correcting the information in accordance with the instruction. Regarding the result, regarding the change factors other than the hardware to be allocated, that is, the number of steps, other hardware resources, etc.
Evaluate the degree of change of the above-mentioned change element in accordance with the resource allocation of the hardware to be allocated, determine whether or not the allocation is worthy of performing the allocation using the evaluation, and execute the allocation execution command according to the determination result. The system is designed to execute only the assignments that the system is expected to be effective among the assignments that the designer intends to make and that the system intends to make. The design work can be advanced while maintaining the performance.

[Brief description of the drawings]

FIG. 1 is a block diagram of a hardware resource allocation support system according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of information stored in a scheduling information storage unit, and FIG. 3 is stored in a hardware resource storage unit. FIG. 4 is a view for explaining the display contents of the information of FIG. 2 by the control information display section, FIG. 5 is a view for explaining the display contents of the information of FIG. 3 by the data path display section, and FIG. FIG. 7 is an explanatory diagram of a first example of a command input by the hardware resource assignment designating section, FIG. 7 is a flowchart showing a processing flow of the cost estimating section, and FIG. 8 is S7 of FIG.
FIG. 9 is an explanatory diagram showing an execution result of the second example, FIG. 9 is an explanatory diagram of a second example of a command input by the hardware resource allocation specifying unit, and FIG. 10 is stored in the scheduling information storage unit after the command is executed in FIG. FIG. 11 is a flowchart showing a correction flow of the hardware resource storage unit by the computing unit allocating unit, FIG. 12 is an explanatory diagram of information stored in the hardware resource storage unit, and FIG. Is a display content explanatory diagram when the information of FIG. 10 is displayed by the control information display unit, FIG. 14 is a display content explanatory diagram when the information of FIG. 12 is displayed by the data path display unit 14,
FIG. 15 is an explanatory diagram showing an example of an operation list when the scheduling information and the hardware resource information are integrated. 11 ... scheduling information storage unit, 12 ... hardware resource storage unit, 13 ... control information display unit, 14 ...
Data path display unit, 15 hardware resource allocation designation unit, 16 cost evaluation unit, 17 execution determination unit

Claims (2)

(57) [Claims] 1. Scheduling information storage means, evaluation information storage means, copying means for copying information from the scheduling information storage means to the evaluation information storage means, resource allocation designation means for instructing hardware resource allocation. A resource allocation trial unit for correcting information in the evaluation information storage unit in accordance with an instruction from the resource allocation designating unit and performing a resource allocation operation on the information in the evaluation information storage unit; Regarding the resource allocation result,
A change element evaluation means for evaluating the degree of change of the change element associated with the resource allocation of the hardware to be allocated with respect to the change element other than the hardware to be allocated. 2. A scheduling information storage means, a hardware resource storage means, and a resource allocation execution means for performing resource allocation processing on information of the scheduling information storage means and the hardware resource storage means in response to an allocation execution command. Evaluation information storage means; copying means for copying information from the scheduling information storage means to the evaluation information storage means; resource assignment designation means for instructing hardware resource assignment; Resource allocation trial means for modifying the information in the evaluation information storage means and attempting a resource allocation operation on the information in the evaluation information storage means;
Change element evaluation means for evaluating the degree of change of the change element associated with resource allocation of the allocation target hardware with respect to the change element other than the allocation target hardware; and A hardware resource allocation support system comprising: an execution determination unit that provides the allocation execution instruction to the resource allocation execution unit.