JP2829994B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2829994B2 JP2829994B2 JP63295027A JP29502788A JP2829994B2 JP 2829994 B2 JP2829994 B2 JP 2829994B2 JP 63295027 A JP63295027 A JP 63295027A JP 29502788 A JP29502788 A JP 29502788A JP 2829994 B2 JP2829994 B2 JP 2829994B2
- Authority
- JP
- Japan
- Prior art keywords
- pull
- resistor
- bonding pad
- bonding
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特にプルアップ抵抗
又はプルダウン抵抗をオプションで外部導出端子に接続
することができる半導体集積回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a pull-up resistor or a pull-down resistor can be optionally connected to an external lead terminal.
第３図と第４図に従来のプルアップ抵抗又はプルダウ
ン抵抗の内蔵を選択する一従来例を示す。3 and 4 show a conventional example in which a built-in pull-up resistor or pull-down resistor is selected.
第３図はプルアップ抵抗の内蔵を選択する回路図であ
る。第４図は第３図を実施するための簡単なレイアウト
図である。第４図においてボンディングパッド４−１は
第３図の端子３−１でありボンディングパッド４−１か
らのびているアルミニウム配線４−２は第３図のインバ
ータ３−２のゲートにつながっている。アルミ配線４−
３は第３図のプルアップ抵抗３−３につながっている。
第３図において点線をつなぐことによってプルアップ抵
抗の内蔵を選択したことになり、これはデバイス的には
第４図において斜線部のアルミ配線４−４をつなぐこと
によりプルアップ抵抗の内蔵を選択したことになる。FIG. 3 is a circuit diagram for selecting whether to incorporate a pull-up resistor. FIG. 4 is a simple layout diagram for implementing FIG. 4, the bonding pad 4-1 is the terminal 3-1 in FIG. 3, and the aluminum wiring 4-2 extending from the bonding pad 4-1 is connected to the gate of the inverter 3-2 in FIG. Aluminum wiring 4-
Reference numeral 3 is connected to the pull-up resistor 3-3 in FIG.
In FIG. 3, the connection of the pull-up resistor is selected by connecting the dotted lines, which is device-wise. In FIG. 4, the connection of the pull-up resistor is selected by connecting the hatched aluminum wiring 4-4 in FIG. It will be done.
上述した従来の半導体集積回路は拡散工程のアルミ配
線にてプルアップ抵抗又はプルダウン抵抗の内蔵を選択
することができるようになっているので、プルアップ抵
抗又はプルダウン抵抗の内蔵の選択を変更するたびにア
ルミマスクを作らなくてはならず、製品ができ上がるま
で時間が長くなるという欠点がある。In the conventional semiconductor integrated circuit described above, since the built-in pull-up resistor or pull-down resistor can be selected by the aluminum wiring in the diffusion process, each time the selection of the built-in pull-up resistor or pull-down resistor is changed. However, there is a drawback in that the aluminum mask must be made, and it takes a long time to complete the product.
本発明による半導体集積回路は、プルアップ抵抗又は
プルダウン抵抗の内蔵を選択することができる半導体集
積回路において、プルアップ抵抗又はプルダウン抵抗を
介して電源端子にのみ接続された第１のボンディングパ
ッドと、信号入力用又は信号出力用の第２のボンディン
グパッドとを有し、これら第１及び第２のボンディング
パッドが近接配置されていることを特徴とする。A semiconductor integrated circuit according to the present invention, in a semiconductor integrated circuit capable of selecting a built-in pull-up resistor or pull-down resistor, a first bonding pad connected only to a power supply terminal via a pull-up resistor or a pull-down resistor; A second bonding pad for signal input or signal output, and the first and second bonding pads are arranged close to each other.
したがって、第２のパッドに接続されるべき外部リー
ドに第１のパッドもワイヤで接続すれば、プルアップ又
はプルダウン抵抗付の端子とすることができる。Therefore, if the first pad is also connected to the external lead to be connected to the second pad by a wire, it can be a terminal with a pull-up or pull-down resistor.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の構成図である。ボンディ
ングパッド１−１はインバータ１−２につながってい
る。ボンディングパッド１−３はプルアップ抵抗１−４
につながっている。ボンディングパッド１−１はリード
フレーム１−５とボンディングワイヤ１−６でつながっ
ている。プルアップ抵抗１−４を内蔵する場合は、ボン
ディングパッド１−３とリードフレーム１−５をボンデ
ィングワイヤ１−７でつなげばよい。内蔵しない場合
は、ボンディングパッド１−３とリードフレーム１−５
をボンディングワイヤ１−７でつながないようにすれば
よい。ワイヤ１−７を設けるか否かは所謂ワイヤボンデ
ィング工程で選択でき、製品完成を遅くすることはな
い。FIG. 1 is a configuration diagram of one embodiment of the present invention. The bonding pad 1-1 is connected to the inverter 1-2. The bonding pad 1-3 is a pull-up resistor 1-4
Is connected to The bonding pad 1-1 is connected to a lead frame 1-5 and a bonding wire 1-6. When the pull-up resistor 1-4 is incorporated, the bonding pad 1-3 and the lead frame 1-5 may be connected by a bonding wire 1-7. If not, the bonding pad 1-3 and the lead frame 1-5
Are not connected by the bonding wire 1-7. Whether or not to provide the wires 1-7 can be selected in a so-called wire bonding step, and does not delay product completion.
第２図は本発明の他の実施例の構成図である。ボンデ
ィングパッド２−1,2−3,2−５とインバータ２−２、プ
ルアップ抵抗２−4,2−６とは実施例１と同じつながり
になっている。さらにボンディングパッド２−１とリー
ドフレーム２−７とはボンディングワイヤ２−８でつな
がっている。ボンディングパッド２−３、又はボンディ
ングパッド２−５もしくは両パッドをボンディングワイ
ヤ２−９又はボンディングワイヤ２−10でリードフレー
ム２−７につなげることにより抵抗値の異なるプルアッ
プ抵抗を内蔵することができる。FIG. 2 is a block diagram of another embodiment of the present invention. The bonding pads 2-1, 2-3, 2-5, the inverter 2-2, and the pull-up resistors 2-4, 2-6 have the same connection as in the first embodiment. Further, the bonding pad 2-1 and the lead frame 2-7 are connected by a bonding wire 2-8. By connecting the bonding pad 2-3 or the bonding pad 2-5 or both pads to the lead frame 2-7 with the bonding wire 2-9 or the bonding wire 2-10, pull-up resistors having different resistance values can be built-in. .
なお、上述した実施例に限定されず、プルダウン抵抗
についても同様に実施できる。また、パッド１−1,2−
１は入力端子に限らず、出力端子でも、入出力端子でも
よい。Note that the present invention is not limited to the above-described embodiment, and the same can be applied to a pull-down resistor. Also, pads 1-1 and 2-
1 is not limited to an input terminal, and may be an output terminal or an input / output terminal.
以上説明したように本発明はプルアップ抵抗又はプル
ダウン抵抗のついたボンディングパッドを設けることに
よりボンディング工程にてプルアップ抵抗又はプルダウ
ン抵抗の内蔵を選択することができ製品ができあがるま
で時間が短くできる効果がある。As described above, according to the present invention, by providing a bonding pad with a pull-up resistor or a pull-down resistor, it is possible to select a built-in pull-up resistor or a pull-down resistor in a bonding process, thereby shortening the time until a product is completed. There is.
第１図は本発明の一実施例の構成図、第２図は本発明の
他の実施例の構成図、第３図は一従来例の回路図、第４
図は第３図の簡単なレイアウト図である。 １−1,1−3,2−1,2−3,2−5,4−１……ボンディングパ
ッド、１−2,2−2,3−２……インバータ、１−4,2−4,2
−6,3−３……プルアップ抵抗、１−5,2−７……リード
フレーム、１−6,1−7,2−8,2−9,2−10……ボンディン
グワイヤ、３−１……端子、４−2,4−３……アルミ配
線、４−４……選択切り換えアルミ配線。FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, FIG.
The figure is a simple layout diagram of FIG. 1-1, 1-3, 2-1, 2-3, 2-5, 4-1 ... bonding pad, 1-2, 2-2, 3-2 ... inverter, 1-4, 2-4 , 2
-6,3-3 ... pull-up resistor, 1-5,2-7 ... lead frame, 1-6,1-7,2-8,2-9,2-10 ... bonding wire, 3- 1 ... terminal, 4-2, 4-3 ... aluminum wiring, 4-4 ... selection switching aluminum wiring.
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/822 H01L 27/04Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/822 H01L 27/04
Claims (3)
を選択することができる半導体集積回路において、プル
アップ抵抗又はプルダウン抵抗に接続された第１のボン
ディングパッドと、信号入力用又は信号出力用の第２の
ボンディングパッドと、前記第１及び第２のボンディン
グパッドに近接配置されたリードフレームと、前記リー
ドフレームと前記第２のボンディングパッドとを接続す
るボンディングワイヤとを有し、前記リードフレームと
前記第１のボンディングパッドとを接続することにより
前記第１及び第２のボンディングパッドとを相互に接続
可能としたことを特徴とする半導体集積回路。In a semiconductor integrated circuit capable of selecting a built-in pull-up resistor or pull-down resistor, a first bonding pad connected to a pull-up resistor or a pull-down resistor and a first bonding pad for signal input or signal output. 2 bonding pads, a lead frame disposed close to the first and second bonding pads, and a bonding wire connecting the lead frame and the second bonding pad. A semiconductor integrated circuit, wherein the first and second bonding pads can be connected to each other by connecting to a first bonding pad.
は抵抗値の異なる他のプルアップ抵抗又はプルダウン抵
抗に接続された第３のボンディングパッドをさらに有
し、前記第３のボンディングパッドは前記リードフレー
ムに近接配置されており、前記リードフレームと前記第
１及び第３のボンディングパッドの少なくとも一方とを
接続することにより前記第１のボンディングパッドと前
記第２及び第３のボンディングパッドの少なくとも一方
とを相互に接続可能としたことを特徴とする請求項１記
載の半導体集積回路。2. The semiconductor device according to claim 1, further comprising a third bonding pad connected to another pull-up resistor or a pull-down resistor having a different resistance value from the pull-up resistor or the pull-down resistor, wherein the third bonding pad is connected to the lead frame. And the first bonding pad and at least one of the second and third bonding pads are connected to each other by connecting the lead frame to at least one of the first and third bonding pads. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuits can be connected to each other.
された第１のボンディングパッドと、前記第１のボンデ
ィングパッドに近接配置された信号入力用又は信号出力
用の第２のボンディングパッドと、リードフレームと、
前記リードフレームと前記第１のボンディングパッドと
を接続する第１のボンディングワイヤと、前記リードフ
レームと前記第２のボンディングパッドとを接続する第
２のボンディングワイヤとを有し、これによって前記第
２のボンディングパッドが前記プルアップ抵抗又はプル
ダウン抵抗に接続されていることを特徴とする半導体集
積回路。3. A first bonding pad connected to a pull-up resistor or a pull-down resistor, a signal input or signal output second bonding pad disposed adjacent to the first bonding pad, and a lead frame. When,
A first bonding wire that connects the lead frame to the first bonding pad; and a second bonding wire that connects the lead frame to the second bonding pad. Wherein the bonding pad is connected to the pull-up resistor or the pull-down resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63295027A JP2829994B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63295027A JP2829994B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02140964A JPH02140964A (en) | 1990-05-30 |
| JP2829994B2 true JP2829994B2 (en) | 1998-12-02 |
Family
ID=17815376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63295027A Expired - Lifetime JP2829994B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2829994B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4892781B2 (en) * | 2001-01-18 | 2012-03-07 | 富士電機株式会社 | Semiconductor physical quantity sensor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188956A (en) * | 1983-04-11 | 1984-10-26 | Nec Corp | Semiconductor device |
| JPS6122446A (en) * | 1984-07-10 | 1986-01-31 | Asahi Optical Co Ltd | Actuator for two-dimensional drive of pickup for optical disc |
| JPS61173514A (en) * | 1985-01-29 | 1986-08-05 | Matsushita Electric Ind Co Ltd | Signal processing circuit |
| JPS61224446A (en) * | 1985-03-29 | 1986-10-06 | Fujitsu Ltd | Semiconductor integrated circuit |
-
1988
- 1988-11-21 JP JP63295027A patent/JP2829994B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02140964A (en) | 1990-05-30 |
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