JP2826335B2 - Track equalizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line equalizer for correcting a line loss caused by a line length, a wire material, and the like, and particularly to a line in which complicated adjustment work is eliminated and the number of parts is reduced. It relates to an equalizer.

[Conventional technology]

2. Description of the Related Art A conventional line equalizer of this type is known as a device for correcting a line loss due to a line length (wiring length) or a wire material.

One of such line equalizers is configured to prepare a plurality of identification thresholds for a line loss and switch the identification threshold according to the state of the line loss to correct the line loss. is there.

According to the line equalizer, the identification threshold can be switched according to the state of the line, and the line loss can be corrected.

Further, as another line equalizing device, there is a device configured to combine a peak value detecting circuit, an automatic gain control circuit (AGC), and a variable equalizing amplifier circuit to correct a line loss. .

According to the line equalizer, the circuit operates according to the state of the line, operates in an optimum state, and can correct the line loss.

〔Problems to be solved〕

In the former former line equalizer, there is a problem that threshold adjustment is necessary and threshold adjustment is difficult.

In the latter conventional line equalizer, a peak value detection circuit,
Since the line loss is corrected by combining an automatic gain control circuit (AGC), a variable equalizing amplifier circuit, and the like, there is a problem that the number of AGC and variable equalizing amplifier circuits increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a line equalizing apparatus that eliminates the operation of adjusting a threshold value and reduces complicated circuit elements.

[Solutions to solve the problem]

The present invention focuses on the point that in the case of a data stream having a relatively low signal speed (10 MHz or less), it is not necessary to use a complicated equalization technique such as an automatic gradient control circuit in consideration of the frequency characteristics of the line. It was done.

Therefore, in order to achieve the above object, a line equalizer according to the present invention is a line equalizer that adjusts a threshold value for a binary digital signal in accordance with a level change due to a line loss of a digital communication system. A level detection unit for detecting the level of a digital signal input via the first control unit; and a first detection unit for the bias adjustment circuit when the level detected by the level detection unit is smaller than a predetermined value because the line length is long. A high DC level is selected as the bias signal of the above, and when the line length is shorter than the predetermined value because the line length is short, a judgment signal is sent to the bias adjustment circuit so as to select a low DC level as the second bias signal. A determination unit to be output; and a stepwise switching of the values of the first and second bias signals based on a determination signal from the determination unit to provide the digital signal to a digital signal. A bias adjustment circuit for adjusting a direct current bias, and an input signal from a line to which a first or second bias signal from the bias adjustment circuit is applied as a DC bias, and a fixed reference signal for internal processing. And an identification circuit for forming and outputting a signal.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the line equalizer of the present invention.

In FIG. 1, the line equalizer 1 includes a level detector 11.
, A determination unit 12, a threshold adjustment circuit 13, and an identification circuit 14.

The level detector 11 has a function of peak detection and the like, and is configured to detect the level of an input signal 101 input from a line and output a level detection result signal 102. The determination unit 12 is configured to output a determination signal 103 that is in an optimal state according to the level detection result signal (determination signal) 102 from the level detection unit 11. The threshold adjustment circuit 13 is configured to adjust and output a reference signal 104 corresponding to the level detection result signal 102 from the determination unit 12. The identification circuit 14 is configured to compare the reference signal 104 from the threshold adjustment circuit 13 with the input signal 101 from the line to form and output an internal processing signal 105.

 The operation of the embodiment having the above configuration will be described.

The input signal 101 whose level changes according to the line length is input to the level detector 11. The level detection section 11 outputs a level detection result signal 102 and supplies it to the determination section 12. The determination unit 12 determines whether the reference signal 104 to the identification circuit 14 is appropriate based on the level detection result signal 102. For example, when the level of the input signal 101 is small because the line length is long, the determination signal 103 is output to the threshold adjustment circuit 13 so as to reduce the reference signal 104. vice versa,
When the level of the input signal 101 is large, the reference signal 1
The determination signal 103 is output to the threshold adjustment circuit 13 so that 04 becomes larger.

If the determination unit 12 has a hysteresis characteristic, a malfunction does not occur even if the input signal 101 slightly changes.

In the threshold adjustment circuit 13, the identification circuit 14 is
The reference signal 104 is adjusted and output.

The identification circuit 14 is configured by a circuit such as a line receiver, and compares the input signal 101 with the reference signal 104 whose level has been adjusted to form and output an internal processing signal 105.

In the identification circuit 14, the level detection unit 11, the determination unit 12,
Since the reference signal 104 is determined by the threshold adjustment circuit 13, even if the input data level changes due to line loss, it can be identified without being erroneously read.

In the above embodiment, the method of adjusting the reference signal 104 has been described. However, the same effect can be obtained by fixing the reference signal 104, applying a DC bias to the input signal 101, and changing the DC bias of the input signal 101. Is obtained.

In any case, it is enough to switch the reference signal 104 or the DC bias to about two steps,
The configuration is simplified, the number of parts is reduced, and the failure rate can be reduced.

〔The invention's effect〕

As described above, according to the present invention, an optimal signal can be input to the identification circuit according to the state of the line with a simple circuit configuration, so that the number of constituent circuits can be reduced and the failure rate can be reduced.

Further, according to the present invention, even when the input signal level changes, a bias signal having a magnitude following the input signal level is superimposed on the input signal, so that complicated threshold value adjustment is not required, and the number of adjustment steps is reduced. Reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the line equalizer of the present invention. DESCRIPTION OF SYMBOLS 1 ... Line equalization apparatus, 11 ... Level detection part, 12 ... Determining part, 13 ... Threshold adjustment circuit, 14 ... Identification circuit.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Shigeru Fujimoto 3-20-4 Nishishinbashi, Minato-ku, Tokyo Japan Electric Engineering Co., Ltd. (56) References JP-A-62-40849 (JP, A) JP-A-61-258524 (JP, A) JP-A-48-98760 (JP, A) JP-A-60-86911 (JP, A) JP-A-56-89126 (JP, A)

Claims (1)

(57) [Claims] 1. A line equalizer for adjusting a threshold value for a binary digital signal according to a level change due to a line loss in a digital communication system, wherein the level of a digital signal input through a line having a predetermined line length is detected. A level detection unit, when the level detected by the level detection unit is smaller than a predetermined value because the line length is long, a high DC level is selected as a first bias signal for a bias adjustment circuit, A determination unit that outputs a determination signal to the bias adjustment circuit to select a low DC level as a second bias signal when the line length is shorter than the predetermined value because the line length is short; and a determination from the determination unit. The first and second signals based on the
A bias adjustment circuit for adjusting a DC bias applied to a digital signal by changing the value of the bias signal in a stepwise manner; and an input from a line to which the first or second bias signal from the bias adjustment circuit is applied as a DC bias A line equalizer, comprising: a signal and an identification circuit that compares a fixed reference signal to form and output an internal processing signal.