JP2823716B2 - Parallel MSK modulation system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MSK modulation system, and more particularly, to an orthogonality and base of a reference sine wave and a carrier without using a dedicated jig or measuring instrument. The present invention relates to a parallel MSK modulation system capable of adjusting a band multiplication circuit. 2. Description of the Related Art FIG. 8 shows a configuration example of a conventional general parallel MSK modulation system. The input data is divided into an I signal and a Q signal by a serial / parallel converter 101 and supplied to multipliers 121 and 122, respectively. Multiplier 12
1 multiplies the reference sine wave signal COS (ωbt) by the I signal, and the multiplier 122 outputs the Q signal and the −π / 2 phase shifter 12
At step 3, the reference sine wave signal is multiplied by a signal shifted by -π / 2. The multipliers 121 and 122 and the -π / 2 phase shifter 123 constitute a baseband multiplying circuit 102. Further, multipliers 131 and 132, -π / 2 phase shifter 13
3 and the adder 134 constitute the quadrature modulation circuit 103.
The multiplier 131 outputs the output of the multiplier 121 and the carrier signal CO
S (ωat), and the multiplier 132
2 is multiplied by a signal obtained by shifting the phase of the carrier signal by -π / 2 by the -π / 2 phase shifter 133. Multipliers 131 and 1
The multiplied signal obtained at 32 is added at the adder 134 to obtain an MSK output. [0004] As described above, in the conventional parallel MSK modulation system, the reference sine wave of the baseband multiplication circuit and the carrier of the quadrature modulation circuit are each 0 (r).
ad) and -π / 2 (rad).
Therefore, a phase shift circuit is used to obtain it. For example, there is a method of adjusting this portion by itself before configuring the MSK modulation circuit. However, since components for mechanical adjustment are generally used, vibrations that may occur at the time of configuration may be caused. In addition, there is a possibility that the adjustment position may be shifted, or the shift amount may be shifted due to a variation in impedance of a circuit to be connected, and the adjustment may be meaningless. Also, in the method of adjusting after the configuration, there is a problem that a special jig must be manufactured or a measuring instrument must be prepared. An object of the present invention is to provide an MSK modulation system which can easily adjust the orthogonality of a reference sine wave and a carrier wave and a baseband multiplication circuit. [0007] In order to solve the above-mentioned problems, a parallel MSK modulation system according to the present invention comprises a serial-parallel conversion circuit for converting input data into an I signal and a Q signal, and a select signal. Selection mode A for outputting normal data, selection mode B for outputting repeated data having a period twice as long as the data period of the I or Q signal, and selection mode C for outputting fixed level data of a predetermined constant level A sine wave signal from the reference sine wave generation circuit to two outputs from the data adjustment circuit, a reference sine wave generation circuit that outputs a sine wave signal, a cosine wave signal, and a signal of the opposite polarity. Baseband multiplying circuit having first and second multiplying circuits for multiplying a carrier signal and a cosine wave signal, respectively, and an output of the first and second multiplying circuits and a carrier signal And a third and fourth multiplication circuit for multiplying the carrier signal by a signal obtained by shifting the phase of the carrier signal by -π / 2, and adding the output signals of the third and fourth multiplication circuits. A quadrature modulation circuit having an adder circuit for obtaining an MSK output, wherein at the time of quadrature characteristic adjustment, the quadrature modulation circuit and baseband multiplication are performed based on the quadrature modulation output obtained by setting the selection mode C and the selection mode B. The circuit is configured so that the characteristics of the circuit can be adjusted. According to the present invention, a selection mode A for outputting normal data and a selection mode B for outputting repetitive data having a cycle twice as long as the data cycle of the I or Q signal are determined by a data adjustment circuit. Any one of the selection modes C for outputting fixed level data of a fixed level can be set, and a sine wave signal, a cosine wave signal from the reference sine wave generation circuit, and a reverse polarity signal thereof are output to two outputs from the data adjustment circuit. A quadrature of an MSK modulation circuit having a baseband multiplication circuit for multiplication, a multiplication circuit for multiplying an output of the baseband multiplication circuit by a carrier signal, and a quadrature modulation circuit for adding the multiplication circuit output signals to obtain an MSK output. This is a system that allows easy adjustment of characteristics. Therefore, it is configured to adjust the characteristics of the quadrature modulation circuit and the baseband multiplication circuit while monitoring the spectrum information of the quadrature modulation output obtained by setting the data adjustment circuit to the selection mode C and the selection mode B. . Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram of an embodiment of a parallel MSK modulation system according to the present invention. The input data is converted into an I signal and a Q signal in a serial / parallel conversion circuit 1, and passes through a data adjustment circuit 2 to a baseband multiplication circuit 3.
Is input to The multipliers 31 and 32 of the baseband multiplication circuit 3 respectively output the COS from the reference sine wave generation circuit 4.
(Ωbt) and SIN (ωbt) are multiplied by the input signal. The multiplier 51 of the quadrature modulation circuit 5 multiplies the output of the multiplication circuit 31 by the carrier signal COS (ωat). Also,
The multiplier 52 converts the carrier signal into -π by the -π / 2 phase shifter 53.
A signal obtained by performing a phase shift of / 2 is multiplied by an output signal of the multiplier 32. Adder 54 adds the output signals of multipliers 51 and 52 to obtain an MSK output. As described above, the output of the serial-parallel conversion circuit 1 is input to the data adjustment circuit 2. The data adjustment circuit 2 selects the normal data, that is, the data serial-to-parallel converted by the serial-parallel adjustment circuit 1 or another fixed pattern signal described later, based on the pattern selection control signal, and inputs the same to the baseband multiplication circuit 3. On the other hand, the reference sine wave selected by the pattern selection control signal from the reference sine wave generation circuit 4 is input to the baseband multiplication circuit 3,
The output multiplied by both signals is input to the quadrature modulation circuit 5 to generate an MSK signal. The generation of the fixed pattern by the data adjustment circuit 2 can be performed, for example, by the configuration shown in FIG. Also,
FIG. 3 shows the output. Incidentally, actually, it is constituted by two circuits (I and Q channel units). Normal data (I and Q data) and repeated data are input to the selector 21, and one of them is selectively output by a select signal. Here, the repetitive data is a clock generated in the preprocessing timing circuit and has a period 2Tb which is twice the I or Q data period Tb. The analog delay 22 is for adjusting the phase of data to the reference sine wave. The selection of data output from the selector 21 is performed by a select signal as a pattern selection signal. As shown in FIG. 3, three modes are selected by a combination of a data fixed signal as a pattern selection signal and a select signal. Is specified. For example, if the select signal is “L” and the data fixed signal is “H”, the mode A is designated and normal data is output from the data adjustment circuit 2. If the select signal is "H" and the data fixing signal is "H", the mode B is designated and the above-mentioned repeated data is output. Further, if the select signal is “L” or “H” and the data fixing signal is “H”, the mode C is designated, and fixed data (for example, Low) is forcibly output. FIG. 4 shows an example of the configuration of the reference sine wave generating circuit 4 in FIG. 1, and FIG. 5 shows its output.
This circuit is also actually composed of two circuits (I and Q channel units). The sampling data storage unit 41 stores the data of the sampling points of the reference sine wave as shown in FIG. The reference sine wave sent to the multiplying circuit of the I channel is read out by a read control signal to # 1, # 2, #
If the sampling data is sent to the D / A converter 43 on the I channel side via the selector 42 in the order of 3 ... # 8, the sampling data is sent to the Q channel side in the order of # 7, # 8, # 1 ... # 6. The signal is sent to the D / A converter 43 on the Q channel side (selection mode D). The selector 42
Select control is performed by a read circuit 45 that responds to a read control signal (H or L). By doing so, the relative phase difference between these two signals can maintain the orthogonal relationship. If the order of the sampling data on the Q channel side is # 3, # 4, # 5... # 2, it is possible to generate a signal whose phase is inverted (selection mode E). The relation diagram is shown in FIG. Analog delay 46
Is for adjusting the orthogonality of the reference sine waves, and a delayed clock is supplied to the D / A converter 43 as a clock. From the addition theorem of trigonometric functions, COS A · COS B + SIN A · SIN B = COS (A−B) (1) COS A · COS B−SIN A · SIN B = COS (A + B) (2) If A is a carrier ωa and B is a reference sine wave ωb, the result of the multiplication is (ωa + ωb) or (ωa−ω
b) only exists. That is, the frequency is observed by a spectrum analyzer, and the phase shifter 5 as a phase shift circuit is operated so as to satisfy the above condition.
By adjusting 3, the resulting orthogonality between the carrier wave and the reference sine wave is obtained. Therefore, if the reference sine wave generation circuit 4 is in the selection mode D and the data adjustment circuit 2 is in the selection mode C, the condition of the equation (1) is satisfied. The phase shift circuit can be adjusted so as to satisfy the condition of Expression (2). Further, if the output of the reference sine wave generation circuit 4 is stopped and the data adjustment circuit 2 is set to the selection mode B, the bias circuit of the baseband multiplication circuit 3 is adjusted so that the operating point of the switching by the data can be reduced. It can be set to 50% and can be performed while observing with a spectrum analyzer. In other words, setting the switching operation point to the above-mentioned point means that only odd harmonics of the fundamental wave exist in the multiplied output. Therefore, by performing adjustment so as to suppress even-order harmonics most, it is possible to approximate an ideal operation of the multiplier and to suppress unnecessary spurious. The data adjustment circuit 2 is set to a selection mode B,
If the reference sine wave circuit 4 is set to the selection mode D or E,
It is possible to adjust so as to suppress the reference sine wave remaining in the baseband multiplication output and the carrier wave remaining in the quadrature modulation output, and can perform the measurement while observing with a spectrum analyzer. In short, according to the present invention, in order to easily adjust the orthogonality of the reference sine wave and the carrier wave and the characteristics of the baseband multiplying circuit, the data adjusting circuit 2 is used.
As well as normal data (mode A) as well as repetition data (mode B) and fixed data (mode C) as output data to the baseband multiplying circuit 3, the reference sine wave generating circuit 4 It is configured such that signals such as sin, -sin, and cosine wave signals can be selectively output as the reference wave from. That is, when the operation mode of the data adjusting circuit 2 is mode C, the data input to the baseband multiplying circuit 3 is fixed data, irrespective of the characteristics of the baseband multiplying circuit 3, and Vessel 5
1, 52, etc.) can be monitored by observing the MSK output. Therefore, it is possible to adjust while monitoring the MSK output in order to suppress the spurious component related to the carrier caused by the characteristics of the quadrature modulation circuit 5, and to adjust the quadrature characteristics completely. For example, according to the perfect quadrature modulation circuit 5, odd harmonic components centering on the fundamental frequency component appear as line spectrum data in the MSK output, but if harmonic distortion exists in the characteristics of the quadrature modulation circuit 5, the even harmonic components will appear. The components will be mixed. Therefore, if the quadrature modulation circuit 5 is adjusted while monitoring the frequency information of the MSK output using a spectrum analyzer or the like so that the even harmonic components are sufficiently suppressed,
If the reference wave output from the reference sine wave generation circuit 4 is used, a quadrature modulation circuit 5 having excellent orthogonality can be obtained. On the other hand, when the operation mode of the data adjustment circuit 2 is set to mode B, the data “1” and “0” are output from the data adjustment circuit 2 to the multiplier 31 of the baseband multiplication circuit 3.
And 32. The multipliers 31 and 32
When the data from the data adjustment circuit 2 is "1", a multiplication output with the reference wave output from the reference sine wave generation circuit 4 is output to the quadrature modulation circuit 5, but when the data is "0", "0" is output. Is done. Here, in the multipliers 31 and 32, whether the input data is "1" or "0" is determined based on the result of comparison with the threshold value. If the threshold value is not appropriate, the baseband multiplication circuit 3 Unnecessary spurious components are mixed in the output of Therefore, in the present invention, while monitoring the MSK output, the above threshold value is adjusted to set a threshold value that sufficiently suppresses spurious components. As described above, according to the parallel MSK modulation system of the present invention, the adjustment of the orthogonality of the reference sine wave and the carrier and the adjustment of the baseband multiplication circuit are performed only by using only the spectrum analyzer. Can be adjusted without using any jigs or measuring instruments.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram showing an embodiment of a parallel MSK modulation system according to the present invention. FIG. 2 is a block diagram illustrating a configuration example of a data adjustment circuit in the embodiment of FIG. 1; FIG. 3 is a diagram illustrating an output example of a data adjustment circuit in the embodiment of FIG. 1; FIG. 4 is a block diagram showing a configuration example of a reference sine wave generation circuit in the embodiment of FIG. 1; FIG. 5 is a diagram illustrating an output example of a reference sine wave generation circuit in the embodiment of FIG. 1; FIG. 6 is a diagram showing sampling points of a reference sine wave in the embodiment of the present invention. FIG. 7 is a diagram showing a reference sine wave phase relationship between I and Q in the embodiment of the present invention. FIG. 8 is a configuration block diagram of a conventional parallel MSK modulation system. [Description of Signs] 1,101 Serial-parallel conversion circuit 2 Data adjustment circuit 3, 102 Baseband multiplication circuit 4 Reference sine wave generation circuit 5, 103 Quadrature modulation circuits 31, 32, 51, 52, 121, 122, 131, 1
32 multipliers 53, 123, 133 -π / 2 phase shifters 54, 134

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-216555 (JP, A) JP-A-63-119339 (JP, A) JP-A 1-171146 (JP, U) (58) Survey Field (Int.Cl. ⁶ , DB name) H04L 27/00-27/38

Claims (1)

(57) Claims: A serial / parallel conversion circuit for converting input data into an I signal and a Q signal; a selection mode A for outputting normal data by a select signal; A data adjustment circuit having a selection mode B for outputting repeated data having a period and a selection mode C for outputting fixed level data having a predetermined constant level; A baseband having a reference sine wave generating circuit to output, and first and second multiplying circuits respectively multiplying two outputs from the data adjusting circuit by a sine wave signal and a cosine wave signal from the reference sine wave generating circuit And a third and fourth multiplication circuits for multiplying the outputs of the first and second multiplication circuits, a carrier signal, and a signal obtained by shifting the phase of the carrier signal by -π / 2, respectively. A quadrature modulation circuit having a path and adding an output signal of the third and fourth multiplication circuits to obtain an MSK output. A parallel MSK modulation system, wherein the characteristics of the quadrature modulation circuit and the baseband multiplication circuit are adjustable based on the quadrature modulation output obtained by setting B.