JP2820948B2 - Memory card and signal recording device or signal reproducing device using the memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a memory card in which a semiconductor IC memory or the like is mounted on a card body, and records a data signal (especially, an image signal captured by an imaging device such as an electronic camera). The present invention relates to a memory card which can be held and which can be removably inserted into a device for recording / reproducing the data signal.

Further, the present invention relates to a signal recording device or a reproducing device using the memory card as a recording medium.

[Prior Art] Conventional memory cards of this type include Japanese Patent Application Laid-Open No. 62-243486.
As disclosed in Japanese Unexamined Patent Application Publication No. H10-260, there is an apparatus using a semiconductor memory as a recording medium, which is detachable from an imaging apparatus. The semiconductor memory includes n (integer) image memory areas corresponding to the photoelectric conversion units of the imaging device;
A control memory area for storing information indicating a storage state as to whether or not image information is stored in each of the image memory areas, and information such as imaging conditions at the time of imaging of an image stored in the image memory area. ing. Further, the semiconductor memory is
It is detachable integrally with the battery and is driven by a clock that is common or synchronized with the imaging device. That is, an address control unit is provided inside the semiconductor memory.

[Problems to be Solved by the Invention] However, since the size of the above-described semiconductor memory is reduced due to being mounted on the card body, the recording capacity is small.

Therefore, recording and holding of a data signal requiring a large recording capacity, such as an image signal, cannot be performed sufficiently. In addition, since the semiconductor memory described above inputs and outputs signals using digital signals, it requires a large number of signal transmitting and receiving terminals. For this reason, these terminals have a high risk of causing poor contact and lack reliability. Further, when connecting to an external device, there is a fear that a problem such as an increase in insertion / extraction force may occur.

Therefore, an object of the present invention is to record and hold many data signals while the recording capacity itself is relatively small, and to reduce the number of signal input / output terminals, and to record and store data signals. An object of the present invention is to provide a memory card capable of stably holding data, and a signal recording device or a reproducing device using the card as a recording medium.

[Means for Solving the Problems] In order to solve the above problems and achieve the objects, the following measures have been taken. A memory for storing a data signal, a memory control circuit for controlling the input and output of the data signal to and from the memory, an interface for transmitting and receiving the data signal to and from the outside of the card, And a signal compression means for compressing the input signal.
The memory card was configured to include at least one of an A / D converter and an output D / A converter. Further, in the signal recording device using the above-mentioned memory card as a recording medium, a signal recording device of a different type from the signal compression device provided in the memory card is provided in the signal recording device to constitute the signal recording device. Further, in a signal recording device using the memory card as a recording medium, a signal compression unit is provided in the signal recording device, the signal compression unit is a DPCM encoding circuit, and the signal compression unit in the memory card is Huffman encoding. The signal recording device was configured as a circuit. Furthermore, a signal reproducing apparatus using the above memory card as a recording medium, wherein the signal reproducing apparatus is provided with decoding means for decoding a data signal compressed and stored in a memory provided in the memory card. Thus, the signal reproducing apparatus is configured.

[Action] The following action is exhibited by taking the above-described means. The signal compression means for compressing the input data signal is provided in the memory card, so that many data signals can be recorded even in a small-capacity memory. Since the signal input is performed by the analog signal with the converter, the number of input terminals can be reduced. Further, since the output interface section of the memory card is provided with a D / A converter and performs signal output by analog signals, the number of output terminals can be reduced. Moreover, there is no possibility of contact failure, and the reliability of the memory card is improved.

Further, in a signal recording device using this memory card as a recording medium, a signal compression unit of a different type from the signal compression unit provided in the memory card is provided in the signal recording device. , The degree of compression of the data signal can be increased.

In addition, the signal compression means provided in the signal recording device is a DPCM encoding circuit, and the signal compression means provided in the memory card is a Huffman encoding circuit, so that a large amount of data can be stored without increasing the memory in the card. The signal is recorded in the memory.

Further, by providing a decoding means for decoding the data signal compressed and stored in the memory provided in the memory card in the signal reproducing device, the memory card can be reduced in size and weight.

Embodiment FIGS. 1A to 1C show a first embodiment of the present invention, and FIG. 1A shows a configuration of a memory card.
The memory card 1 includes a connection member, an interface circuit 2 that receives an image signal from a signal recording device such as an electronic camera, and encodes and compresses the image signal from the interface circuit 2 based on a certain encoding method. Encoding and compression circuit 3 for converting the encoded code data, an image recording memory 4 for storing the compressed encoded data, and an encoding method using the encoded data output from the memory 4 in the encoding and compression circuit 3 A memory controller 6 for controlling the input / output of signals in the image recording memory 4 together with the interface unit 2; And a power source 7. The image recording memory 4 is composed of an SRAM.

FIG. 1B is a diagram showing a specific example of the encoding and compression circuit 3 shown in FIG.
FIG. 3 is a diagram illustrating an example of an encoding and compression circuit for e Modulation (hereinafter abbreviated as DPCM). The image signal is quantized, for example, nonlinearly by the quantizer 24 via the subtractor 20. Then, they are input to the delay line 21, the delay line 22, and the delay line 23, respectively. For example, the delay line 21 is a one-pixel delay line, the delay line 22 is a 1H (one line) delay line, and the delay line 23 is a 1H (one line) delay line and a one-pixel delay line. Output signals from the delay lines 21 to 23 are multiplied by prediction coefficients a ₁ , a ₂ , and a ₃ by multipliers 25, 26, and 27. The prediction coefficients a _{1 to} a ₃ are, for example, a ₁ = 1, a ₂ = 1, a ₃ = −1. Each image signal multiplied by the prediction coefficients a1 to a3 is added to an adder 28.
Is added. On the other hand, the image signal added by the adder 28 is input to the adder 29 and added to the quantized image signal. On the other hand, subtraction is performed from the image signal input to the subtractor 20 and input from the interface circuit. The image signal, which is the output signal of the subtracter 20, is quantized by the above-described quantizer 24, and then input to the encoder 30. Then, the data is converted into, for example, 4-bit code data by the encoder 30 and then output to the memory 4.

FIG. 1C is a diagram showing an example of the decoding circuit 5 for the two-dimensional prediction DPCM. The image signal decoded by the decoder 40 is input to the delay lines 51 to 53 via the adder 50. The output signal of the delay line 51 to 53 are multiplied by the same prediction coefficients a ₁ ~a ₃ and the prediction coefficient are input to the multipliers 55-57. The outputs from the multipliers 55 to 57 are added by the adder 58. The image signal output from the adder 58 is input to the adder 50. The adder 50 adds the image signal from the decoder 40 and the image signal from the adder 58, and outputs the result to the interface circuit 2.

The present embodiment configured as above has the following operational effects. For example, an 8-bit primary color image signal R, G, B is transmitted from the solid-state memory camera (not shown) which is a signal recording device for recording an image signal to the memory card 1 via the interface circuit 2 to the encoding / compression circuit 3. 3-R, 3-G, 3-
Suppose that they are input to B respectively. Then, the encoding and compression circuit 3 compresses and converts the 8-bit R, G, B signal data into, for example, 2-bit (R), 4-bit (G), and 2-bit (B) code data. The compression-converted code data is recorded in 4-R, 4-G, and 4-B of the image recording memory 4, respectively. The R, G, and B code data read from the image recording memory 4 are input to 5-R, 5-G, and 5-B of the decoding circuit 5. Then, after being converted into the same R, G, B primary color image signals as at the time of input, they are input to a signal reproducing device (not shown) via the interface circuit 2. The input and output of image signals and code data in the interface circuit 2 and the image recording memory 4 are controlled by the memory controller 6.

According to this embodiment, since the image signal is recorded in a compressed state, a large amount of data can be recorded and held even if the image recording memory 4 has a small capacity.

In this embodiment, a two-dimensional predictive DPCM is used as an example of the encoding and compression circuit 3, but a code for performing encoding such as discrete cosine transform, run-length encoding, Huffman encoding, and arithmetic encoding is used. Compressed circuit 3 can be used. Note that, as shown in the above embodiment, the decoding circuit 5 that decodes in accordance with the encoding used in the encoding and compression circuit 3 is used as the decoding circuit 5.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. This embodiment is different from the first embodiment in that a discrete cosine transform coding circuit 3 is used as the coding and compression circuit 3 instead of the two-dimensional predictive DPCM circuit, and that the interface circuit 2 and the coding and compression circuit 3 3 and decoding circuit 5
And the buffer memory 9 is interposed between them. In this embodiment, since the encoding and compression circuit 3 employs the encoding circuit 3 for performing discrete cosine transform, the algorithm becomes more complicated than that using the DPCM. Therefore, before inputting the primary color image signals R, G, B to the encoding and compression circuit 3, for example, the buffer memory 9 for one screen of the primary color image signals R, G, B
−R, 9−G, 9−B are temporarily stored.

The present embodiment has the following operation. For example, it is assumed that 8-bit image signal data R, G, and B from a solid-state memory camera (not shown) are temporarily stored in the buffer memory 9 via the interface circuit 2. Then, the encoding and compression circuit 3 reads necessary image data from an appropriate address in the buffer memory 9 and performs encoding and compression processing. The compressed code data is recorded in the image recording memory 4. The code data read from the image recording memory 4 is input to the decoding circuit 5. Then, after being restored to the image data R, G, B before compression encoding,
The data is input to the buffer memory 9 and then output to the signal recording device or the reproduction via the interface circuit 2.

In the second embodiment, the same effects as those in the first embodiment can be obtained.

FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention. In the second embodiment, the buffer memory 9 is required. In this embodiment, the interface circuit 2, the image recording memory 4, the encoding / compression circuit 3, and the decoding circuit 5 are commonly connected by a bidirectional signal line. And Therefore, a partial area of the image recording memory 4 can be used also as a buffer memory, and the buffer memory 9 of the second embodiment can be omitted.

FIG. 4 is a block diagram showing the configuration of the fourth embodiment of the present invention. This embodiment is an example in which the memory card 1 has a bus configuration. The interface circuit 2, the encoding and compression circuit 3, the image recording memory 4, the decoding circuit 5, and the memory controller 6
They are interconnected by a data bus, address bus, and control bus, and are also connected to the CPU 10.

The memory card 1 thus configured is controlled by the CPU 10 such as input and output of image signals, encoding and compression of image signals, recording in the image recording memory 4, decoding of image data, and the like.

FIG. 5 is a block diagram showing the configuration of the fifth embodiment of the present invention. In this embodiment, a buffer A
This is an example including a / D converter and a D / A converter. R, G, B image signals from a solid-state memory camera (not shown) are input to buffers 210-R, 210-G, 210-B provided in the interface circuit 2 in the state of analog signals, respectively. The image signals input to the buffers are converted into digital signals by A / D converters 220-R, 220-G, and 220-B connected to the buffers. Then, the image signal is recorded in the image recording memory 4 as a digitalized image signal. The image signals read from the image recording memory 4 are supplied to D / A converters 230-R, 230-G, 230-B provided in the interface circuit 2.
After being converted to an analog signal by the buffer 240-R, 2
It is output to an external regenerator (not shown) via 40-G and 240-B.

Therefore, according to this embodiment, since an analog signal is used as an image signal input / output to / from the memory card 1, a number of input / output terminals corresponding to the number of bits of the digital signal are not required. Therefore, the memory card does not have to worry about poor connection or the like.

6 to 9 are diagrams showing examples in which the same interface circuit as that of the fifth embodiment is applied to the interface circuit 2 of the first to fourth embodiments. The memory card 1 shown in FIGS. 6 to 9 has an A / D converter, a D / A
Both converters are provided, but not necessarily both, and may remain digital input or digital output as needed. D / A converter 2
The 30-R, 230-G, and 230-B may not be provided in the interface circuit 2 and may be provided on one of the front and rear of the interface circuit 2.

According to the memory card configured as described above, the effects of both the first embodiment and the fifth embodiment can be obtained.

FIG. 10 is a block diagram showing the configuration of the sixth embodiment of the present invention. In this embodiment, a TV signal conversion circuit is provided in the memory card 1.
This is an example including a TV synchronization signal generating means 61 and a TV synchronization signal generating means 61. The TV signal conversion circuit 60 is interposed between the output side of the image recording memory 4 and the interface circuit 2. Recording of an image signal in the image recording memory 4 is performed in the same manner as in the fifth embodiment. Then, for example, the R, G, B image signals read from the image signal memory 4 are input to the TV signal conversion circuit 60.
Then, it is output to the D / A converter 230 in the interface circuit 2 together with the SYNC signal generated by the TV synchronization signal generating means 61. Then, in the D / A converters 230-R, 230-G, 230-B and the buffers 240-R, 240-G, 240-B, the analog signal T
After being converted into an RGB signal of the V standard, it is output to an input terminal of a color monitor TV or the like (not shown) compatible with RGB.

In the sixth embodiment, the output signal from the image signal memory 4 is directly input to the TV signal conversion circuit 60. However, in the case of the configuration like the memory card shown in the first embodiment, the decoding circuit 5 Is input to the TV signal conversion circuit 60.

In the sixth embodiment, the output of the TV signal conversion circuit 60 is D / A converted.
After D / A conversion of the output from the TV, the TV signal conversion circuit 60 may input the output.

In this embodiment, the output signal of the TV signal conversion circuit 60 is
Although converted to a V image signal, it may be converted to a composite video signal. Such an example is shown in FIG. When converted to a composite video signal, it is input to an input terminal of a color TV monitor or the like that supports composite video input. At this time, the SYNC signal does not need to be output to the outside.

Further, by providing an RF conversion circuit 250 shown by a broken line in the TV signal output section of the interface circuit 2 shown in FIG.
An image can be displayed on a general TV using only a memory card without using a regenerator.

FIGS. 12A and 12B are block diagrams showing a seventh embodiment of the present invention.

In this embodiment, Huffman encoding and decoding are used as the encoding circuit 3 and the decoding circuit 5. The memory card 1 includes an interface circuit 2, a Huffman encoding circuit 3, a memory 4, and a memory controller 6. The Huffman encoding circuit 3 includes a code generation circuit 3a and a clock generation circuit 3b. Describing an animal with the above configuration, a data signal sent from a signal recording device such as an electronic camera is input to the Huffman encoding circuit 3 via the interface circuit 2. The principle of this Huffman coding is described, for example, in Iwanami Koza Vol.4, Information Science and Technology, "Theory of Information and Coding", page 22, where a short code is used for symbols with a high probability of occurrence and a symbol for symbols with a low probability of occurrence. By assigning a long code, the average code length is shortened to perform data compression. here,
According to the input code, a short code “0” is used for a code having a high frequency, and a long code “101” is used for a code with a low frequency.
And so on, and the number of clock pulses equal to the code length is generated from the code generation circuit 3a. The output Huffman code is written into the memory 4, and the clock pulse is input to the memory controller 6, and the address is advanced by the number of clock pulses. As a result, the Huffman-coded data is sequentially written into the memory.
Here, the Huffman coding circuit 3 can be integrated into a one-chip IC, and a reduction in size and weight can be easily achieved.

Next, a decoding circuit for the Huffman code will be described.
Since the decoding process is relatively complicated, FIG. 12 (b)
The Huffman decoding circuit 12 comprises a CPU 13 and a decoding table ROM 14, as shown in FIG.

In decoding, first, a zero address of the decoding table is combined with one bit of the received data, and the address table is referred to. Here, it is determined whether or not the search is completed based on the most significant bit of the obtained data. If the search is completed, the lower data is output as a decoded value. On the other hand, if the search is in progress, the table is referred to using lower data as an address. The table is referred to by combining this value with one bit of the next received data, and it is determined again whether or not the search is completed.
By repeating the above process, the received Huffman code string can be decoded. FIG. 13 is a flowchart showing the process of this Huffman decoding.

Next, an embodiment in which the memory card provided with the Huffman coding circuit shown in the seventh embodiment is used as a recording medium of an imaging device such as an electronic camera which is a signal recording device will be described. As shown in FIG. 14, the memory card 1 is detachably provided to the imaging device 300. The imaging device 300 is C
An image sensor 301 such as a CD, a lens 302 for projecting a subject image onto the image sensor 301, a process circuit 303 for performing processing such as amplification and color separation of the output of the image sensor, an AD converter 304, and data compression by DPCM for the output. And an encoding circuit 305 for performing

On the other hand, the memory card 1 includes a Huffman encoding circuit 3 and a memory 4, and a data signal Huffman encoded by the encoding circuit 3 is recorded in the memory 4. The reproduction of the image data signal written in the memory card 1 is performed by the signal reproducing device 340 as shown in FIG. The signal reproducing device 340 includes a decoding circuit 341 for decoding Huffman codes and a decoding circuit 34 for decoding DPCM.
2.Conversion circuit 343 for converting the decoded image signal into a TV signal
And are provided.

In the solid-state memory camera system configured as described above, the memory card 1
Is dressed.

The subject image is projected on the image sensor 301 by the lens 302,
A video signal corresponding to this image is output from the image sensor 301. This signal is subjected to processing such as amplification and color separation in a process circuit 303, and then converted into a digital signal by an A / D converter 304, and further subjected to DPCM data compression by an encoding circuit 305.

The output of the encoding circuit 305 is subjected to Huffman encoding processing in the encoding circuit 3 in the memory card 1 via the interface circuit 2 and stored in the memory 4.

At the time of reproducing an image of the memory card 1 on which the image signal is recorded, the memory card 1 is mounted on the signal reproducing device 340, and the signal output from the memory 4 is input to the decoding circuit 341 in the signal reproducing device to decode the Huffman code. Further decoding circuit 34
After the DPCM is decoded by 2, it is converted into a TV signal by the conversion circuit 343 and reproduced by the monitor 350.

In the above configuration, only the encoding circuit is provided in the memory card, and the decoding circuit is provided in the signal reproducing device outside the card, but this is realized by a very simple circuit for the Huffman encoding circuit. On the other hand, decoding is a relatively complicated circuit, so that only the encoding circuit is provided in the memory card to reduce the size and weight of the imaging device and the memory card.

In the signal reproducing apparatus having the above-described configuration, two signal decoding means, that is, the Huffman decoding circuit 341 and the DPCM decoding circuit 342 are provided. By inputting the signal of the memory card directly to the memory card, the image signal recorded on the memory card without the Huffman coding circuit 321 (the signal obtained by performing only the DPCM encoding in the imaging device) can be reproduced. It becomes possible. Further, a plurality of various decoding circuits may be provided in the signal reproducing apparatus, and the decoding circuit may be selected according to the type of encoded data recorded in the memory. Further, an adapter for inserting the Huffman decoding circuit between the memory card and the main body of the signal reproducing apparatus may be used.

As described above, by providing the data compression function in both the imaging apparatus main body and the memory card, the degree of compression can be further increased due to the effect of combining the two compression methods. Particularly, when a Huffman encoding type compression circuit is provided in the memory card, Huffman encoding is reversible data compression, so that the image quality does not deteriorate. In addition, the memory card is provided with a very simple Huffman coding circuit, and the imaging device is provided with a relatively complicated DPCM coding circuit. There is a feature that a signal can be recorded.

As described above, Huffman coding can employ various reversible data compression methods such as arithmetic coding.

FIGS. 16 (a) and 16 (b) are diagrams showing the structure of a TV signal output terminal when a memory card is directly connected to a TV or the like. 71 is an output signal pin, 72 is a ground terminal, 73 is an output signal pin 71 for entering and exiting, and the output operation of the memory card 1 is O.
N, OFF switch. The output signal pin 71 is formed by attaching two thin conductive metal springs so as to form a ring shape, and the attached one end is inserted into the memory card 1. The switch 73 is directly connected to a portion of the output pin 71 inserted in the memory card or directly to a signal line in the card. Further, the switch 73 is provided on the side wall of the memory card 1 and slides the switch 73 in the direction of the arrow so that the output signal pin 71 moves in and out of the memory card 1. When connecting directly to the composite video terminal or antenna terminal of the TV, insert the output signal pin 71 into the signal input terminal (not shown) of the TV, and connect the ground terminal 72 to the ground terminal around the signal input terminal. The length of the portion of the output signal pin 71 protruding from the memory card 1 can be adjusted by the switch 73. The switch 73 is held by the memory card 1 by a spring member (not shown), and is slidable with respect to the memory card 1. 74 is a control terminal and 75 is a power supply terminal.

In the memory card 1 configured as described above, the reproduction start signal is obtained by sliding the switch 73 so that the output signal pin 71 protrudes from the memory card 1. Moreover, slide switch 73 to output signal pin.
Until 71 is stored in the memory card 1, it is repeatedly reproduced (output).

FIG. 17 is a diagram showing a configuration of a connection adapter. The connection adapter has a jack 81 for receiving an output signal pin 71 of the memory card, and is electrically connected to the inserted memory card 1 guided by the card insertion guide rail. The structure of the connection portion may be the same terminal structure (for example, a card edge connector) as when connecting to a solid-state memory camera. Then, the image signal input from the memory card 1 is transmitted to the TV via the cable 83.
Etc. are connected to the input terminal. The connection adapter is provided with a power supply circuit 86 for driving the memory card.
The AC power supplied via the power cord 87 is rectified and smoothed and output. The output of the power supply circuit 86 is supplied to the memory card via the power supply terminal 85 and the power supply terminal 75 of the memory card. The power supply circuit 86 is an internal battery or an AC adapter. A control terminal 84 and a control terminal on the memory card side are operated by a playback control switch (not shown) mounted on the side wall of the connection adapter.
Through 74, the playback operation can be controlled.

Note that the connection between the memory card 1 and the playback device is not limited to the above-described configuration. In addition, the first embodiment
The memory 4 used in the seventh embodiment may be a multi (dual) port memory, or may be an SRAM, a DRAM, an EPROM, an EEPROM,
It may be ERRAM or the like. Further, in the above-described embodiment, the description has been made using RGB image data as image data.However, the present invention is not limited to this, and may be, for example, complementary color signal data, or Y, RY, BY, I , Q, and other image signals. In addition, general digital data may be used without being limited to image signals. Of course, various modifications can be made without departing from the spirit of the present invention.

[Effects of the Invention] According to the present invention, since a signal compression means for compressing a data signal input to a memory card is provided, a large amount of data can be stored even in a small-capacity memory. The input interface section is provided with an A / D converter to perform signal input using analog signals, so that the number of input terminals can be reduced. Further, since the output interface section of the memory card is provided with a D / A converter and performs signal output by analog signals, the number of output terminals can be reduced. Moreover, there is no possibility of contact failure, and the reliability of the memory card is improved.

Further, in a signal recording device using this memory card as a recording medium, a signal compression unit of a different type from the signal compression unit provided in the memory card is provided in the signal recording device. Therefore, the degree of compression of the data signal can be increased, and many data signals can be recorded in the memory.

In addition, the signal compression means provided in the signal recording device is a DPCM encoding circuit, and the signal compression means provided in the memory card is a Huffman encoding circuit, without increasing the size of the memory card and the memory in the card. Many data signals can be recorded.

Further, by providing a decoding means for decoding the data signal compressed and stored in the memory provided in the memory card in the signal reproducing device, the memory card can be reduced in size and weight.

[Brief description of the drawings]

1 (a), 1 (b) and 1 (c) are views showing a first embodiment of the present invention. FIG. 1 (a) is a block diagram showing a configuration of a memory card, and FIG. FIG. 3C is a diagram showing the configuration of the circuit, and FIG. 3C is a diagram showing the configuration of the decoding circuit. Fig. 2 ~
FIG. 5 is a block diagram showing the configuration of each of the second to fifth embodiments of the present invention, and FIGS. 6 to 9 are interface circuits of the first to fourth embodiments and the fifth embodiment. FIG. 10 is a block diagram showing a configuration of a sixth embodiment of the present invention, and FIG. 11 is a block diagram showing a configuration of a modification of the sixth embodiment. FIGS. 12 (a) and 12 (b) show a seventh embodiment of the present invention. FIG. 12 (a) is a block diagram showing the configuration of a memory card using a Huffman coding circuit, and FIG. FIG. 13 is a block diagram showing a Huffman decoding process, FIG. 13 is a flowchart showing a Huffman decoding process, and FIG. 14 is a block diagram showing an imaging device as a signal recording device using a memory card of the seventh embodiment as a recording medium. FIG. 15 is a block diagram showing a signal reproducing apparatus using the memory card of the seventh embodiment as a recording medium.
(A) and (b) show the structure of the TV signal output terminal of the memory card, and FIG. 17 shows the structure of the connection adapter. 1 ... memory card, 2 ... interface circuit, 3
... An encoding / compression circuit, 4 a memory, 5 a decoding circuit, 6 a memory controller, 7 a power supply, 9 a buffer memory, 10 a CPU.

Claims (4)

(57) [Claims] A memory for storing a data signal; a memory control circuit for controlling input / output of the data signal to / from the memory; an interface unit for transmitting / receiving the data signal to / from the outside of the card; Signal compression means for compressing the data signal, wherein the interface unit is an input-side A / D converter,
A memory card comprising at least one of an output side D / A converter. 2. A signal recording device using the memory card according to claim 1 as a recording medium, wherein a signal compression unit of a different type from the signal compression unit provided on the memory card is provided in the signal recording device. Signal recording device. 3. A signal recording device using the memory card according to claim 1 as a recording medium, wherein a signal compression means is provided in the signal recording device, and the signal compression means is a DPCM encoding circuit. A signal recording device, wherein the signal compression means is a Huffman encoding circuit. 4. A signal reproducing apparatus using the memory card according to claim 1 as a recording medium, wherein the signal reproducing apparatus decodes a data signal compressed and stored in a memory provided in the memory card. A signal reproducing device comprising means.