JP2818418B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an internal address counter and a technique for improving the operability of an access operation to such a semiconductor memory device. The present invention relates to technology that is effective when applied to a FiFo memory that inputs and outputs in a format.

(Prior art)

When transferring data between multiple devices or functional blocks with different data processing speeds and transfer speeds, FiFo memory etc. can be used as buffer memory to absorb such differences in capabilities and speeds .

The FiFo memory includes, for example, a memory cell array in which a plurality of memory cells are arranged in a matrix, an address decoder for addressing the memory cells included in the memory cell array, and a write / read operation for performing a write / read operation on the addressed memory cells. And a read address counter and a write address counter for internally generating an access address. The read address counter sequentially increments the read address for each data read operation and supplies it to the address decoder, and the write address counter sequentially increments the write address for each data write operation and supplies it to the address decoder. Each address counter is constituted by a ring counter having a bit number corresponding to the storage capacity of the memory cell array. When data is empty, the values of the read address counter and the write address counter match, the value of the write address counter is incremented each time writing is performed, and the value of the read address counter is incremented each time reading is performed. You. The values of the read address counter and the write address counter are always monitored internally, and if the values match during a write operation, a new write cannot be accepted. Inform equipment and functional modules. If the two values match during the read operation, the data to be read no longer exists, and this state is notified to the device or function module from which the data is read by an empty signal.

Examples of documents describing FiFo memory include “Nikkei Electronics” No. published by Nikkei McGraw-Hill.
No. 423 (issued June 15, 1987).

[Problems to be solved by the invention]

However, in the conventional FiFo memory, since the order of reading and writing data is uniquely determined by the built-in address counter as described above, it cannot respond to a random access request to a memory cell at all. For example, when it is necessary to check data stored in the middle of the FiFo memory due to system operation, it is necessary to wait until the necessary data is output in order. Furthermore, if unnecessary data is generated in the middle due to an error in the system operation, etc., it is necessary to read all the unnecessary data in order and update the value of the read address counter in order to clear the unnecessary data. Has been found by the inventor to be time consuming and hinder real-time processing of data.

An object of the present invention is to provide a semiconductor memory device that can perform random access even when the order of reading and / or writing data is specified by a built-in address counter. Another object of the present invention is to provide a semiconductor memory device that can easily perform substantial clearing of data even when the order of data reading and / or writing is defined by the value of a built-in address counter. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows.

That is, in a semiconductor memory device in which the order of data reading and / or writing is defined by a built-in address counter, a selecting means for selecting an output address signal of the address counter and an address signal supplied from the outside is provided. When the external address signal is adopted as the access address signal by the means, the updating operation of the address counter can be suppressed and controlled. In the semiconductor memory device configured as described above, when an arbitrary address other than the address indicated by the address counter is accessed based on the external address signal, the physical address space of the semiconductor memory device and the reference of a required address to be accessed are determined. Considering the case where certain address information is required externally, it is desirable that the information held in the address counter be readable to the outside via the external data input / output terminal.

Also, in a semiconductor memory device in which the order of data reading and / or writing is defined by a built-in address counter, the value of the address counter can be externally rewritten via an external data input / output terminal. In the semiconductor memory device configured as described above, when the value of the address counter is rewritten, the value of the address counter is determined via the external data input / output terminal, considering that the state of the address counter needs to be known from outside. It is desirable to be able to read externally.

(Operation)

According to the above-described means, by causing the selecting means to select an external address signal, required data can be obtained from an arbitrary address other than the address while maintaining the address indicated by the address counter. And / or random access is possible even in a semiconductor memory device in which the order of writing is defined by a built-in address counter.

Further, when unnecessary data is generated in the middle of the stored data, the address counter is forcibly rewritten from the outside, thereby achieving a simple clearing process of the data.

Embodiment 1 FIG. 1 is a block diagram of a FiFo memory according to an embodiment of the present invention. The FiFo memory 1 shown in FIG.
Although not particularly limited, it is one functional module included in the microcomputer or processor 2 shown in FIG. Although not particularly limited, the processor 2 shown in FIG. 2 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

FIG. 2 representatively shows a central processing unit 3 and a serial input circuit 4 in addition to the FiFo memory 1. The serial input circuit 4 receives the received data RxD
Synchronizes or restores the captured data, converts the captured data into parallel data, and outputs the data. The FiFo memory 1 is used as a buffer memory for storing data supplied from the serial input circuit 4. The FiFo memory 1 includes an interface unit on the serial input circuit 4 side and an interface unit on the central processing unit 3 side.

The serial input circuit 4 side interface unit is supplied with the parallel-converted received data Drx from the serial input circuit 4 and also supplied with a push signal PUSH instructing the FiFo memory 1 to write the received data Drx. . A full signal FS for notifying that there is no empty memory cell in the FiFo memory 1 is supplied from the interface unit on the serial input circuit 4 side to the serial input circuit 4.

The interface unit on the central processing unit 3 side includes an address bus.
When the data Di is exchanged with the central processing unit 3 and the supply of the address signal Ai via the ABUS and the data bus DBUS, a predetermined bit of the address signal Ai is supplied to the decoder 5.
Receive the control signals AA and CA generated by decoding in step (1), and further receive the read / write signal R / W. FiFo memory 1 from the central processing unit 3 side interface unit to the central processing unit 3
Signal for notifying that there is no data to be read any longer, and the central processing unit 3
An access inhibition status signal INH for instructing the access operation of the FiFo memory 1 to be inhibited is supplied.

Although not particularly limited, the central processing unit 3 controls the entire processor and also performs a protocol process on the received data RxD.

Next, the details of the FiFo memory 1 will be described with reference to FIG. The FiFo memory 1 basically performs input / output of data in a first-in first-out format, and is further configured so that the central processing unit 3 can perform random access and clear processing of unnecessary data.

In FIG. 1, reference numeral 10 denotes a memory cell array in which a plurality of rewritable memory cells are arranged in a matrix. Addressing of required memory cells included in the memory cell array 10 is performed by the address decoder 11. A read / write circuit 12 reads / writes data from / to the memory cell addressed by the address decoder 11.

An address signal Ai for random access by the central processing unit 3 is supplied to an address input buffer 15. Also, to internally generate an access address for inputting / outputting data to / from the FiFo memory 1 in a first-in first-out format,
The memory includes a read address counter 13 and a write address counter 14 which are configured by a ring counter having a bit number corresponding to the storage capacity of the memory cell address 10. The write address counter 14 sequentially increments and outputs the write address Aw for each data write operation in the first-in first-out format. The increment operation of the write address counter 14 is controlled by a control signal φ output from the controller 17.
Indicated by wi being asserted. The read address counter 13 sequentially increments and outputs the read address Ar for each data read operation in the advance format. The increment operation of read address counter 13 is instructed by assertion of control signal φri output from controller 17.

The address signal Ai output from the address input buffer 15, the address signal Ar output from the read address counter 13, and the address signal Aw output from the write address counter 14 are selected by the selector 16 and sent to the address decoder 11. Supplied. The selection control of the selector 16 is performed according to a control signal φs of a plurality of bits output from the controller 17.

The values of the read address counter 13 and the write address counter 14 are matched in the initial state, and the address signal Ar output from the read address counter 13 and the address signal Aw output from the runt address counter 14 are always The data is supplied to a comparison / judgment circuit 18 and the coincidence / mismatch is constantly monitored. The comparison determination circuit 18 sets the full signal FS to a high level in order to notify the serial input circuit 4 of a state in which new writing cannot be accepted if the values Ar and Aw match during the first-in-time writing operation. If the values Ar and Aw match in the read operation of the first-out format, the empty signal ES is asserted to a high level in order to notify the central processing unit 3 that there is no longer data to be read. Although the comparison judgment circuit 18 is not particularly limited,
A first-in write operation is detected based on an increment instruction of the write address counter 14 by the control signal φwi, and a first-read operation is detected based on an increment instruction of the read address counter 13 by the control signal φri.

The read / write circuit 12 is interfaced to a data bus DBUS via a data input / output buffer 20 used for a memory read access and a random access of a first-in-first-out type by the central processing unit 3. Serial input circuit 4 via data input buffer 21 used for memory write access
Interfaced to Data input / output control for the data input / output buffer 20 is performed by a control signal φ output from the controller 17 according to the level of the read / write signal R / W.
i, φo. Also, the data input buffer 21
Is controlled by a control signal φp output from the controller 17. Although not particularly limited, the read / write control of the read / write circuit 12 is performed by the central processing unit 3 at the time of the advance type memory read access and random access by the control signal output from the controller 17 according to the level of the read / write signal R / W. The write control of the read / write circuit 12 is specified by the control signal φp when the serial input circuit 4 accesses the memory write in the first-in-first-out format.

The read address counter 13 and the write address counter 14 are coupled to a data input / output buffer 20, and the central processing unit 3 reads the address signals Ar and Aw held by the data input / output buffer 20, and the central processing unit 3 forcibly reads the values. And can be rewritten. Read address counter 13 coupled to data input / output buffer 20
Are controlled by a control signal φac output from the controller 17. Similarly, the input / output gate of the write address counter 14 coupled to the data input / output buffer 20 controls the control signal φwa output from the controller 17.
Opening / closing is controlled by c.

Here, the control signal AA output from the decoder 5
Indicates the address signal of the FiFo memory 1 by its high level.
It is regarded as a signal indicating random access by Ai. When the control signal AA is asserted to a high level, the controller 17
Select and output the address signal Ai. The read / write operation in this random access is a read / write signal
Indicated by R / W. Accordingly, when a memory read operation is instructed, control signals φr and φo are asserted, and control signals φw and φi are negated. When a memory write operation is instructed, control signals φr and φo are negated, and control signals φw and φi are asserted.

The 2-bit control signal CA output from the decoder 5
Is a control signal for instructing access of the read address counter 13 and the write address counter 14. One predetermined bit included in the control signal CA is regarded as a bit instructing access to the read address counter 13 by its high level, and the other one bit is regarded as a bit instructing access to the write address counter 14 by its high level. . When the access to the read address counter 13 is instructed by the control signal CA, the controller 17 asserts the control signal φac to open an input / output gate (not shown) of the read address counter 13. When the access to the write address counter 14 is instructed by the control signal CA, the controller 17 asserts the control signal φwac to open an input / output gate (not shown) of the write address counter 14. The read / write operation at this time is instructed by the read / write signal R / W, and according to this, one of the control signals φi and φo is asserted, thereby controlling the data input / output direction in the data input / output buffer 20. Is done. When the read address counter 13 and the write address counter 14 are accessed, both the control signals φr and φw are negated.

When the read operation is instructed by the read / write signal R / W while the control signal AA is negated to low level, the FiFo memory 1 reads the read address counter 13.
Is set to the read operation mode in the first-out format in accordance with the output address signal Ar of the above. As a result, when the control signal φri is asserted, the read address counter 13 is incremented, and the address signal Ar output from the incremented read address counter 13 is selected by the selector.
The data is supplied to the address decoder 11 via 16.

Push signal PUSH supplied from serial input circuit 4
Is regarded as a signal indicating a write operation mode in a first-in first-out format in accordance with the output address signal Aw of the write address counter 14 at its high level. Controller 17
Asserts the control signal φwi when the push signal PUSH is asserted to a high level, whereby the write address counter 14 is incremented, and the address signal Aw thus obtained is supplied to the address The data is supplied to the decoder 11.

Since the FiFo memory 1 of this embodiment can be accessed from both the central processing unit 3 and the input circuit 4 serially, there is no particular limitation to avoid contention for access from both. By FiFo
An access prohibition status signal INH for prohibiting access to the memory 1 is provided. The logic of this conflict avoidance is
Although not particularly limited, the access request from the serial input / output circuit 4 is prioritized, and the access inhibition status signal INH is asserted, for example, in response to the assertion period of the push signal PUSH.

 Next, the operation of the above embodiment will be described.

The serial input circuit 4 asserts the push signal PUSH on condition that the full signal FS is negated, and supplies the received data Drx to the FiFo memory 1. This allows FiFo
The memory 1 sequentially increments the write address counter 14 and sequentially stores the received data Drx in the memory cell array 1.
Stored in 0.

The central processing unit 3 instructs the FiFo memory 1 to perform a read operation in a first-out format on the condition that the empty signal ES and the access prohibition status signal INH are negated. As a result, the FiFo memory 1 increments the read address counter 13 while increasing the memory cell array.
The received data stored in 10 is read out in order.

Here, a description will be given of an operation of clearing unnecessary data generated in the middle of the received data stored in the memory cell array 10 due to an error in the system operation or the like.
For example, as shown in FIG. 5A, when the read address counter 13 and the write address counter 14 point to certain values Ar and Aw, data in the areas ED1 and ED2 in the address space of the memory cell array 10 becomes unnecessary. In this case, the central processing unit 3 may rewrite the value of the read address counter 13 to Ar 'and rewrite the value of the write address counter 14 to Aw', as shown in FIG. 5 (B). . When the values of the read address counter 13 and the write address counter 14 are rewritten in this manner, the received data Drx subsequently given from the serial input circuit 4 becomes
The unnecessary data remaining in the area ED2 is sequentially written from the address of the value Aw 'indicated by the write address counter 14, and is ignored. After that, the memory cell array
When the central processing unit 3 reads the received data stored in the storage device 10 in advance, the read address counter 13
Are read out sequentially from the address of the value Ar ′ indicated by, and the data remaining in the area ED1 is ignored. Therefore, even if it is not necessary to read out all unnecessary data in order and update the value of the read address counter 13, the central processing unit 3 merely performs an operation of forcibly rewriting the values of the read address counter 13 and the write address counter 14 to the unnecessary data. Substantial clear processing can be easily performed.

When rewriting the values of the read address counter 13 and the write address counter 14 in this clearing process, if the central processing unit 3 needs to know the states of the address counters 13 and 14, the central processing unit 3 sets the read address counter 13 Read access is made to the value of the write address counter 14, and the values Ar 'and Aw' to be rewritten are calculated based on the read values Ar and Aw. When read access of the address counters 13 and 14 is required,
For example, when the central processing unit 3 recognizes only the packet number, the byte number, or the word number of the unnecessary data, the physical address space of the memory cell array 10 and the value A to be calculated are determined.
It is assumed that it is necessary to obtain values Ar and Aw to be the references of r 'and Aw'.

Next, when it is necessary to check data stored in the middle of the FiFo memory 1 due to the system operation, the central processing unit 3 randomly accesses the FiFo memory 1 by the address signal Ai and reads required data. . In the read operation at this time, the control signal φri is not asserted, whereby the value of the read address counter 13 is maintained as it is. When the central processing unit 3 needs the physical address space of the FiFo memory 1 and address information serving as a reference of a required address to be accessed at the time of the random access, the central processing unit 3 reads the read address counter 13 and the write address. The value of the counter 14 can be read by read access.

According to the above embodiment, the following effects can be obtained.

(1) By causing the selector 16 to select the external address signal Ai, the central processing unit 3
13 and the address indicated by the write address counter 14 can be obtained, and the required data can be obtained from any address other than the address indicated by the address. Random access is also possible in the FiFo memory 1 specified by the value.

(2) When unnecessary data occurs in the middle of the data stored in the memory cell array 10, the value of the read address counter 13 and / or the write address counter 14 is forcibly rewritten under the control of the central processing unit 3. By doing
Substantial clearing of data in the FiFo memory 1 can be easily performed.

(3) Due to the above operation and effect, the FiFo capable of random access and arbitrary clearing of unnecessary data by the central processing unit 3 is possible.
When the memory 1 is used as a buffer memory of the serial input circuit 4 and the central processing unit 3 intends to perform protocol processing on the received data, the central processing unit 3 randomly accesses the FiFo memory 1 and includes it in the received data. The protocol processing can be performed by arbitrarily obtaining information such as the control field to be processed, and as a result, unnecessary data such as received data and transmission source identification data included in the received data that is unnecessary is used as a buffer memory. Clear processing can be easily performed on the memory 1. Therefore, it is not necessary to transfer all the data received in the FiFo memory 1 to a local memory or the like and then perform the protocol processing. This makes it possible to increase the efficiency of the protocol processing and to simplify the system therefor.

Embodiment 2 FIG. 3 is a block diagram of a FiFo memory according to another embodiment of the present invention. FiFo memory 31 shown in FIG.
Although not particularly limited, it is one peripheral device included in the microcomputer system shown in FIG. 4, and is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

FIG. 4 representatively shows, in addition to the FiFo memory 31, a processor 33 and a serial input circuit 34 as a bus master module, and a bus arbiter 32 for arbitrating bus rights, which are a data bus DBUS and an address bus ABUS. ,
And the control bus CBUS. The processor 33 and the serial input circuit 34 output bus request signals BREQ ₁ and BREQ ₂ as signals requesting a bus right, and receive a bus request signal BREQ ₁ and BREQ ₂ for the bus arbiter 32.
Are the bus acknowledge signals BACK ₁ and BACK for exclusively recognizing the bus right to the processor 33 and the serial input circuit 34.
Outputs ₂ .

The serial input circuit 34 synchronizes or restores the received data RxD supplied in a bit serial manner, captures the data, converts the captured data into parallel, and outputs the converted data. FiFo memory 31
Is used as a buffer memory for storing data supplied from the serial input circuit. Although not particularly limited, the processor 33 also performs data processing such as protocol processing on received data stored in the FiFo memory 31. The FiFo memory 31 is constituted by a single chip or a single pellet, and has a single interface unit used for general purposes. This interface section
The data bus DBUS, the address bus ABUS, and the control bus CBUS are coupled. The FiFo memory 31 receives the read / write signal R / W output from the processor 33 and the serial input circuit 34 via the control bus CBUS, and also checks whether there is no empty memory cell in the FiFo memory 31 externally, especially the serial input circuit. A full signal FS for informing the control bus CBUS is output to the control bus CBUS, and an empty signal ES for notifying the processor 33 in particular that there is no more data to be read out in the FiFo memory 31 is output to the control bus CBUS. The FiFo memory 31 receives control signals AA and CA generated by decoding predetermined bits of the address signal Ai output from the processor 33 and the serial input circuit 34 by the decoder 35.

Next, the details of the FiFo memory 31 will be described with reference to FIG. The FiFo memory 31 basically performs input / output of data in a first-in first-out format, and is further configured so that the processor 33 can perform random access and clear processing of unnecessary data.

In FIG. 3, reference numeral 40 denotes a memory cell array in which a plurality of rewritable memory cells are arranged in a matrix. Addressing of required memory cells included in the memory cell array 40 is performed by an address decoder 41. The read / write circuit 42 reads / writes data from / to the memory cells addressed by the address decoder 41.

An address signal Ai for random access by the processor 33 is supplied to an address input buffer 45. Further, in order to internally generate an access address for inputting / outputting data to / from the FiFo memory 31 in a first-in first-out format, a read address counter 43 and a write address counter 43 each including a ring counter having a bit number corresponding to the storage capacity of the memory cell array 40 are provided. It has 44. The write address counter 44 sequentially increments and outputs the write address Aw for each data write operation in the first-in first-out format. The increment operation of the write address counter 44 is instructed by asserting the control signal φwi output from the controller 47. The read address counter 43 sequentially increments and outputs the read address Ar for each data read operation in the first-in first-out format. The increment operation by the read address counter 43 is instructed by the assertion of the control signal φri output from the controller 47.

An address signal Ai internally taken from the address input buffer 45, an address signal Ar output from the read address counter 43, and a write address counter.
The address signal Aw output from 44 is selected by the selector 46 and supplied to the address decoder 41. The selection control of the selector 46 is performed according to a control signal φs of a plurality of bits output from the controller 47.

The values of the read address counter 43 and the write address counter 44 match in the initial state, and the address signal Ar output from the read address counter 43 and the address signal Aw output from the write address counter 14 are always It is supplied to a comparison / judgment circuit 48 and the coincidence / mismatch is constantly monitored. The comparison determination circuit 48 sets the full signal FS to a high level to notify the serial input circuit 34 of a state in which new writing cannot be accepted if the values Ar and Aw match during a first-in-time write operation. If the values Ar and Aw match during the read operation of the first-out format, an empty signal ES for notifying the processor 33 of a state in which data to be read no longer exists is asserted to a high level. Note that, although not particularly limited, the comparison determination circuit 48 detects a write operation of a first-in first-out format based on an increment instruction of the write address counter 44 by the control signal φwi, and reads a read address counter by the control signal φri.
Based on the increment instruction of 43, the read operation of the advance format is detected.

The read / write circuit 42 is interfaced to a data bus DBUS via a data input / output buffer 50.
Data input / output control for the data input / output buffer 50 is performed by control signals φi and φo output from the controller 47 in accordance with the level of the read / write signal R / W. The read / write control of the read / write circuit 42 is instructed by control signals φr, φw output from the controller 47 according to the level of the read / write signal R / W.

The read address counter 43 and the write address counter 44 are coupled to the data input / output buffer 50, and the processor 33 reads the address signals Ar and Aw held by the data input / output buffer 50, and the processor 33 forcibly rewrites the values. You can do it. The input / output gate of the read address counter 43 coupled to the data input / output buffer 50 controls the control signal φ output from the controller 47.
Opening / closing is controlled by ac. Similarly, the input / output gate of the write address counter 44 coupled to the data input / output buffer 50 is controlled to open and close by a control signal φwac output from the controller 47.

Here, the control signal AA output from the decoder 35
Signals the FiFo memory 31 by its high level.
It is regarded as a signal indicating random access by Ai. When the control signal AA is asserted to a high level, the controller 47
Select and output the address signal Ai. The read / write operation in this random access is specified by a read / write signal R / W output from the processor 33.
Accordingly, when a memory read operation is instructed, control signals φr and φo are asserted and control signals φw and φi are asserted.
Is negated. When a memory write operation is instructed, control signals φr and φo are negated and control signal φ
w and φi are asserted.

The 2-bit control signal CA output from the decoder 35
Is a control signal for instructing access of the read address counter 43 and the write address counter 44. One predetermined bit included in the control signal CA is regarded as a bit instructing access to the read address counter 43 by its high level, and the other one bit is regarded as a bit instructing access to the write address counter 44 by its high level. . When access to the read address counter 43 is instructed by the control signal CA, the controller 47 asserts the control signal φac to open an input / output gate (not shown) of the read address counter 43. When the access to the write address counter 44 is instructed by the control signal CA, the controller 47 asserts the control signal φwac to open an input / output gate (not shown) of the write address counter 44. The read / write operation at this time is instructed by the read / write signal R / W, and according to this, one of the control signals φi and φo is asserted to control the data input / output direction in the data input / output buffer 50. Is done. When the read address counter 43 and the write address counter 44 are accessed, both the control signals φr and φw are negated.

When the read operation is instructed by the read / write signal R / W while the control signal AA is negated to the low level, the FiFo memory 31 reads the read address counter 43.
Is set to the read operation mode based on the first-out format in accordance with the output address signal Ar. As a result, when the control signal φri is asserted, the read address counter 43 is incremented, and the address signal Ar output from the incremented read address counter 43 is selected by the selector.
The data is supplied to the address decoder 41 via 46.

When the write operation is instructed by the read / write signal R / W while the control signal AA is negated to the low level, the FiFo memory 31 stores the write address counter 44.
In accordance with the output address signal Aw. As a result, when the control signal φwi is asserted, the write address counter 44 is incremented, and the address signal Aw output from the incremented write address counter 44 is changed to the selector 46.
Is supplied to the address decoder 41 via the.

The FiFo memory 31 of this embodiment is made accessible to both the processor 33 and the input circuit 34 serially through a common interface unit, but the bus right of the processor 33 and the serial input circuit 34 is exclusively controlled by the bus arbiter 32. As a result, the contention for access to the FiFo memory 31 from both the processor 33 and the serial input circuit 34 is avoided by the bus arbiter 32 in bus arbitration.

 Next, the operation of the above embodiment will be described.

The serial input circuit 34 asserts the bus request signal BREQ ₂ when the full signal FS is not asserted,
When the bus right is granted in response to this request, the address signal Ai that can set the control signal AA to low level is output, and
Set the read / write signal R / W to low level to set the FiFo memory 3
Instruct 1 to perform a write operation in a first-in first-out format, and thereafter output the received data Drx to the data bus DBUS. This gives F
The iFo memory 31 sequentially stores the received data Drx in the memory cell array 40 while incrementing the write address counter 44.

The processor 33 asserts the bus request signal BREQ ₁ when the empty signal ES is not asserted,
When the bus right is granted in response to this request, the address signal Ai that can set the control signal AA to low level is output, and
Set the read / write signal R / W to high level to set the FiFo memory 3
Instruct 1 to perform the operation based on the advance format. This allows the FiF
o The memory 31 sequentially reads the received data stored in the memo cell array 40 while incrementing the read address counter 43.

Here, when unnecessary data is generated in the middle of the received data stored in the memory cell array 40 due to an error in the system operation or the like, the operation of clearing the unnecessary data is the same as that in the above-described embodiment. For example, FIG. As shown in A), when the read address counter 43 and the write address counter 44 point to certain values Ar and Aw, when the data in the areas ED1 and ED2 in the address space of the memory cell array 40 becomes unnecessary, the processor 33 rewrites the value of the read address counter 43 to Ar 'and rewrites the value of the write address counter 44 to Aw', as shown in FIG. 5 (B). Thus, the read address counter 43
When the value of the write address counter 44 is rewritten, the received data Drx subsequently given from the serial input circuit 34 is sequentially written from the address of the value Aw 'indicated by the write address counter 44, and unnecessary data remaining in the area ED2 is written. Is ignored. Thereafter, the received data stored in the memory cell array 40 is processed by the processor.
When the data 33 is read in advance, the data is sequentially read from the address of the value Ar 'indicated by the read address counter 43, and the data remaining in the area ED1 is ignored.
Therefore, even if it is not necessary to read all unnecessary data in order and update the value of the read address counter 43, only the operation of forcibly rewriting the values of the read address counter 43 and the write address counter 44 by the processor 33 can substantially reduce unnecessary data. Clear processing can be easily performed.

In this clear processing, the read address counter 43
And when rewriting the value of the write address counter 44,
When the processor 33 needs to know the states of the address counters 43 and 44, the processor 33 performs read access to the values of the read address counter 43 and the write address counter 44 and rewrites them based on the read values Ar and Aw. The power values Ar 'and Aw' are calculated.

Next, when it is necessary to check data stored in the middle of the FiFo memory 31 due to system operation, the processor 33 randomly accesses the FiFo memory 31 by the address signal Ai and reads required data. In the read operation at this time, the control signal φri is not asserted, whereby the value of the read address counter 43 is maintained. At the time of this random access, the processor
If the 33 requires the physical address space of the FiFo memory 31 and the address information which is a reference of the required address to be accessed, the processor 33 is used as a read address counter.
It is possible to read-access the value 43 or the write address counter 44 and read the value.

Even when the FiFo memory 31 is configured as a single memory chip or a pellet as in this embodiment, the order of reading and writing data is defined by the values of the built-in address counters 43 and 44, as described in the first embodiment. Even if it is possible, random access becomes possible, and FiFo memory
It becomes possible to easily perform the substantial clearing process of the data at 31, and by these things,
When the processor 33 attempts to perform protocol processing on received data, it is not necessary to transfer all the data received in the FiFo memory 31 to a local memory or the like and then perform the protocol processing, thereby improving the efficiency of the protocol processing. Can be.

Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

In the above embodiment, the functional module for accessing the FiFo memory has been described as a central processing unit, a processor, and a serial input circuit, but the present invention is not limited thereto, and may include a direct memory access controller, a parallel input circuit, and the like. Good. In addition, the control signal for determining the operation mode of the FiFo memory is not limited to the control signals AA and CA described in the above embodiment, and can be appropriately changed, and the generation method thereof can be variously changed. .
Further, the clearing process in the FiFo memory is not limited to the content described with reference to FIG. 5; for example, when there is unnecessary data only in the area ED1 in FIG. 5A, only the value of the read address counter is rewritten. You can do it. Similarly the fifth
If there is unnecessary data only in the area ED2 in FIG. 7A, only the value of the write address counter needs to be rewritten.

In the above description, mainly the case where the invention made by the present inventor is applied to a FiFo memory which is a buffer memory for received data, which is a field of application as the background, but the present invention is not limited thereto, and the present invention is not limited thereto. The present invention can be widely applied to a buffer memory for data, an interface circuit between various input / output circuits and a host side or a system side, and a FiLo memory. The present invention can be applied to at least a condition that incorporates an address counter that defines the order of reading and writing data.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the output address signal of the address counter and the address signal supplied from the outside can be selected, and the update operation of the address counter is suppressed when the external address signal is used as the access address signal. Even if the order is specified by the built-in address counter, it is possible to randomly access any address other than the address indicated by the built-in address counter while maintaining the address indicated by the built-in address counter.

In addition, by making the value of the built-in address counter that defines the order of reading and / or writing of data externally rewritable, when unnecessary data is generated in the middle of stored data, the address counter can be externally written. Forcibly rewriting has an effect that data can be substantially cleared easily.

Since the value of the address counter can be read from the outside, the physical address space of the semiconductor memory device and the address information serving as the reference of the required address to be accessed are required externally when random access or unnecessary data is cleared. In such a case, such a request can be easily answered by reading the value of the address counter.

A random access function and a clear function are added to a semiconductor memory device in which the order of data reading and / or writing is defined by the value of a built-in address counter, so that such a semiconductor memory device can be used not only as a data buffer but also as a protocol. It can also be used as a temporary storage area of data for data processing such as processing, so that the operation of transferring data from the data buffer to the temporary storage area can be omitted, and a dedicated data temporary storage area can be used. This eliminates the necessity, and contributes to simplifying the data processing system and speeding up data processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a FiFo memory according to one embodiment of the present invention, FIG. 2 is a block diagram showing a main part of a processor formed by forming the FiFo memory shown in FIG. 1 on the same semiconductor substrate, The figure shows a single chip Fi which is another embodiment of the present invention.
Block diagram of Fo memory, Fig. 4 is FiFo shown in Fig. 3.
FIGS. 5A and 5B are block diagrams showing an example of a system configuration on a board including a memory, and FIGS. 5A and 5B are diagrams showing an example of a clearing process in a FiFo memory. 1 ... FiFo memory, 2 ... processor, 3 ... central processing unit, 4 ... serial input circuit, 5 ... decoder, 10 ...
... Memory cell array, 11 ... Address decoder, 12 ...
Read / write circuit, 13: Read address counter, 14: Write address counter, 15: Address input buffer, 16: Selector, 17: Controller, 18
…… Comparison circuit, 20… Data input / output buffer, 21…
... Data input buffer, 31 ... FiFo memory, 32 ... Bus arbiter, 33 ... Processor, 34 ... Serial input circuit, 35 ... Decoder, 40 ... Memory cell array, 41 ...
Address decoder, 42 ... Read / write circuit, 43 ...
... Read address counter, 44 ... Write address counter, 45 ... Address input buffer, 46 ... Selector,
47: Controller, 48: Comparison judgment circuit, 50: Data input / output buffer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) G11C 7/00 G11C 11/34 G11C 8/00 G11C 29/00

Claims (4)

(57) [Claims] An address counter for updating an access address in a FiFo format, selection means for selecting an output address signal of an address counter and an address signal supplied from outside, and an address counter based on the address signal selected by the selection means. A memory cell array in which a plurality of addressed memory cells are arranged in a matrix; a read / write circuit for performing a read operation and a write operation on the addressed memory cells; and control means; In response to an external instruction of a FiFo access operation for accessing a memory cell using the output address signal of the counter, the selecting means selects the address signal supplied from the address counter to enable the memory cell array and Allows updating of address counter in FiFo format Responding to an external instruction of a random access operation for accessing a memory cell using an externally supplied address signal, causing the selecting means to select the externally supplied address signal to enable access to the memory cell array. In addition, the updating of the address counter is suppressed, and further, when the FiFo access operation is instructed after the random access operation, the memory cell array can be continuously accessed from the value of the address counter in which the updating is suppressed. Semiconductor memory device. 2. The address counter according to claim 1, wherein a count value of the address counter is made readable via an external data input / output terminal. The control means further controls switching between a read operation on the address counter and a read operation on the memory cell. 2. The semiconductor memory device according to claim 1, wherein 3. The address counter is made writable via an external data input / output terminal, and the control means further controls switching between a write operation on the address counter and a read operation on the memory cell. The semiconductor memory device according to claim 1. 4. The address counter according to claim 1, further comprising: a read address counter for updating an address for a data read operation by a count operation; and a write address counter for updating an address for a data write operation by a count operation. 4. The semiconductor memory device according to claim 3, wherein: