JP2816746B2 - Serial data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention is directed to a serial data transmission method for transmitting serial data consisting of a plurality of bits with a start bit added at the beginning together with a clock signal having a cycle corresponding to a 1-bit data signal width in a predetermined cycle and at the same transmission timing in both directions. It is about the system.

[Prior art]

When transmitting data consisting of a plurality of bits from the transmitting side to the receiving side, if the data is transmitted in a plurality of bits in parallel, the time required for the transmission may be short, but since it is necessary to lay parallel transmission lines, the transmission A method of serially transmitting data is used in a machine tool, an engine room of an automobile, or the like where there is not enough room for laying tracks. FIG. 4 is a block diagram showing the most basic configuration of a conventional serial data transmission system for transmitting data consisting of a plurality of bits serially and bidirectionally at the same transmission timing. 2 transmitting / receiving circuit 2,
A data transmission line 3 for transmitting serial data SD1 consisting of a plurality of bits to which a start bit is added at the beginning to the second transmitting / receiving circuit 2, and transmitting a clock signal CLK1 having a cycle corresponding to a 1-bit data signal width to the second transmitting / receiving circuit 2. And a data transmission line 5 for transmitting serial data SD2 consisting of a plurality of bits to which a start bit is added to the first transmission / reception circuit 1, and a clock signal CLK2 having a period corresponding to the data signal width of 1 bit. And a clock transmission line 6 for transmitting the clock signal to the first transmission / reception circuit 1. As shown in the example of the data format in FIG. 5, the serial data SD1 and SD2 start with a start bit STB (“H” level) having a 1-bit configuration, followed by an 8-bit data portion D.
Is added. Then, the serial data SD1,
Assuming that the required transmission time of SD2 is Ta and the pause time Tb is the transmission of the next serial data SD1 and SD2, the serial data
As shown in FIG. 6, SD1 and SD2 are sequentially transmitted bidirectionally at the same transmission timing in a “Ta + Tb” time cycle. Assuming that one cycle of the clock signal CLK is t, in the transmission form of FIG. 6 to which the data format example of FIG. 5 is applied, Ta = 9t,
Tb = 5t. On the other hand, the clock signal CLK1 (or CLK2) is associated with the serial data SD1 (or SD2) as shown in the time chart of FIG.
The change (1 → 0, 0 → 1) of each bit in D2) uses the clock signal CLK1 (or CLK2) as a trigger signal and is synchronized with the clock signal CLK. When the serial data SD2 has been transmitted in the timing relationship as shown in FIG. 7, the first transmission / reception circuit 1 first synchronizes with the rising edge of the clock signal CLK2,
After confirming the STB, the subsequent data portion D is taken into a shift register or the like and converted into 8-bit parallel data, and predetermined data processing or control of a controlled device is performed by the converted output data. Here, assuming that the transmission timings of the serial data SD1 and SD2 are the same, the first transmitting / receiving circuit 1
At the same time as the start of data transmission, the start bit STB is received from the second transmission / reception circuit 2 and the operation shifts to the reception state of the data section D thereafter. This is the same in the second transmitting / receiving circuit 2. The transmission and reception circuits 1 and 2 are monitored by a monitoring device 7 that monitors the operation state of the entire system.

[Problems to be solved by the invention]

However, when the transmission timing of the next serial data SD1, SD2 is delayed due to malfunction of the transmission / reception circuits 1, 2, or the frequency of the clock signals CLK1, CLK2 changes due to noise or the like being superimposed on the clock transmission lines 5, 6. Then, the transmission timing and the reception timing of the serial data, which are considered to be the same timing, may be shifted, and the reception timing may be delayed. If such a delay in the reception timing exceeds the allowable range, the start bit ST
Since B cannot be confirmed, the subsequent data portion D is ignored, and processing and control based on the contents of the data portion D cannot be performed, or a control error occurs, and the reliability of the system is reduced. . The present invention has been made in view of the above circumstances, and provides a serial data transmission system capable of detecting a transmission abnormality due to a delay in serial data reception timing and preventing a decrease in system reliability. The purpose is to do.

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides a method for transmitting serial data consisting of a plurality of bits with a start bit added at a predetermined period and a bidirectional direction together with a clock signal having a period corresponding to a 1-bit data signal width. In a serial data transmission system for transmitting at a timing, a start bit reception timing detecting circuit for detecting a reception timing of a start bit of serial data received from a transmission partner; Determines whether the reception timing of the start bit detected by the timing detection circuit is within the allowable range, and outputs a transmission error signal to a monitoring device that monitors the operating state of the system if it exceeds the allowable range. And a transmission abnormality detection device comprising a determination circuit for performing the determination.

[Action]

According to the above configuration, when the reception timing of the start bit from the other party exceeds the allowable range with respect to the transmission timing of the serial data to the other party, the transmission abnormality signal is output from the determination circuit. , The reliability of the system can be prevented from deteriorating.

【Example】

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a serial data transmission system according to the present invention. A transmission abnormality detection circuit 8 is newly provided on the second transmission / reception circuit 2 side in comparison with the conventional configuration. As shown in FIG. 2, an example of the detailed structure of the transmission abnormality detecting circuit 8 is a serial data transmitted from the first transmission / reception circuit 1 which is the transmission partner of the second transmission / reception circuit 2.
A start bit reception timing detection circuit (hereinafter abbreviated as detection circuit) 80 for receiving SD1 and detecting the start bit STB of the start bit STB, and detecting the transmission timing of the serial data SD2 to the first transmission / reception circuit 1 Circuit 8
It is determined whether or not the reception timing of the start bit STB detected by 0 is within an allowable range. If the reception timing is outside the allowable range, the transmission abnormality detection signal ALM is monitored by the monitoring device 7 that monitors the operating state of the system. And a determination circuit 81 that outputs the result to the The detection circuit 80 receives the serial data SD1, the clock signals CLK1 and CLK2, and the signals RST and RFT. Note that the signal RST is a signal indicating that the reception circuit unit of the second transmission / reception circuit 2 has received the start bit STB, and the signal SFT is transmitted to a parallel / serial conversion shift register provided in the transmission circuit unit of the second transmission / reception circuit 2. On the other hand, this signal permits the start of conversion of parallel 8-bit data into serial data. The detection circuit 80 includes an inverter 800 for inverting the clock signal CLK1, a flip-flop 801 set by receiving the signal RST, and a 3-bit counter 80 for counting the clock signal CLK1 after receiving the start bit STB.
2. An AND gate 803 that allows the clock signal CLK1 to pass only when the flip-flop 801 is set, an inverter 804 that outputs an "L" level signal when the count value of the counter 802 becomes "4", and the signal RST. The shift register 806 stores the time when the next start bit STB is received after the shift register 806 is generated.
And an input gate 807 for inputting a shift lock. The determination circuit 81 includes a flip-flop 810, which is set when the signal SFT rises,
Flip-flops 811, 818, 812, 813, and flip-flop 8, which sequentially shift the set output Q of the
The logical product of the set output Q of the 12 and the set output Q of the flip-flop 810 is obtained, and the logical product signal is output as an abnormality determination timing signal TMG (hereinafter, referred to as a timing signal), and the output of the shift register 806. A NOR gate 816 that outputs a "L" level signal when the reception timing of the start bit STB is within the allowable range, and an "H" level when it exceeds the allowable range. Captured by 815 output TMG, transmission error detection signal ALM from set output Q
And a flip-flop 817 for outputting the same. As shown in FIG. 5, the serial data SD1 and SD2 are sequentially transmitted bidirectionally at the same transmission timing in a “Ta + Tb” time cycle, and Ta = 9t and Tb = 5t. Next, the operation of the above circuit will be described with reference to the time chart of FIG. Note that flip-flops 801, 810 to 81
3, 817, 818, the counter 802, and the shift register 806 are initialized when the power is turned on. First, when the serial data SD1 and the clock signal CLK1 are transmitted from the first transmitting / receiving circuit 1 in the form shown in FIGS. 5 to 7, the transmission abnormality detecting circuit 8 and the second transmitting / receiving circuit 2 transmit the serial data SD1 and the clock. The signal CLK1 is received. At the same time, the serial data SD2 is transmitted from the second transmission / reception circuit 2 in the same form, and the first transmission / reception circuit 1 receives the serial data SD2 and the clock signal CLK2. At this time, if the data transmission line 3 and the clock transmission line 4 are normal, the second transmission / reception circuit 2 and the transmission abnormality detection circuit 8 transmit from the first transmission / reception circuit 1 at the same timing as the data transmission timing of the second transmission / reception circuit 2. Serial data SD
Receive one. For example, if the 8-bit data portion D of the serial data SD1 is "00000000", the clock signal CLK1 as shown in FIG. 3A is received, and the clock signal CLK1 is started as shown in FIG. 3C. Serial data SD1 in which only bit STB is at “H” level is received. The received serial data SD1 is input to the data terminal of the shift register 806, but is not taken into the shift register 806 because the AND gate 807 is closed. On the other hand, the second transmitting / receiving circuit 2 outputs a clock signal CLK2 as shown in FIG. 3 (b). However, the reception circuit unit of the second transmission / reception circuit 2 confirms the start bit STB at the beginning of the received serial data SD1, and as shown in FIG. Signal R
Output ST. Then, the rising edge of the signal RST sets the flip-flop 801 and the inverted set output thereof becomes "L" level as shown in FIG. 3 (f). When the flip-flop 801 is set, the AND gate 803 opens, and the reset state of the counter 802 is released. At the same time, the clock signal CLK1
Is input via the AND gate 803. When the count value becomes "4", 2 ² output terminal becomes the "H" level, thereby, so that the output signal of the inverter 804 shown in FIG. 3 (g), to the "L" level.
Then, flip-flop 801 is reset by the “L” level output signal of inverter 804. And
When the flip-flop 801 is reset, the counter 802 is reset again. On the other hand, the reset state of the shift register 806 is released when the flip-flop 801 is reset.
That is, since the reception timing of the next start bit STB approaches, the reset state is released. When the reset state is released, the shift clock signal from the AND gate 807 takes in the data from the data input terminal and shifts. In the example of FIG. 3, the next start bit STB is received as the data. Since there is no data, the stored contents are the same as those in the reset state. However, when the next start bit STB is normally received at the timing shown in FIG. 3C, the start bit STB is taken into the shift register 806 at the falling edge of the clock signal CLK1. Then, each time the new clock signal CLK1 falls, it is shifted to the upper bit side. On the other hand, as shown in FIG. 3 (e), the signal SFT rises at substantially the intermediate timing of the eighth bit of the data portion D of the received data SD1, and this signal SFT rises.
Rises, flip-flop 801 is set. When the flip-flop 810 is set, the flip-flops 811, 818, 812, 813 are sequentially set with a delay of one cycle of the clock signal CLK2. Then, as the flip-flop 812 is set, the AND gate 807 is closed, and the shift operation of the shift register 806 is prohibited. Therefore, if the next start bit STB is normally received, the shift number of the shift register 806 is only one, two times if the timing is one clock earlier, and zero if the timing is one clock later. , 2 ¹ = “H” when the number of shifts is 1 and 2 ² when the number of shifts is ²
= "H", when the shift count is 0 times will be 2 ⁰ = "H". That is, if the error of the start bit STB with respect to the normal reception timing is within ± 1 clock, the shift register
One of the output terminals of the 806 becomes “H” level. By such an operation, the shift register 806 stores when the start bit STB was received, and more specifically, whether the start bit STB was received with an error within ± 1 clock from the normal reception timing. Accordingly, the output of the NOR gate 816 of the decision circuit 81 is always at the “L” level if the start bit STB is received within an error of ± 1 clock with respect to the normal reception timing, and otherwise is “H”. Level. Therefore, the flip-flop 817 of the determination circuit 81 is set by the timing signal TMG output from the AND gate 815 when the output of the NOR gate 816 is at “H” level. That is, as shown in FIG. 3 (h), the flip-flop 817 is set only when the start bit STB is not received within an error of ± 1 clock with respect to the normal reception timing. This set output is output as a transmission abnormality detection signal ALM as shown in FIG. 3 (k). Then, it is input to the monitoring device 7 and notified that a transmission error has occurred. The monitoring device 7 performs an error recovery process or the like, and performs a process of returning a transmission error state to a normal state. On the other hand, if the error is within ± 1 clock from the normal reception timing, the flip-flop 817 is not set, so that the transmission abnormality detection signal ALM becomes "L" level as shown in FIG. 3 (j). . In a simple transmission system that does not include the monitoring device 7, a display device or the like may notify a manager of the occurrence of a transmission error.

【The invention's effect】

As described above, according to the present invention, in a serial data transmission system for transmitting serial data with a start bit added at the beginning thereof at a predetermined cycle in the same transmission timing, the reception timing of the start bit of the serial data received from the transmission partner is Because it is configured to detect whether the reception timing is within an allowable range with respect to the transmission timing of the serial data to the transmission partner, and to output a transmission abnormality signal when the reception timing exceeds the allowable range, By processing such as causing the monitoring device to take recovery measures, it is possible to prevent the reliability of the system from deteriorating due to a delay in reception timing of serial data due to superposition of noise or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a serial data transmission system according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a transmission abnormality detecting circuit which is a main part of the present invention, and FIG. 4 is a time chart for explaining the operation of the detection circuit, FIG. 4 is a block diagram showing a configuration of a conventional serial data transmission system, FIG. 5 is an explanatory diagram showing an example of a serial data transmission format, and FIG. FIG. 7 is an explanatory diagram showing a data transmission format, and FIG. 7 is a time chart showing a relationship between a data portion and a clock signal. DESCRIPTION OF SYMBOLS 1 ... 1st transmission / reception circuit 2 ... 2nd transmission / reception circuit 3, 5 ... Data transmission line 4, 6 ... Clock transmission line 7 ... Monitoring device 8 ... Transmission abnormality detection circuit 80 ... Start bit reception timing detection Circuit 81: Judgment circuit

Claims (1)

(57) [Claims] 1. Serial data transmitted at predetermined intervals and bidirectionally at the same transmission timing together with a clock signal having a cycle corresponding to a 1-bit data signal width, comprising serial data consisting of multiple bits with a start bit added at the beginning. In the transmission system, the start bit reception timing detection circuit that detects the reception timing of the start bit of the serial data received from the transmission partner, and the start bit reception timing detection circuit detects the transmission timing of the serial data to the transmission partner A determination circuit that determines whether the reception timing of the start bit is within an allowable range, and outputs a transmission abnormality signal to a monitoring device or the like that monitors an operation state of the system when the reception timing is outside the allowable range. Serial data transmission characterized by having a transmission error detection device system.