JP2815955B2 - Digital data reproduction circuit in optical storage device. - Google Patents

Description

The present invention relates to a digital data reproducing circuit in an optical storage device for obtaining digital data corresponding to information recorded on a recording medium in an optical disk device or the like.

[Conventional technology]

2. Description of the Related Art Optical disk devices that record and reproduce data by condensing a light beam on a minute spot and irradiating a rotating or sliding recording medium are now widely known.

For example, in a magneto-optical disk device, a perpendicular magnetization film whose magnetization is oriented perpendicular to the disk surface is used as a recording medium. At room temperature, since the coercive force of this recording medium is large, it is difficult to change the direction of magnetization. However, when this recording medium is irradiated with a light beam, the temperature of that portion rises, and the coercive force decreases as the temperature approaches the Curie temperature, so that the direction of magnetization can be changed relatively easily by applying an external magnetic field.

Therefore, when data is recorded, a light beam is irradiated in a state where a magnetic field is applied from the outside, the directions of magnetization are aligned in advance (erasing operation), and then the direction of the external magnetic field is reversed and recorded. When the light beam is turned on and off in response to the data, the direction of magnetization is inverted only in the portion irradiated with the light beam, and data can be recorded (light modulation recording).

Alternatively, the light beam is continuously emitted without blinking,
If the direction of the external magnetic field is reversed in accordance with the data, recording can be performed without performing an erasing operation (magnetic field modulation recording).

On the other hand, when reproducing data, the recording medium is irradiated with a light beam weaker than during recording so as not to exceed the Curie temperature. The change in the plane of polarization of the reflected light is converted into a change in light intensity by an analyzer, which is further converted into an electric signal, and the signal is compared with a certain voltage level to digitize the data. Can be played.

[Problems to be solved by the invention]

By the way, a portion where the direction of magnetization is inverted corresponding to the recording data on the recording medium is hereinafter referred to as a mark. When the size of the mark is smaller than the spot diameter of the light beam, the size of the reproduction output is increased. Will vary depending on the size of the mark. Therefore, it is difficult to obtain digital data from a mark row in which marks of various sizes are mixed by a conventional method.

For example, in magnetic field modulation recording, if the reversal cycle of the external magnetic field is shorter than the relative speed of the light beam and the recording medium, the external magnetic field is reversed before the light beam moves a distance corresponding to the spot diameter. 10 As shown in FIG.
A mark 103 smaller than the diameter of the light beam spot 101, a mark 102 sufficiently larger than the mark 103, and a mark gap 104 between two adjacent size marks 109 and 110 and smaller than the diameter of the light beam spot 101. In some cases, a mark string composed of, for example, is recorded.

When this mark train is reproduced with a light beam, the reproduction level 106 of the small mark 103 is small, the reproduction level 105 of the large mark 102 is large, and the reproduction level 107 of the small mark gap 104 is sufficient, as shown in FIG. I can't go down. For this reason, the maximum value and the minimum value of the amplitude of the reproduction signal fluctuate.

If such a reproduction signal is to be digitized at the slice level 108, the reproduction level 106 of the small mark 103
Since the reproduction level 107 at the small mark interval 104 cannot sufficiently exceed the slice level 108, FIG.
The signal becomes as shown in
There is a problem in that digital data corresponding to 09/110 cannot be obtained.

[Means for solving the problem]

The digital data reproducing circuit in the optical storage device according to the present invention is a digital data reproducing circuit in an optical storage device that reproduces digital data by sampling a reproduction signal whose amplitude peak value or bottom value fluctuates based on a clock. Peak / bottom detection means for detecting a peak value and a bottom value from among the sampled values; storage means for storing the detected peak value or the bottom value; and a current sampling value and a peak value or a bottom value adjacent thereto. And a determining means for determining whether the result of the comparison is larger or smaller than a predetermined value, and setting the predetermined value in the determining means to be smaller than the reproduction signal amplitude from the minimum mark. The reproducing signal is converted into digital data based on the output of the judging means.

(Operation)

According to the above configuration, since the determination is made by setting the predetermined value smaller than the reproduction signal amplitude from the minimum mark, accurate digital data can be obtained even if the peak value or bottom value of the reproduction signal varies. Obtainable.

〔Example〕

As one embodiment of the present invention, a binarizing circuit provided in a reproducing circuit of a magneto-optical disk device will be described below with reference to FIGS. 1 to 9.

On a recording medium composed of a perpendicular magnetization film, portions in which the direction of magnetization is inverted corresponding to the recording data (hereinafter, this portion is referred to as a mark) are arranged side by side as shown in FIG. 2A, for example. I have. That is, a mark 23 smaller than the diameter of the light beam spot 21, a mark 22 sufficiently larger than the mark 23,
A mark row including a mark gap 24 smaller than the diameter of the light beam spot 21 in a portion between two adjacent large marks 28 and 29 is mixed on the recording medium.

At the time of reproduction, the recording medium is irradiated with a light beam weaker than at the time of recording so as not to exceed the Curie temperature. Then, a change due to the magneto-optical effect of the polarization plane in the reflected light is converted into a change in light intensity by the analyzer, which is further converted into an electric signal. Thereafter, the electric signal is amplified to a predetermined amplitude to obtain a reproduced signal having a waveform as shown in FIG. 2 (b).

Comparing the reproduced signal with the mark train shown in FIG. 3A, the reproduction level 26 of the small mark 23 is considerably lower than the reproduction level 25 of the large mark 22, and the small mark gap is small.
It can be seen that the reproduction level 27 of 24 is not sufficiently reduced. Then, the reproduction signal in which the maximum value and the minimum value of the amplitude fluctuate is input to the binarization circuit.

As shown in FIG. 1, the binarization circuit of the present invention comprises an A / D converter 11, three latches 12 to 14, a peak / bottom detection circuit 15 as detection means, and a latch with a latch enable as storage means. 16. It comprises a difference comparison circuit 17 as a comparison output means and a D flip-flop 18.

In the above configuration, the above-mentioned reproduction signal (FIG. 2 (b)) is first input to the A / D converter 11 from the (in-1) terminal. In this embodiment, the data is converted into 4-bit digital data (0 to F in hexadecimal), and the output is input to the latch 12. The output of latch 12 is
, And the output of the latch 13 is input to the latch 14.
Since these latches 12 to 14 store the data at the rising edge of the clock input from the clk terminal, the data output from these latches 12 to 14 are shown in FIGS.
As shown by the hexadecimal numbers in FIG. 2F, the clock is delayed by one clock.

In addition, as a clock, as shown in FIG.
Although a binary signal having a single frequency that is a fraction of the shortest change period of the reproduction signal and sufficiently synchronized with the reproduction signal is used here, it is sufficiently shorter than the shortest change period of the reproduction signal. The operation is exactly the same even when a single-frequency binary signal having a period is used.

The data delayed by one clock by the latches 12 to 14 is
Three inputs PC of peak / bottom detection circuit 15 _3-0PB
3-0.PA PAs are respectively input to _3-0 . Here, the peak / bottom detection circuit 15 is defined as: {data input to input PA ₃ to ₀ ≦ data input to input PB ₃ to ₀ ≧ input PC
Data input to ₃ to ₀ or input PA _{3 to 0}
This circuit is such that the output (PO) becomes active (high level) only when the data input to the input ≧ the data input to the input PB _3-0 ≦ the data input to the input PC _3-0 .
Therefore, the output of the peak / bottom detection circuit 15 is only output during the period when the latch 13 is outputting the data of the peak (maximum part) or the bottom (minimum part) of the reproduction signal, as shown in FIG. 2 (g). , High level.

The output of latch 13 is latch 16 with latch enable.
The output of the peak / bottom detection circuit 15 is input to the LE (latch enable) input of the latch 16 with latch enable. Since the latch 16 with latch enable stores data at the rising edge of the clock only during the period when the LE input is at the high level, the output of the latch 13 when the output of the peak / bottom detection circuit 15 is active is stored. As shown in FIG. 2 (h), until the next peak or bottom is detected by the peak / bottom detection circuit 15,
This means that the previous peak or bottom data is retained.

The output of the latch 13 is the input DB of the difference comparison circuit 17.
₃ to _0, and the output of the latch 16 with latch enable is input to the inputs DA ₃ to DA of the difference comparison circuit 17. Here, the difference comparison circuit 17 compares the data input to the inputs DA ₃ to ₀ with the data input to the input DBs ₃ to ₀ , and the absolute value of the difference is equal to or greater than a set value, and ｛Input DA
_In the case of data input to ₃ to ₀ <data input to input DB ₃ to ₀ }, the output becomes active (high level) and {data input to input DA ₃ to ₀ > input DB _{3 to 0}
In this case, the output becomes inactive (low level) when the data｝ is input to the input AUX, and otherwise outputs the same logic as the logic of the signal input to the input AUX.

Note that, in the present embodiment, the above set value is a small mark 23
The reproduction level 26 (FIG. 2 (b)) of FIG. 2 (a) is set to 4, which is about half of that of FIG.

The output of the difference comparison circuit 17 is input to the D flip-flop 18 and latched at the rise of the clock, and the output is input to the input AUX of the difference comparison circuit 17. That is, the output value of the difference comparison circuit 17 one clock before is input to the input AUX.

Accordingly, the output of the difference comparison circuit 17 is composed of the reproduced data for each clock (FIG. 2 (e)) output from the latch 13 and the previous peak or the previous peak in the reproduced data output from the latch 16 with latch enable. Compared with the bottom data (FIG. 2 (h)), the absolute value of the difference (FIG. 2 (i)) is 4 or more of the set value, and the reproduced data for each clock has the previous peak. Alternatively, if the data is larger than the bottom data, it becomes active (high level). If the absolute value of the difference is 4 or more of the set value and the reproduced data for each clock is smaller than the previous peak or bottom data, It becomes inactive (low level), and retains the previous state except in the above two cases.

The output signal of the difference comparison circuit 17 obtained as described above is shown in FIG. 2 (j), and the output signal of the D flip-flop 18 is shown in FIG. 2 (k).

As is apparent from the figure, the output of the difference comparison circuit 17 or the output of the D flip-flop 18 is a binary signal that exactly corresponds to the mark sequence (FIG. 2A) recorded on the recording medium. It has become.

Next, specific examples of the peak / bottom detection circuit 15 and the difference comparison circuit 17 used in the above-described binarization circuit will be described below.
Note that this is an example, and the specific mode is not limited as long as the functions are the same.

First, as shown in FIG. 3, the peak / bottom detection circuit 15 includes four comparison circuits 31 to 34 and two AND gates 35.3.
6, and an OR gate 37.

Comparator circuit 31 compares the two 4-bit data inputted to the input _{A 3 to 0} and the input _{B 3 to 0,} {input _{A 3 to 0}
≧ Data input _to inputs _3-0０
Is a circuit in which the output A ≧ B becomes active (high level). Specifically, for example, as shown in FIG.
Four ExOR gates 71a-71d, five AND gates 75a-75
e, can be realized by combining the OR gate 73 and the eight inverters 72a to 72h.

The remaining three comparison circuits 32 to 34 (FIG. 3) are the same as the comparison circuit 31.

Another specific example of the peak / bottom detection circuit 15 is shown in FIG. It uses ROM41 and has three inputs P at its address.
Assign the _{A 3~0 · PB 3~0 · PC 3~0} , is obtained by programming the ROM41 to output the same logic as the circuit of Figure 3 from the data output.

Next, as shown in FIG. 5, the difference comparison circuit 17 includes three comparison circuits 51a to 51c, two subtraction circuits 54a and 54b, two data selectors 57a and 57b, an ExOR gate 59, and a set value. From a constant setting circuit 52 that outputs

The comparison circuits 51a to 51c are the same as the above-described comparison circuit 31 (FIG. 7).

Subtraction circuit 54a outputs the result of subtracting the data input to the input _{B 3 to 0} from the data inputted to the input _{A 3 to 0} output from _(A-B) 3~0 as 4-bit data 8, specifically, for example, as shown in FIG. 8, seven ExOR gates 81a to 81g and five AND gates 88a to 88a.
88e, two OR gates 82a and 82b, five inverters 83a ~
It can be realized by combining 83e. The subtraction circuit 54b is the same as the subtraction circuit 54a.

The data selector 57a (FIG. 5) outputs the same logic as the input value of the input A to the output Y when a low level is input to the input SEL, and outputs the input B to the output Y when a high level is input to the input SEL. Is a circuit that outputs the same logic as the input value of the two ANs. Specifically, for example, as shown in FIG.
This can be realized by combining the D gates 91 and 92, the OR gate 93, and the inverter 94. Note that the data selector 57
b is the same as the data selector 57a.

Another specific example of the difference comparison circuit 17 is shown in FIG. It uses ROM61 and has two inputs DA at its address.
_{3 to 0.DB 3} to ₀ are assigned, and the ROM 61 is programmed to output the same logic as the circuit of FIG. 5 from the data output.

In the above embodiment, the binarization circuit provided in the reproduction circuit of the magneto-optical disk device has been described. However, the present invention can be applied to an optical disk device.

〔The invention's effect〕

According to the digital data reproducing circuit in the optical storage device of the present invention, accurate digital data can be obtained even if the peak value or the bottom value of the reproduced signal fluctuates.

[Brief description of the drawings]

1 to 9 show an embodiment of the present invention. FIG. 1 is a block diagram showing a binarizing circuit according to the present invention. FIG. 2 is an explanatory diagram showing the operation of the binarization circuit. FIG. 3 is a block diagram showing a specific example of a peak / bottom detection circuit. FIG. 4 is a block diagram showing another specific example of the peak / bottom detection circuit. FIG. 5 is a block diagram showing a specific example of the difference comparison circuit. FIG. 6 is a block diagram showing another specific example of the difference comparison circuit. FIG. 7 is a circuit diagram of the comparison circuit. FIG. 8 is a circuit diagram of a subtraction circuit. FIG. 9 is a circuit diagram of the data selector. FIG. 10 shows a conventional example and is an explanatory diagram of binarization by a slice level. 11 is an A / D converter, 12 to 14 are latches, 15 is a peak / bottom detection circuit (detection means), 16 is a latch with latch enable (storage means), and 17 and 18 are a difference comparison circuit and a D flip-flop ( Comparison output means).

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshihisa Exit 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 20/10 321

Claims (3)

(57) [Claims] 1. A digital data reproducing circuit in an optical storage device for reproducing digital data by sampling a reproduced signal whose amplitude peak value or bottom value fluctuates based on a clock, comprising: Peak / bottom detection means for detecting a bottom value; storage means for storing the detected peak value or bottom value; and a comparison result between the current sampling value and a peak value or bottom value adjacent thereto. Determination means for determining whether is larger or smaller than a predetermined value. The predetermined value in the determination means is set to be smaller than the amplitude of the reproduction signal from the minimum mark, and the reproduction is performed based on the output of the determination means. A digital data reproducing circuit in an optical storage device, which converts a signal into digital data. 2. The method according to claim 1, wherein the determination means determines that the digital data is a change point when the comparison result is larger than a predetermined value, and is a holding point of the digital data when the comparison result is smaller than a predetermined value. Item 2. A digital data reproducing circuit in the optical storage device according to item 1. 3. The determining means determines that the digital data is a change point when the comparison result is larger than a predetermined value, and continues the comparison operation until it is determined that the digital data is the next change point. 2. A digital data reproducing circuit in an optical storage device according to claim 1, wherein: