JPH0559507B2 - - Google Patents

Description

Detailed Description of the Invention <Technical Field> The present invention relates to an optical memory device that records, reproduces, or erases information by irradiating an optical information recording medium with a light beam such as a laser beam. The present invention relates to a signal detection circuit that detects a signal.

<Prior Art> A signal detection circuit in a magneto-optical disk memory device will be described as an example of a signal detection circuit in a conventional optical memory device. A magneto-optical disk memory device is an optical memory device that uses a magnetic film having an axis of easy magnetization in a direction perpendicular to the film surface as a recording medium, and performs recording, reproduction, or erasing by irradiating the film with a laser beam.

The recording/reproducing method of this magneto-optical disk memory device will first be explained.

During recording, when a laser beam focused to a diameter of about 1 μm is intensity-modulated according to the recording signal and irradiated onto the magnetic film surface of the magneto-optical disk, the temperature of the magnetic film locally rises. The coercive force decreases in the area where the temperature has risen, so if an auxiliary magnetic field is applied from the outside at the same time, the direction of magnetization is reversed and information is recorded.

During reproduction, the surface of the recorded magnetic film is irradiated with linearly polarized laser light of a weaker intensity than during recording. Then, the reflected light causes a tilt in the plane of polarization due to the magneto-optical effect (Kerr effect) of the magnetic film. This slope is detected by an analyzer and converted into light intensity, which is then detected by a photodetector and information is reproduced.

FIG. 5 shows a block diagram of an information reproducing apparatus for a magneto-optical disk device, FIG. 6 shows a signal detection circuit, and FIG. 7 shows signal waveforms in FIG. 6. Furthermore, Figures 5 and 6
The same reference numerals shown in the figures and FIG. 7 indicate the same things.

In FIG. 5, the analog signal reproduced by the optical head 21 is transferred to an amplifier 22 and a waveform processing circuit 23.
becomes the reproduced signal 101 through the signal detection circuit 2.
4, a digital information signal 205 is detected. Digital information signal 205 is guided to PLL and synchronization detection circuit 25. Based on the introduced digital information signal 205, the PLL generates a phase-synchronized clock signal, and the synchronization detection circuit detects synchronization in sectors such as sector marks.

Conventionally, the signal detection circuit 24 shown in FIG. 5 has had the configuration shown in FIG. 6. That is, the reproduced signal 101
is led to one side of the comparator 1 as an input, and also to the comparison voltage generation circuit 31 (the part surrounded by the broken line). In this example, a low-pass filter 32 is used as the comparison voltage generation circuit 31.
The comparison voltage 204 obtained as an output from the comparison voltage generation circuit 31 is led to the other input of the comparator 1, and a digital information signal 205 is obtained as the output of the comparator 1.

FIG. 7 shows the waveform in FIG. 6. As shown in FIG. 7, the reproduced signal 101 corresponds to the recording marks only in the recorded area. The DC component of this reproduced signal 101 is shown by a broken line. The output of the low-pass filter 32 in the comparison voltage generation circuit 31, that is, the comparison voltage 204 is the output of the reproduction signal 101.
The waveform shows transient response characteristics for the DC component. Therefore, the digital information signal 205 obtained by comparing the reproduced signal 101 and the comparison voltage 204 becomes a random noise signal in the unrecorded area, as shown in FIG. 7, and the comparison voltage 204 immediately after the start of the recorded area. The transient characteristics of the signal result in a signal with a duty shift.

The digital information signal 205 shown above is
When input to the PLL and synchronization detection circuit shown in the figure, random noise signals generated in the unrecorded area and signals with a duty shift immediately after the start of the recording area are used for PLL pull-in operation and synchronization detection of sector marks, etc. However, reliability deteriorated. In other words, the PLL tends to respond to random noise signals, and the synchronization detection circuit may erroneously detect synchronization. A signal with a duty shift may degrade the PLL pull-in response and may not be detected by the synchronization detection circuit. Therefore, a signal detection circuit that detects reliable digital information signals for PLL pull-in operation and synchronization detection has been desired.

In this example, a magneto-optical disk memory device is taken as an example of the optical memory device, but the above-mentioned problems are the same in write-once type optical disk memory devices and the like.

<Object of the Invention> In view of the problems of the prior art described above, the object of the present invention is to provide a signal detection circuit that detects a reliable digital information signal for PLL pull-in operation and synchronization detection in sector marks, etc. It's about doing.

<Example> An example of a signal detection circuit for an optical memory device according to the present invention will be described below, taking a signal detection circuit for a magneto-optical disk memory device as an example.

FIG. 1 is a diagram showing a first embodiment of a signal detection circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms in FIG. 1.

In FIG. 1, a reproduced signal 101 is introduced to one input of a comparator 1 and to an adder 2. In FIG. On the other hand voltage v ₀
A signal 102 is sent to the adder 2 by switching between the voltage divided by the variable resistor 4 and the ground voltage in the switching circuit 5 based on the timing signal 106 . In this adder 2, a signal 102 is added to the reproduced signal 101. Output signal 10 of adder 2
3 is led to a comparison voltage generation circuit 31. A low-pass filter 3 is used as the comparison voltage generation circuit 31. The comparison voltage 104 obtained here is led to the other input of the comparator 1, and a digital information signal 105 is detected.

FIG. 2 shows the signal waveform in FIG. 1. A signal 102 is added to the reproduced signal 101 based on a timing signal 106. That is, a certain level is added to the reproduced signal 101 only in the unrecorded area. Focusing on the DC component, as shown in FIG. 2, when the signal 102 is added to the DC component of the reproduced signal 101, the DC component of the signal 103 (indicated by a broken line) is obtained. Therefore, the digital information signal 105 detected by comparing the comparison voltage 104 outputted through the low-pass filter 3 and the reproduced signal 101 can avoid generation of random noise signals in the unrecorded area, and can be used in the recorded area. The duty can be improved immediately after the start of the process. Note that in this example, the signal 102 is added to the reproduced signal 101, but when the signal 102 is added to the comparison voltage 104, only the generation of random noise signals in the unrecorded portion can be avoided.

Next, a second embodiment will be described using FIG. 3.

The reproduced signal 101 is input to one side of the comparator 1 and the second
Comparison voltage generation circuit 31 (portion surrounded by broken line)
be guided by First, this second comparison voltage generation circuit 31 will be explained. The reproduced signal 101 is guided to a positive direction peak hold circuit 11 and a negative direction peak hold circuit 12, and the respective output signals 111 and 112 are sent to an adder 13 and a multiplier 14 (1/
2x). That is, this circuit is a second comparison voltage generation circuit that detects the envelope of the reproduced signal 101 and outputs the center level of the envelope as the second comparison voltage. Now, when the voltage obtained by dividing v ₀ by the variable resistor 14 and the ground voltage are switched in the switching circuit 15 based on the timing signal 106, a signal 114 is obtained. A signal 115 obtained by adding this signal 114 and signal 113 in the adder 16
is outputted via the low-pass filter 17, and a first comparison voltage 116 is obtained. The comparator 1 compares the reproduced signal 101 with the first comparison voltage 116 and detects the digital information signal 105.

The signal waveform in FIG. 3 will be explained using FIG. 4. Second comparison voltage 1 for reproduced signal 101
The DC components of 13 are shown in FIG. On the contrary,
A signal 114 is added to the second comparison voltage 113 based on the timing signal 106 . Therefore, for the DC component (waveform shown by the broken line) of the output signal 115 of the adder 16 shown in FIG.
16 is obtained. When the reproduced signal 101 and the first comparison voltage 116 are compared, a digital information signal 105 is obtained.
is obtained. Similar to the example shown in FIG. 2, this digital information signal 105 can avoid generation of random noise in the unrecorded area, and can improve the duty immediately after the start of the recorded area. In this example, the signal 114 is set to the second comparison voltage 1.
13, but the same effect can be obtained by adding it to the reproduced signal 101 instead of the second comparison voltage 113, inputting it to the second comparison voltage generation circuit 31, and comparing the second comparison voltage and the reproduction signal. is obtained. Further, even if the signal 114 is added to the output signal of the low-pass filter 17 instead of the second comparison voltage 113, only the generation of random noise in the unrecorded area can be avoided.

As shown above, a voltage of a certain level is added to the reproduced signal or the output of the second comparison voltage generation circuit or the comparison voltage input to the comparator in the unrecorded part,
If the digital information signal is detected using the comparison voltage thus obtained, generation of random noise signals in the unrecorded area can be avoided, and the duty immediately after the start of the recording area can be improved. Therefore, it is possible to improve the reliability of the PLL pull-in operation based on this digital information signal and the synchronization detection in the synchronization detection circuit.

In the above two embodiments, a magneto-optical disk memory device was taken as an example of the optical memory device, and an example of the signal generation circuit thereof was shown. It is also applicable to

<Effects of the Invention> According to the present invention, a voltage of a certain level is added to a predetermined position or comparison voltage of a reproduced signal or comparison voltage generation circuit in an unrecorded area, and the comparison voltage obtained thereby is used. If the digital information signal is detected using the same method, the generation of random noise signals in the unrecorded portion can be avoided, and the duty immediately after the start of the recording portion can be improved. Therefore, the reliability of the PLL pull-in operation and the synchronization detection of the synchronization detection circuit based on this digital information signal can be improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a signal detection circuit of a magneto-optical disk memory device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram in FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a signal waveform diagram in FIG. 3, FIG. 5 is a block diagram of an information reproducing device, and FIG. 6 is a conventional example. FIG. 7 is a signal waveform diagram in FIG. 6. In the figure, 1... comparator, 2, 13, 16... adder, 3, 17, 32... low pass filter, 4,
14... Variable resistor, 5, 15... Switching circuit, 11... Positive direction peak hold circuit, 12
... Negative direction peak hold circuit, 14 ... Multiplier, 21 ... Optical head, 22 ... Amplifier, 23
... Waveform processing circuit, 24 ... Signal detection circuit, 25
...PLL and synchronization detection circuit, 31...comparison voltage generation circuit.

Claims (1)

[Scope of Claims] 1. In a signal detection circuit of an optical memory device that records, reproduces or erases information by irradiating an optical information recording medium with a light beam such as a laser beam, an adder that applies a voltage that switches from a constant level to a ground level in accordance with the rising edge of a timing signal corresponding to the start of a recorded area of the information recording medium to the reproduced signal obtained by the above-described signal; and a DC component from the output of the adder. Digital information is generated by comparing a comparison voltage generation circuit that generates a comparison voltage by extracting the signal, a reproduction signal obtained by reproduction from the information recording medium, and a comparison voltage output from the comparison signal generation circuit. 1. A signal detection circuit for an optical memory device, comprising a comparator that outputs a signal. 2. In a signal detection circuit of an optical memory device that records, reproduces, or erases information by irradiating an optical information recording medium with a light beam such as a laser beam, a reproduction signal obtained by reproduction from the information recording medium a comparison voltage generation circuit that generates a comparison voltage by extracting a DC component from the information storage medium; a comparator that outputs a digital information signal by comparing a reproduction signal obtained by reproduction from the information recording medium and a comparison voltage output from the adder; 1. A signal detection circuit for an optical memory device, comprising: