JP2814917B2 - Switching power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply circuit, and more particularly to an improvement in conversion efficiency, which is a ratio of input DC power to output DC power under light load.

[0002]

2. Description of the Related Art A DC voltage is input, and is switched by a switching element to be converted into an alternating current, and then converted into a voltage by a transformer. In a switching power supply circuit to be supplied, a load current largely fluctuates and a light load is often used for a long time. Therefore, it is desired to improve the efficiency at light load and extend the usable time of the battery as the primary power supply.

Conventionally, various proposals have been made to improve the efficiency under light load. For example, Japanese Patent Application Laid-Open No.
In the device disclosed in Japanese Patent No. 3352, an intermittent switching operation is performed in a light load state, and power is supplied to a load circuit by electrostatic energy accumulated in a smoothing capacitor during a period when the switching operation is stopped. Supplying.

Further, in the device disclosed in Japanese Patent Application Laid-Open No. H2-254972, a snubber capacitor (sn
The capacity of the hub is reduced. A snubber capacitor is inserted in parallel to protect the switching element.However, in the case of a light load, the current controlled by the switching element is small, so even if the snubber capacitor is reduced, the switching element can be protected. it can. Since charging and discharging of the snubber capacitor all result in power loss, if the capacity of the snubber capacitor is reduced,
Power loss can be reduced.

[0005]

The above-mentioned conventional switching power supply circuit has the following problems. That is, in the device disclosed in JP-A-3-173352, power is supplied from the smoothing capacitor to the load during the switching operation stop period. Therefore, it is necessary to increase the capacity of the smoothing capacitor. This is an obstacle to downsizing the device. When the load current suddenly increases from the light load state, the switching from the intermittent switching state to the continuous switching state is performed immediately, but it takes time to charge the voltage of the smoothing capacitor that has decreased due to the sudden increase in the load current. Cannot respond immediately to an increase in load current. Furthermore, in this device, since an increase in load current is detected by a decrease in output voltage, there is a problem that it is not possible to improve the performance of a switching power supply circuit in order to minimize a change in output voltage.

Next, in the device disclosed in Japanese Patent Application Laid-Open No. 2-2549972, the capacitance of the snubber capacitor is reduced. However, even if the capacitance of the snubber capacitor is reduced to zero, the drain of the MOSFET used as a switching element is reduced.・
There is a problem that the charge and discharge of the parasitic capacitance between the electrodes existing between the sources and between the gate and the source causes a loss similarly to the charge and discharge of the snubber capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to solve the problems of the conventional device and to increase the capacity of a smoothing capacitor without deteriorating the output voltage regulation characteristics. And to provide a high-efficiency switching power supply circuit capable of suppressing the instantaneous drop of the output voltage when the load changes from a light load to a rated load, and further suppressing the loss caused by the parasitic capacitance of the switching element. The purpose is.

[0008]

SUMMARY OF THE INVENTION A switching power supply circuit according to the present invention comprises a primary DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, A rectifier circuit connected to the secondary winding,
A PWM control circuit for controlling a pulse width of a switching signal supplied to the switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit automatically controlled so as to keep the output voltage of the circuit constant, the switching means has an FET, and the PWM control circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. A circuit for comparing the output voltage of the load current detection circuit with a reference voltage; and when the output of the comparator indicates that the output voltage of the load current detection circuit is lower than the reference voltage, the switching signal is repeated. Means for controlling so as to reduce the frequency.

A primary DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer, A PWM control circuit for controlling a pulse width of a switching signal supplied to a switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, and the pulse width of which is controlled by the PWM control circuit. In the switching power supply circuit automatically controlled so as to keep the output voltage constant, the switching means has an FET, and the PWM control circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. And a comparator for comparing an output voltage of the load current detection circuit with a reference voltage, and an output of the comparator,
When the output voltage of the load current detection circuit is lower than the reference voltage, the amplitude VGS of the switching signal
And means for controlling so as to reduce.

A primary side DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer, A PWM control circuit for controlling a pulse width of a switching signal supplied to a switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, and the pulse width of which is controlled by the PWM control circuit. In the switching power supply circuit automatically controlled so as to keep the output voltage constant, the switching means has an FET, and the PWM control circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. And a comparator for comparing an output voltage of the load current detection circuit with a reference voltage, and an output of the comparator,
When the output voltage of the load current detection circuit indicates that the output voltage is lower than the reference voltage, means for controlling the frequency of the switching signal and reducing the amplitude VGS thereof is provided.

A DC power supply on a primary side, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer, A PWM control circuit for controlling a pulse width of a switching signal supplied to a switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, and the pulse width of which is controlled by the PWM control circuit. In the switching power supply circuit automatically controlled so as to keep the output voltage constant, the switching means is connected in parallel to the first FET by an on / off switch or disconnected from the parallel circuit by a first FET. And the switching power supply circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. If, in the case shown a comparator for comparing the output voltage of the load current detection circuit with a reference voltage, the output of the comparator, the output voltage of the load current detecting circuit is lower than the reference voltage, the second FET
And means for controlling so as to be disconnected from the parallel circuit.

A DC power supply on a primary side, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer, A PWM control circuit for controlling a pulse width of a switching signal supplied to a switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, and the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit that is automatically controlled to keep the output voltage of the rectifier circuit constant,
A smoothing capacitor is connected to a smoothing circuit having first and second smoothing chokes. A dummy load is connected to the smoothing capacitor in parallel, and the second smoothing choke is connected to the first smoothing choke by an on / off switch. Connected in parallel or disconnected from the parallel circuit, the switching power supply circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit, and an output voltage of the load current detection circuit. A comparator for comparing with a reference voltage, and means for controlling to disconnect the second smoothing choke from the parallel circuit when the output of the comparator indicates that the output voltage of the load current detection circuit is lower than the reference voltage. It is characterized by having.

A primary side DC power supply; switching means connected to the DC power supply via a primary winding of a transformer; a rectifier circuit connected to a secondary winding of the transformer; A PWM control circuit for controlling a pulse width of a switching signal supplied to a switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, and the pulse width of which is controlled by the PWM control circuit. In the switching power supply circuit automatically controlled so as to keep the output voltage constant, the switching means is connected in parallel to the first FET by an on / off switch or disconnected from the parallel circuit by a first FET. And the rectifier circuit is connected to a smoothing circuit having a smoothing capacitor and first and second smoothing chokes. A dummy load is connected in parallel to the smoothing capacitor, and the second smoothing choke is controlled by an on / off switch so as to be connected in parallel to the first smoothing choke or disconnected from the parallel circuit, and the switching power supply circuit Further, a load current detection circuit that generates a voltage representing a load current of the rectifier circuit, a comparator that compares an output voltage of the load current detection circuit with a reference voltage, and an output of the comparator is the load current detection circuit. Means for disconnecting the second FET from the parallel circuit and disconnecting the second smoothing choke from the parallel circuit when the output voltage is lower than the reference voltage.

Further, the load current detection circuit includes a resistor inserted in a path of the load current of the rectifier circuit.

Further, the load current detection circuit includes a current transformer inserted in series with the switching means and a rectifier for detecting an amplitude of a secondary voltage of the current transformer.

[0016]

In the switching power supply circuit of the present invention, when the switching element is an FET, the loss due to charging and discharging of the parasitic capacitance between the electrodes is proportional to the number of times of charging and discharging. Can be done. In a light load state, the switching frequency f
, The load current can be sufficiently supplied. Further, when the switching voltage VGS is reduced,
Loss due to charging and discharging to this voltage can be reduced. When VGS is reduced, the resistance of the FET in the ON state increases, and the loss for that increases, but the increase in loss for light loads is small.

When the parasitic capacitance between the electrodes of the FET is reduced, the loss due to the charging and discharging of the parasitic capacitance is reduced. However, the FET having a small parasitic capacitance has a small current capacity. FETs are connected in parallel to form a switching element. At light load, one F
ET was disconnected from the circuit. When using a smoothing choke, a bleeder resistor is provided so that the current flowing through the smoothing choke does not become discontinuous.To reduce the loss due to this bleeder resistance, increase the inductance of the smoothing choke at light load. And the current flowing through the bleeder resistor was reduced.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a DC power supply 1, a primary winding of a transformer 2, and a closed circuit of a switching element 5 are periodically opened and closed by the switching element 5. Is repeated. FIG. 9 shows an example of a switching waveform when the switching element is an FET. The gate drive voltage VGS, which is a voltage between the gate and the source of the FET 5, is a rectangular wave indicated by VGS in FIG.

When VGS is applied, the FET 5 is turned on, and the drain-source voltage VDS of the FET 5 becomes almost zero. The drain current ID flows through the primary winding of the transformer 2 as indicated by ID in FIG. This drain current induces a voltage in the secondary winding of the transformer 2. The voltage induced in the secondary winding of the transformer 2 is rectified by the rectifier diode 3 and charges the smoothing capacitor 4. Load current I0
Is obtained by discharging the capacitor 4.

The pulse width of the gate drive voltage VGS is PW
It is controlled by the M control circuit 6. The output voltage V0 is PW
It is compared with a reference voltage in the M control circuit 6. The pulse width is feedback-controlled by the PWM control circuit 6 so that the error voltage, which is the difference between the output voltage and the reference voltage, keeps this error voltage almost zero. In this embodiment, the load current detector 10 includes a resistor that generates a voltage VI proportional to I0. The comparator 9 compares VI with the reference voltage Vref, and when VI <Vref, the signals S1 and S2 of logic “H”
And outputs a signal of logic "L" otherwise.

When the logic of the signals S1 and S2 is "L", the control frequency f from the variable frequency oscillation circuit 7 and the control voltage from the output voltage variable auxiliary power supply circuit 8 are maintained at regular values. When the logic of the signals S1 and S2 is "H", the control frequency f is reduced, the control voltage VCC is reduced, and the switching loss of the device is reduced.

FIG. 7 is a block diagram showing an example of frequency control of the frequency variable oscillation circuit 7, in which the logic of the signal S1 is "H".
At this time, the capacitor C2 is connected in parallel with the capacitor C1, and the oscillation frequency decreases.

FIG. 10 is a circuit diagram showing the parasitic capacitance of the FET 5, where S is a source, D is a drain, and G is a gate.
There is a parasitic capacitance CDS between the drain and the source, a parasitic capacitance CGS between the gate and the source, and a parasitic capacitance CGD between the drain and the gate. During the off period of the drain current, CDS and CGD are charged to VDS. This charging requires the energy WL represented by Expression (2). WL = Coss (VDS (OFF) ) 2/2 ··· (2) However Coss = a CDS + CGD.

This energy WL is consumed inside the FET during the ON period of the drain current following the OFF period. That is, energy WL is consumed in one switching cycle. Since the switching cycle for one second is the frequency f, the switching loss can be reduced in proportion to f by lowering the control frequency.

In the flyback type switching power supply circuit as shown in FIG. 1, the maximum output is represented by Pmax = (1/2) L (IDP) ² f (1). Here, L is the inductance of the primary winding of the transformer 2 through which the current of the switching element flows, and IDP is FE
The peak value of the drain current in the ON state of T5, f
Is the control frequency, but f may be reduced because Pmax is small in a light load state.

Note that the actual capacity charged to VGS is larger than the sum of CGS and CGD. It is C
This is because the GD has a mirror effect. Therefore, the energy WG for charging the actual parasitic capacitance is represented by WG = (QG) (VGS (ON)) (3). Here, QG is a charge charged from the gate to the source during the ON period. Half of this energy is consumed when charging during the ON period, and the other half is consumed in the PWM control circuit 6 during the OFF period following this ON period. Therefore, when VGS is reduced, the loss due to QG decreases in proportion to the square of VGS. It's QGS is VGS
Because it is proportional to

When VGS is reduced, the resistance RON when the FET 5 is in the on state increases as shown in FIG.
This increase increases the resistance loss in FET5. At a light load, this increase in resistance loss is smaller than the decrease in loss expected from equation (3).

FIG. 5 is a diagram showing the relationship between load current and power loss in a conventional device, where W1 is a power loss proportional to the square of the load current, and W2 is a power loss irrelevant to the load current. In the light load region, the loss W2 is larger than the load current, and the conversion efficiency in this region is reduced.

FIG. 6 is a diagram showing the relationship between the load current and the power loss in the device of the present invention. W1 is the same in FIGS. 5 and 6, and W2 is the same as in FIG. 5 in the rated load current region (a). It is the same in FIG. When the load current reaches the point (b), the output logic of the comparator 9 changes, f decreases, VGS decreases, and W
Decrease 2 Therefore, the conversion efficiency of the device of the present invention in the light load region (a) is improved. The conversion efficiency of the device of the present invention is as shown by a solid line P in FIG. The conversion efficiency of the conventional device is as shown by the dotted line Q in FIG.

FIG. 2 shows a modification of the embodiment shown in FIG. 1. A current flowing in the primary winding of the transformer 2 is transformed by a current transformer 11 as a load current detecting circuit, and the secondary side of the current transformer 11 is changed. The rectified voltage is used as load current detection. FIG. 3 shows another modification of the embodiment shown in FIG. 1. The switching power supply circuit shown in FIG. 3 differs from the switching power supply circuit shown in FIG. The circuit is of a forward type, and has a resonance frequency due to the magnetic saturation of the transformer 2 and the secondary circuit having the flywheel diode 12, the smoothing choke 13, and the smoothing capacitor 4 connected to the rectifying diode 3 to have a resonance frequency. , The control frequency f cannot be freely changed.

In this case, only VGS shown in the equation (3) drops in the output voltage variable auxiliary power supply circuit 8. The fixed frequency oscillator 18 converts the fixed frequency signal to the PWM control circuit 6.
To supply. It goes without saying that the reduction of the control frequency f and the reduction of the VGS can be performed independently of each other, and each has an effect of reducing the loss independently.

FIG. 4 is a block diagram showing another embodiment of the present invention. In the drawing, the same reference numerals as those in FIGS. 1 and 3 denote the same or corresponding parts, and two FETs 51 and 52 are used as switching elements. In the rated load region, the two FETs are connected in parallel. FE in light load area
T52 is disconnected from the circuit by the on / off switches 14 and 15. When this is separated, the capacity Coss of the equation (2) and the QG of the equation (3) are reduced, and the loss at light load can be reduced. The switching power supply circuit shown in FIG. 4 is a forward type like the circuit of FIG. 3, and a signal of a fixed frequency is supplied from the oscillator 18. Although it is possible to lower VGS in the light load region as in the embodiment of FIG. 3, this is not performed in the embodiment shown in FIG.

In the embodiment shown in FIG. 4, the smoothing choke is 2
In the rated load region, 132 is connected in parallel with 131, but in the light load region, the connection is cut off by the on / off switch 16 from the parallel connection. In order for the switching power supply circuit to operate stably, the current flowing through the smoothing choke must not be discontinuous. Therefore, a dummy load 17 is provided. The on / off switch 16 increases the reactance of the smoothing choke in the light load region, reduces the current flowing through the dummy load 17, and reduces the loss.

FIG. 12 is a waveform diagram showing a current waveform flowing through the smoothing choke and a current value flowing through the dummy load. There is a relationship of E = L (dI / dt) (4) between the current I flowing through the choke and the voltage E across it. Here, L is the inductance of the choke. If the voltage E at both ends of the choke is a rectangular wave (not shown), the current I has a waveform rising linearly and falling linearly as shown by the choke current IL in FIG. The slope of this straight line is L
Is inversely proportional to At the rated load current I0, the average value of IL is I
Equal to zero. As the load current decreases, the current in the choke decreases, but the slope of the current does not change. Since the current in the choke must not be discontinuous, the dotted line S in FIG.
The minimum value is zero, as shown in FIG.

As in the conventional device, in order for the current shown by the dotted line S in FIG. 12 to flow, when the load current becomes 0, S
Must flow through the dummy load 17. In the present invention, the choke 132 is used in the light load region.
Is cut off from the circuit, the inductance of the choke increases, the slope of the current decreases, and as shown by the solid line T in FIG. 12, the average value of the current decreases, and the loss due to the dummy load decreases.

In the embodiment shown in FIG. 4, the disconnection of the FET 52 and the disconnection of the choke 132 are performed simultaneously.
It goes without saying that each effect can be obtained even if one of them is performed alone. Also, the choke 131 is connected in parallel.
A plurality of chokes 132 and on / off switches 16
In response to a decrease in the load current detected by the comparator 9.
Alternatively, the on / off switch may be controlled. Further, the current transformer 11 of FIG. 2 can be used as the load current detection circuit of the embodiment shown in FIGS.

[0037]

As described above, in the switching power supply circuit of the present invention, the repetition frequency of the switching signal is reduced in the light load region of the switching power supply, the amplitude VGS of the switching signal is reduced, and the parasitic capacitance of the switching element is reduced. Since it is possible to perform a loss reduction measure that can be performed by the switching power supply device, such as reducing the inductance and increasing the inductance of the smoothing choke, the conversion efficiency can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a modification of FIG.

FIG. 3 is a block diagram showing another modification of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between load current and loss of a conventional device.

FIG. 6 is a diagram showing the relationship between load current and loss of the device of the present invention.

FIG. 7 is a circuit diagram showing a part of the variable frequency oscillation circuit of FIG. 1;

FIG. 8 is an explanatory diagram showing an improvement in conversion efficiency according to the present invention.

FIG. 9 is a waveform chart showing voltages of respective parts of the switching element of the device of the present invention.

FIG. 10 is a circuit diagram showing an equivalent circuit of a switching element of the device of the present invention.

FIG. 11 is a diagram showing a relationship between a switching voltage of a switching element of the device of the present invention and an internal resistance.

FIG. 12 is a waveform diagram showing a current waveform of the smoothing choke of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DC power supply 2 Transformer 3 Rectifier diode 4 Smoothing capacitor 5 Switching element 6 PWM control circuit 7 Variable frequency oscillation circuit 8 Output voltage variable auxiliary power supply circuit 9 Comparator 10 Load current detection circuit 11 Current transformer 12 Flywheel diode 13 Smooth choke 14, 15, 16 ON / OFF switch 17 Dummy load 131, 132 Smooth choke

Claims (6)

(57) [Claims] 1. A primary DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, and a rectifier circuit connected to a secondary winding of the transformer.
A PWM control circuit for controlling a pulse width of a switching signal supplied to the switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit automatically controlled so as to keep the output voltage of the circuit constant, the switching means has an FET, and the PWM control circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. A circuit for comparing an output voltage of the load current detection circuit with a reference voltage; and an amplitude of the switching signal when an output of the comparator indicates that an output voltage of the load current detection circuit is lower than the reference voltage. Means for controlling to reduce VGS, comprising: Source circuit. 2. A primary DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer,
A PWM control circuit for controlling a pulse width of a switching signal supplied to the switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit automatically controlled so as to keep the output voltage of the circuit constant, the switching means has an FET, and the PWM control circuit further includes a load current detection circuit for generating a voltage representing a load current of the rectifier circuit. A circuit for comparing an output voltage of the load current detection circuit with a reference voltage; and a frequency of the switching signal when an output of the comparator indicates that an output voltage of the load current detection circuit is lower than the reference voltage. And means for controlling to reduce its amplitude VGS. Switching power supply circuit to the butterflies. 3. A DC power source on a primary side, switching means connected to the DC power source via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer,
A PWM control circuit for controlling a pulse width of a switching signal supplied to the switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit automatically controlled so as to keep the output voltage of the circuit constant, the rectifier circuit is connected to a smoothing circuit having a plurality of smoothing chokes connected in parallel with the smoothing capacitor, and is connected in parallel to the smoothing capacitor. A dummy load is connected, each of the plurality of smoothing chokes is controlled by an on / off switch so as to be disconnected from the smoothing circuit, and the switching power supply circuit further includes a load current detection for generating a voltage representing a load current of the rectifier circuit. Circuit and the output voltage of this load current detection circuit as a reference voltage And a comparator that compares the output voltage of the load current detection circuit with the reference voltage and reduces the number of the plurality of smoothing chokes connected in parallel to the smoothing circuit. A switching power supply circuit, comprising: 4. A primary DC power supply, switching means connected to the DC power supply via a primary winding of a transformer, a rectifier circuit connected to a secondary winding of the transformer,
A PWM control circuit for controlling a pulse width of a switching signal supplied to the switching means, wherein the switching signal is a rectangular wave train having a repetition frequency f and an amplitude VGS, the pulse width of which is controlled by the PWM control circuit. In a switching power supply circuit automatically controlled so as to keep an output voltage of the circuit constant, the switching means is connected in parallel to the first FET by an on / off switch or disconnected from the parallel circuit by an on / off switch. The rectifier circuit is connected to a smoothing circuit having a plurality of smoothing chokes connected in parallel with a smoothing capacitor, a dummy load is connected in parallel to the smoothing capacitor, and the plurality of smoothing chokes is connected to the smoothing capacitor. Each of which is separated from the smoothing circuit by an on / off switch. The switching power supply circuit is further controlled by a comparator that compares an output voltage of the load current detection circuit with a reference voltage, and an output of the comparator indicates that an output voltage of the load current detection circuit is lower than the reference voltage. Means for controlling so as to reduce the number of the plurality of smoothing chokes connected in parallel to the smoothing circuit, and for controlling the second FET to be disconnected from the parallel circuit. Power circuit. 5. The rectifier circuit according to claim 5, wherein the load current detection circuit is a rectifier circuit.
Characterized by having a resistor inserted in the path of the load current
The switching power supply circuit according to any one of claims 1 to 4,
Road. 6. The switch according to claim 1, wherein the load current detection circuit includes a switch.
Current transformer inserted in series with the
A rectifier that detects the amplitude of the secondary voltage of the rent transformer
5. The switch according to claim 1, wherein
Switching power supply circuit.