JP2814704B2 - Interrupt control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a miniaturized circuit, a central processing unit (hereinafter referred to as a CPU).
), And an interrupt control circuit used for omitting instructions.

FIG. 4 shows the configuration of a conventional interrupt control circuit. In FIG. 1, reference numeral 1 denotes a flip-flop circuit which holds an interrupt factor a and outputs the same.
It has a function of resetting the interrupt holding factor a by an interrupt reset instruction b generated from a not shown (not shown).

2 is a flip-flop circuit that holds and outputs an interrupt mask instruction c generated by the CPU, and 3 is an input of an interrupt factor a from the flip-flop circuit 1 and an interrupt mask instruction c from the flip-flop circuit 2. And controls the output of the interrupt factor a by the flip-flop circuit 1.

 Next, the operation of the above conventional example will be described.

When an interrupt factor occurs, the flip-flop circuit 1
Holds the interrupt factor a, and the output to the AND circuit 3 becomes a signal "1" indicating this. At this time, when there is no output of the interrupt mask instruction c from the CPU to the flip-flop circuit 2, that is, when the interrupt is accepted, the output from the flip-flop circuit 2 to the AND circuit 3 becomes a signal “1” indicating this. Become.

Then, the output of the AND circuit 3 becomes “1” because the input signals from both the flip-flop circuits 1 and 2 are both “1”, whereby an interrupt of the interrupt factor a occurs.

On the other hand, when the interrupt mask instruction c is output from the CPU to the flip-flop circuit 2 when the interrupt factor a is held in the flip-flop circuit 1, that is, when the interrupt is not accepted, the AND circuit is output from the flip-flop circuit 2. The output for No. 3 is a signal “0” indicating this.

Then, the output of the AND circuit 3 is “1” because the input signal from the flip-flop circuit 1 is “1” and the input signal from the flip-flop circuit 2 is “0”. The output of the interrupt factor a held in the flip-flop circuit 1 is controlled so that the interrupt of the interrupt factor a does not occur.

At the same time, the CPU outputs to the flip-flop circuit 1 an interrupt reset instruction b for resetting the interrupt factor a held in the flip-flop circuit 1, and the flip-flop circuit 1 Is reset.

Thus, even in the above-described conventional interrupt control circuit, the interrupt factor can be controlled by outputting the interrupt reset instruction b and the interrupt mask instruction c from the CPU.

However, in the above-described conventional interrupt control circuit, it is necessary to independently output two types of instructions from the CPU, an interrupt reset instruction b and an interrupt mask instruction c (see FIG. 5). There was a problem that control was complicated.

Further, in the above-described conventional interrupt control circuit, one AND circuit 3 is required in addition to the two flip-flop circuits 1 and 2, and there is a problem that the circuit configuration is complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide an interrupt control circuit capable of simplifying control by omitting instruction contents from a CPU.

Means for Solving the Problems In order to achieve the above object, the present invention provides a first flip-flop circuit which holds and outputs an interrupt reset / mask instruction from a CPU when the instruction is input, An interrupt reset / mask instruction from the flip-flop circuit and an external interrupt factor are input, and the interrupt factor input based on the contents of the interrupt reset / mask instruction from the first flip-flop circuit is output;
And a second flip-flop circuit for resetting and masking.

Operation The present invention can simplify the control by omitting the instruction content from the CPU by the above configuration,
In addition, the circuit configuration can be simplified to reduce the size of the circuit.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an interrupt control circuit according to one embodiment of the present invention.

In FIG. 1, reference numeral 21 denotes a first flip-flop circuit which holds and outputs an interrupt reset / mask instruction D from the CPU when it is input; The second in which an interrupt reset / mask instruction D and an external interrupt factor A are input
Flip-flop circuit.

The second flip-flop circuit 22 indicates that the content of the interrupt reset / mask command D from the first flip-flop circuit 21 resets and masks the interrupt factor A (H of the signal b in FIG. 3). When things are
The interrupt factor A input to the flip-flop circuit 22 is not reset and held.

The content of the interrupt reset / mask instruction D from the first flip-flop circuit 21 is determined by the interrupt factor A.
Not reset and mask (L of signal b in FIG. 3)
When the flip-flop circuit
The interrupt factor A input to 22 is held and output.

 Next, the operation of the above embodiment will be described.

From the first flip-flop circuit 21 to the second flip-flop circuit 22, the second flip-flop circuit
That the interrupt factor A input to the second flip-flop circuit 22 is not reset and masked (L of the signal b in FIG. 3) or that the interrupt factor A input to the second flip-flop circuit 22 is reset and masked (No. H) of the signal b in FIG.
Interrupt reset / mask instruction D indicating either
Is output.

Here, when the content of the interrupt reset / mask instruction D indicates that the interrupt factor A is not reset and masked (L of the signal b in FIG. 3), it is input to the second flip-flop circuit 22. Interrupt factor A
Is held by the second flip-flop circuit 22, and an interrupt is generated with this holding.

On the other hand, the interrupt reset / mask instruction D
Indicates that the interrupt factor A is reset and masked (H of the signal b in FIG. 3), the second flip-flop circuit 22 resets the interrupt factor A input thereto. As a result, the interrupt factor A is masked. Therefore, in this case, no interrupt occurs.

Next, a state in which the interrupt factor A is already held in the second flip-flop circuit 22 and an interrupt has occurred will be described.

In the same state, the content of the interrupt reset / mask instruction D input to the second flip-flop circuit 22 is CP
Under the control of the U side, the interrupt factor A is reset and masked from the signal indicating that the interrupt factor A is not reset and masked (L of the signal b in FIG. 3) (b in FIG. 3).
When the signal changes to a signal indicating H), the interrupt factor A held in the second flip-flop circuit 22 is reset, and the generation of the interrupt stops.

If the contents of the interrupt reset / mask instruction D are instantaneously changed such that the interrupt factor A is not reset and masked → not → not performed, a so-called reset operation can be achieved. Is changed to indicate that the interrupt factor A is to be reset and masked, and if this state is continued under the control of the CPU, a so-called masking operation can be achieved as a result.

As described above, according to the interrupt control circuit of the present embodiment, the first flip-flop circuit 21 holds the interrupt reset / mask signal from the CPU, thereby
The instruction from U can be unified, and this instruction can be performed at once.

In this embodiment, the interrupt reset / mask signal is input to the first flip-flop circuit 21.
As shown in FIG. 2, the first flip-flop circuit 21
By inputting the power failure detection signal E from the CPU, unnecessary interruption can be prevented from occurring at the time of power failure and recovery from the power failure of the device using this interrupt control circuit.

Effects of the Invention As described above, according to the present invention, when an interrupt reset / mask command is input from a CPU, the first flip-flop circuit that holds and outputs the command, A second flip-flop circuit which receives an interrupt reset / mask instruction and an external interrupt factor and outputs, resets and masks the interrupt factor input based on the contents of the interrupt reset / mask instruction from the first flip-flop circuit Thus, there is an effect that the configuration can be simplified by unifying the contents of instructions from the CPU.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an interrupt control circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a circuit configuration of an interrupt control circuit according to another embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing a circuit configuration of a conventional interrupt control circuit, and FIG. 5 is a signal waveform diagram of a conventional interrupt control circuit according to one embodiment of the present invention. 21: first flip-flop circuit, 22: second flip-flop circuit, A: interrupt cause, D: interrupt reset / mask instruction.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/46 G06F 13/24

Claims (1)

(57) [Claims] A first flip-flop circuit for holding and outputting an interrupt reset / mask instruction from a central processing unit when the interrupt reset / mask instruction is input; The signal from the flip-flop circuit holds the interrupt factor, which is input as a signal indicating that resetting and masking are not performed, and the signal from the first flip-flop circuit is a signal indicating resetting and masking. And resetting the interrupt factor which is input when the signal from the first flip-flop circuit changes from a signal indicating not resetting or masking to a signal indicating resetting or masking. An interrupt control circuit comprising: a second flip-flop circuit for resetting a factor.